DATA PROCESSING APPARATUS FOR TRANSMITTING/RECEIVING INDICATION INFORMATION OF PIXEL DATA GROUPING SETTING VIA DISPLAY INTERFACE AND RELATED DATA PROCESSING METHOD

Abstract

A data processing apparatus includes a compression circuit and an output interface. The compression circuit generates a plurality of compressed pixel data groups by compressing pixel data of a plurality of pixels of a picture based on a pixel data grouping setting of the picture. The output interface records indication information in an output bitstream, and outputs the output bitstream via a display interface. The output bitstream is derived from the compressed pixel data groups. The indication information is set in response to the pixel data grouping setting employed by the compression circuit.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. provisional application No. 61/865,345, filed on Aug. 13, 2013 and incorporated herein by reference.

BACKGROUND

The disclosed embodiments of the present invention relate to transmitting and receiving data over a display interface, and more particularly, to a data processing apparatus for transmitting/receiving indication information of a pixel data grouping setting over a display interface and a related data processing method.

A display interface is disposed between a first chip and a second chip to transmit display data from the first chip to the second chip for further processing. For example, the first chip may be a host application processor, and the second chip may be a driver integrated circuit (IC). The display data may be single view data for two-dimensional (2D) display or multiple view data for three-dimensional (3D) display. When a display panel supports a higher display resolution, 2D/3D display with higher resolution can be realized. Hence, the display data transmitted over the display interface would have a larger data size/data rate, which increases the power consumption of the display interface inevitably. If the host application processor and the driver IC are both located at a portable device (e.g., a smartphone) powered by a battery device, the battery life is shortened due to the increased power consumption of the display interface. Thus, there is a need for an innovative design which can effectively reduce the power consumption of the display interface.

SUMMARY

In accordance with exemplary embodiments of the present invention, a data processing apparatus for transmitting/receiving indication information of a pixel data grouping setting over a display interface and a related data processing method are proposed.

According to a first aspect of the present invention, an exemplary data processing apparatus is disclosed. The exemplary data processing apparatus includes a compression circuit and an output interface. The compression circuit is configured to generate a plurality of compressed pixel data groups by compressing pixel data of a plurality of pixels of a picture based on a pixel data grouping setting of the picture. The output interface is configured to record indication information in an output bitstream and outputting the output bitstream via a display interface, wherein the output bitstream is derived from the compressed pixel data groups, and the indication information is set in response to the pixel data grouping setting employed by the compression circuit.

According to a second aspect of the present invention, an exemplary data processing apparatus is disclosed. The exemplary data processing apparatus includes a plurality of de-compressors and an input interface. Each of the de-compressors is configured to decompress a compressed pixel data group derived from an input bitstream when selected. The input interface is configured to receive the input bitstream via a display interface, and parse indication information included in the input bitstream, wherein multiple de-compressors are selected from the de-compressors according to the indication information.

According to a third aspect of the present invention, an exemplary data processing method is disclosed. The exemplary data processing method includes: generating a plurality of compressed pixel data groups by compressing pixel data of a plurality of pixels of a picture based on a pixel data grouping setting of the picture; and recording indication information in an output bitstream, and outputting the output bitstream via a display interface, wherein the output bitstream is derived from the compressed pixel data groups, and the indication information is set in response to the pixel data grouping setting.

According to a fourth aspect of the present invention, an exemplary data processing method is disclosed. The exemplary data processing method includes: receiving an input bitstream via a display interface; parsing indication information included in the input bitstream; selecting multiple de-compressors from a plurality of de-compressors according to the indication information; and utilizing the selected multiple de-compressors to de-compress a plurality of compressed pixel data groups derived from the input bitstream, respectively.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a data processing system according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating exemplary pixel data grouping patterns each dividing one picture in a first direction.

FIG. 3 is a diagram illustrating exemplary pixel data grouping patterns each dividing one picture in a second direction.

FIG. 4, which is a diagram illustrating a data structure of an output bitstream generated from an application processor to a driver IC according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating an example of information handshaking between the application processor and the driver IC.

FIG. 6 is a flowchart illustrating a control and data flow of a data processing system shown in FIG. 1 according to an embodiment of the present invention.

DETAILED DESCRIPTION

Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

The present invention proposes applying data compression to a display data and then transmitting a compressed display data over a display interface. As the data size/data rate of the compressed display data is smaller than that of the original un-compressed display data, the power consumption of the display interface is reduced correspondingly. However, there may be a throughput bottleneck for a compression/de-compression system due to long data dependency of previous compressed/reconstructed data. To minimize or eliminate the throughput bottleneck of the compression/de-compression system, the present invention further proposes a data parallelism design. In this way, multiple compressed pixel data groups are independently generated at a transmitting end, and multiple de-compressed pixel data groups are independently generated at a receiving end. The de-compression configuration employed by the receiving end is required to be compliant with the compression configuration employed by the transmitting end; otherwise, the receiving end fails to correctly de-compress the compressed display data. The present invention further proposes transmitting/receiving indication information of a pixel data grouping setting via the display interface, such that the de-compression configuration of the receiving end can be correctly configured based on the received indication information. Further details will be described as below.

FIG. 1 is a block diagram illustrating a data processing system according to an embodiment of the present invention. The data processing system 100 includes a plurality of data processing apparatuses such as an application processor 102 and a driver integrated circuit (IC) 104. The application processor 102 and the driver IC 104 may be implemented in different chips, and the application processor 102 communicates with the driver IC 104 via a display interface 103. In this embodiment, the display interface 103 may be a display serial interface (DSI) standardized by a Mobile Industry Processor Interface (MIPI) or an embedded display port (eDP) standardized by a Video Electronics Standards Association (VESA).

The application processor 102 is coupled between the display interface 103 and a data source 105, and supports compressed data transmission. The application processor 102 receives an input display data from the external data source 105, where the input display data may be image data or video data that includes pixel data DI of a plurality of pixels of a picture to be processed. By way of example, but not limitation, the data source 105 may be a camera sensor, a memory card or a wireless receiver. As shown in FIG. 1, the application processor 102 includes a display controller 111, an output interface 112 and a processing circuit 113. The processing circuit 113 includes circuit elements required for processing the pixel data DI to generate a plurality of compressed pixel data groups DG₁′-DG_N′, where N is a positive integer. For example, the processing circuit 113 has a compression circuit 114 and other circuitry 117. The compression circuit 114 may have a mapper/splitter, a plurality of compressors, etc. The other circuitry 115 may have a display processor, additional image processing element (s), etc. The display processor may perform image processing operations, including scaling, rotating, etc. For example, the input display data provided by the data source 105 may be bypassed or processed by the additional image processing element (s) located before the display processor to generate a source display data, and then the display processor may process the source display data to generate the pixel data DI to the compression circuit 114. In other words, the pixel data DI to be processed by the compression circuit 114 may be directly provided from the data source 105 or indirectly obtained from the input display data provided by the data source 105. The present invention has no limitation on the source of the pixel data DI.

Regarding the compression circuit 114, it may use the mapper/splitter to split the pixel data DI of one picture into N pixel data groups according to a pixel data group setting DG_SET. Next, the compression circuit 114 may enable N compressors selected from a plurality of pre-built compressors to compress the N pixel data groups to generate the compressed pixel data groups DG₁′-DG_N′, respectively. Specifically, the number of enabled compressors depends on the number of pixel data groups. In addition, each of the enabled compressors may employ a lossless compression algorithm or a lossy compression algorithm, depending upon the actual design consideration. In this embodiment, compression operations performed by the enabled compressors are independent of each other. In this way, the compression throughput of the application processor 102 can be improved due to data parallelism.

The output interface 112 is configured to pack/packetize the compressed pixel data groups DG₁′-DG_N′ into at least one output bitstream according to the transmission protocol of the display interface 103, and transmit the at least one output bitstream to the driver IC 104 via the display interface 103. By way of example, one bitstream BS may be generated from the application processor 102 to the driver IC 104 via one display port of the display interface 103.

Regarding the driver IC 104, it communicates with the application processor 102 via the display interface 103. In this embodiment, the driver IC 104 is coupled between the display interface 103 and a display panel 106, and supports compressed data reception. By way of example, the display panel 106 may be implemented using any 2D/3D display device. When the application processor 102 transmits compressed display data (e.g., compressed pixel data groups DG₁′-DG_N′ packed in the bitstream BS) to the driver IC 104, the driver IC 104 is configured to receive the compressed display data from the display interface 103 and drive the display panel 106 according to de-compressed display data derived from de-compressing the compressed display data.

As shown in FIG. 1, the driver IC 104 includes a driver IC controller 121, an input interface 122 and a processing circuit 123. The input interface 122 is configured to receive at least one input bitstream from the display interface 103 (e.g., the bitstream BS received by one display port of the display interface 103), and un-pack/un-packetize the at least one input bitstream into a plurality of compressed pixel data groups of a picture (e.g., N compressed pixel data groups). It should be noted that, if there is no error introduced during the data transmission, the compressed pixel data groups generated from the input interface 122 should be identical to the compressed pixel data groups DG₁′-DG_N′ received by the output interface 112.

The processing circuit 123 may include circuit elements required for driving the display panel 106. For example, the processing circuit 123 has a plurality of de-compressors (e.g., M de-compressors 124_1-124_M, where M is a positive integer and M≧N), a plurality of switches (e.g., M switches 126_1-126_M), and other circuitry 125. The other circuitry 125 may have a de-mapper/combiner, a display buffer, additional image processing element (s), etc. Each of the de-compressors 124_1-124_M is configured to decompress a compressed pixel data group when selected. It should be noted that the number of switches 126_1-126_M is equal to the number of de-compressors 124_1-124_M. Hence, each of the switches 126_1-126_N controls whether a corresponding de-compressor is selected for data de-compression. In this embodiment, the switches 126_1-126_M are respectively controlled by a plurality of enable signals EN₀-EN_M generated from the driver IC controller 121. When an enable signal has a first logic value (e.g., ‘1’), a corresponding switch is enabled (i.e., switched on) to make a following de-compressor selected; and when the enable signal has a second logic value (e.g., ‘0’), the corresponding switch is disabled (i.e., switched off) to make a following de-compressor unselected.

The driver IC 104 has multiple pre-built de-compressors (e.g., multiple cores) so as to realize different de-compression capability (or throughput). In this embodiment, since the input interface 122 obtains N compressed pixel data groups from de-packing/de-packetizing the bitstream BS, the driver IC controller 121 is configured to select N de-compressors from the de-compressors 124_1-124_M for data de-compression. In this embodiment, the unselected (M−N) de-compressors may be clock-gated for power saving. The selected de-compressors are used to de-compress the N compressed pixel data groups to generate a plurality of de-compressed pixel data groups, respectively. In this embodiment, the de-compression operations performed by the selected de-compressors are independent of each other. In this way, the de-compression throughput is improved due to data parallelism.

The de-compression algorithm employed by each of the selected de-compressors in the driver IC 104 should be properly configured to match the compression algorithm employed by each of the compressors in the compression circuit 114. In other words, the selected de-compressors are configured to perform lossless de-compression when the compressors in the compression circuit 114 are configured to perform lossless compression; and the selected de-compressors are configured to perform lossy de-compression when the compressors in the compression circuit 114 are configured to perform lossy compression.

The de-mapper/combiner in the other circuit 125 is configured to merge the de-compressed pixel data groups into pixel data DO of a plurality of pixels of a reconstructed picture based on the pixel data grouping setting DG_SET that is employed by a mapper/splitter in the compression circuit 114. The driver IC 104 drives the display panel 106 according to the pixel data DO of the reconstructed picture.

The pixel data group setting DG_SET is related to the number of pixel data groups processed by the compression circuit 114. In other words, the pixel data group setting DG_SET is related to the number of enabled compressors in the compression circuit 114. In this embodiment, the pixel data grouping setting DG_SET employed by the compression circuit 114 is transmitted from the application processor 102 to the driver IC 104 via an in-band channel (i.e., display interface 103). Specifically, the display controller 111 controls the operation of the application processor 102, and the driver IC controller 121 controls the operation of the driver IC 104. Hence, the display controller 111 may first check a de-compression capability and requirement of the driver IC 104, and then determine the number of pixel data groups in response to a checking result. In addition, the display controller 111 may further determine the pixel data grouping setting DG_SET employed by the compression circuit 114 to generate the pixel data groups that satisfy the de-compression capability and requirement of the driver IC 104, and transmit the pixel data grouping setting DG_SET over display interface 103. When receiving a query issued from the display controller 111, the driver IC controller 121 informs the display controller 111 of the de-compression capability and requirement of the driver IC 104. In addition, when receiving the pixel data grouping setting DG_SET from display interface 103, the driver IC controller 121 refers to the received pixel data grouping setting DG_SET to properly set the enable signals EN₁-EN_M, such that multiple de-compressors are selected for data de-compression.

For example, the application processor 102 may refer to information of the de-compression capability and requirement informed by the driver IC 104 to decide the throughput P1 (pixels per clock cycle) of one de-compressor in the driver IC 104 and the target throughput requirement P2 (pixels per clock cycle) of the display panel 106 driven by the driver IC 104. Assume that the throughput of one compressor in the application processor is also P1 (pixels per clock cycle). When P2/P1 is not greater than one, this means that using a single compressor at the AP side and a single de-compressor at the driver IC side is capable of meeting the throughput requirement. Hence, the proposed data parallelism scheme is inactivated, and the conventional compression and de-compression is performed. In this case, the enable signals EN₁-EN₄ may be set by {1, 0, 0, 0} for allowing a single de-compressor to be enabled. When P2/P1 is greater than one, this means that using a single compressor at the AP side and a single de-compressor at the driver IC side is unable to meet the throughput requirement. Hence, the proposed data parallelism scheme is activated. In addition, the number of compressors enabled in the application processor 102 and the number of de-compressors enabled in the driver IC 102 may be determined based on the value of P2/P1 (which will be considered by the display controller 111 to determine the pixel data grouping setting DG_SET).

The present invention proposes several pixel data grouping patterns that can be used to split pixel data of a plurality of pixels of one picture into multiple pixel data groups. FIG. 2 is a diagram illustrating exemplary pixel data grouping patterns each dividing one picture in a first direction. Suppose that the number of de-compressors 124_1-124_M implemented in the driver IC 104 is four (i.e., M=4). Hence, the four enable signals EN₁-EN₄ should be properly set to decide which de-compressors should be used for de-compression. When the pixel data grouping pattern in sub-diagram (A) of FIG. 2 is employed, the pixel data grouping setting DG_SET is set by the display controller 111 to instruct the mapper/splitter in the compression circuit 114 to split one picture with a resolution of W×H into four sub-pictures A₁, A₂, A₃, A₄ each having a resolution of (W/4)×H. Hence, the number of compressed pixel data groups DG₁′-DG_N′ generated from the compression circuit 114 is equal to four (i.e., N=4). For example, the compression circuit 114 enables four compressors to compress pixel data of the sub-pictures A₁-A₄ into four compressed pixel data groups, respectively. Hence, when receiving the pixel data grouping setting DG_SET, the driver IC controller 121 sets the enable signals EN₁-EN₄ by {1, 1, 1, 1}, such that four de-compressors are selected to decompress the four compressed pixel data groups, respectively.

When the pixel data grouping pattern in sub-diagram (B) of FIG. 2 is employed, the pixel data grouping setting DG_SET is set by the display controller 111 to instruct the mapper/splitter in the compression circuit 114 to split one picture with a resolution of W×H into three sub-pictures A₁, A₂, A₃ each having a resolution of (W/3)×H. Hence, the number of compressed pixel data groups DG₁′-DG_N′ generated from the compression circuit 114 is equal to three (i.e., N=3). For example, the compression circuit 114 enables three compressors to compress pixel data of the sub-pictures A₁-A₃ into three compressed pixel data groups, respectively. Hence, when receiving the pixel data grouping setting DG_SET, the driver IC controller 121 sets the enable signals EN₁-EN₄ by {1, 1, 1, 0}, such that three de-compressors are selected to decompress the three compressed pixel data groups, respectively.

When the pixel data grouping pattern in sub-diagram (C) of FIG. 2 is employed, the pixel data grouping setting DG_SET is set by the display controller 111 to instruct the mapper/splitter in the compression circuit 114 to split one picture with a resolution of W×H into two sub-pictures A₁ and A₂ each having a resolution of (W/2)×H. Hence, the number of compressed pixel data groups DG₁′-DG_N′ generated from the compression circuit 114 is equal to two (i.e., N=2). For example, the compression circuit 114 enables two compressors to compress pixel data of the sub-pictures A₁ and A₂ into two compressed pixel data groups, respectively. Hence, when receiving the pixel data grouping setting DG_SET, the driver IC controller 121 sets the enable signals EN₁-EN₄ by {1, 1, 0, 0}, such that two de-compressors are selected to decompress the two compressed pixel data groups, respectively.

In above exemplary pixel data grouping patterns shown in FIG. 2, each pixel row of a picture is divided into multiple sections, while each pixel column of the same picture remains intact. Alternatively, each pixel column of a picture may be divided into multiple sections, while each pixel row in the same picture may remain intact. FIG. 3 is a diagram illustrating exemplary pixel data grouping patterns each dividing one picture in a second direction. When the pixel data grouping pattern in sub-diagram (A) of FIG. 3 is employed, the pixel data grouping setting DG_SET is set by the display controller 111 to instruct the mapper/splitter in the compression circuit 114 to split one picture with a resolution of W×H into four sub-pictures B₁, B₂, B₃, B₄ each having a resolution of W×(H/4). Hence, the number of compressed pixel data groups DG₁′-DG_N′ generated from the compression circuit 114 is equal to four (i.e., N=4). For example, the compression circuit 114 enables four compressors to compress pixel data of the sub-pictures B₁-B₄ into four compressed pixel data groups, respectively. Hence, when receiving the pixel data grouping setting DG_SET, the driver IC controller 121 sets the enable signals EN₁-EN₄ by {1, 1, 1, 1}, such that four de-compressors are selected to decompress the four compressed pixel data groups, respectively.

When the pixel data grouping pattern in sub-diagram (B) of FIG. 3 is employed, the pixel data grouping setting DG_SET is set by the display controller 111 to instruct the mapper/splitter in the compression circuit 114 to split one picture with a resolution of W×H into three sub-pictures B₁, B₂, B₃ each having a resolution of W×(H/3). Hence, the number of compressed pixel data groups DG₁′-DG_N′ generated from the compression circuit 114 is equal to three (i.e., N=3). For example, the compression circuit 114 enables three compressors to compress pixel data of the sub-pictures B₁-B₃ into three compressed pixel data groups, respectively. Hence, when receiving the pixel data grouping setting DG_SET, the driver IC controller 121 sets the enable signals EN₁-EN₄ by {1, 1, 1, 0}, such that three de-compressors are selected to decompress the three compressed pixel data groups, respectively.

When the pixel data grouping pattern in sub-diagram (C) of FIG. 3 is employed, the pixel data grouping setting DG_SET is set to instruct the mapper/splitter in the compression circuit 114 to split one picture with a resolution of W×H into two sub-pictures B₁ and B₂ each having a resolution of W×(H/2). Hence, the number of compressed pixel data groups DG₁′-DG_N′ generated from the compression circuit 114 is equal to two (i.e., N=2). For example, the compression circuit 114 enables two compressors to compress pixel data of the sub-pictures B₁ and B₂ into two compressed pixel data groups, respectively. Hence, when receiving the pixel data grouping setting DG_SET, the driver IC controller 121 sets the enable signals EN₁-EN₄ by {1, 1, 0, 0}, such that two de-compressors are selected to decompress the two compressed pixel data groups, respectively.

As shown in FIG. 2, the horizontal image partitioning is applied to a picture, thus resulting in multiple sub-pictures arranged horizontally in the picture. As shown in FIG. 3, the vertical image partitioning is applied to a picture, thus resulting in multiple sub-pictures arranged vertically in the picture. However, these are for illustrative purposes only, and are not meant to be limitations of the present invention. In practice, the present invention has no limitation on the design of the pixel data grouping pattern. For example, one picture may be split into sub-pictures based on a line-by-line interleaving pattern. In this way, each sub-picture is composed of pixels of one pixel line (e.g., a pixel row or a pixel column). For another example, one picture may be split into sub-pictures based on a checkerboard pattern. In this way, each sub-picture is composed of pixels of one A×B block, where A and B are positive integers, and A may be equal to or different from B. These alternative pixel data grouping pattern designs all fall within the scope of the present invention.

In this embodiment, the output interface 112 records indication information INF of the pixel data grouping setting DG_SET by setting a command set in a payload portion of the output bitstream transmitted over the display interface 103, and the input interface 122 obtains the indication information INF of the pixel data grouping setting DG_SET by parsing a command set in a payload portion of the input bitstream received from the display interface 103. Please refer to FIG. 4, which is a diagram illustrating a data structure of the output bitstream generated from the application processor 102 to the driver IC 104 according to an embodiment of the present invention. The information handshaking between the application processor 102 and the driver IC 104 may be realized by defining a set of commands in the transmitted payload. For example, these commands can be specified in either a user command set or a manufactured command set based on MIPI display command set (DCS) specification, where each command in a command set is an 8-bit code, and the command set can be used to communicate between the application processor 102 and the driver IC 104 about the pixel data grouping setting DG_SET. Please refer to FIG. 5, which is a diagram illustrating an example of information handshaking between the application processor 102 and the driver IC 104. In this example, the application processor 102 may support at least six pixel data grouping patterns, as shown in FIG. 2 and FIG. 3. In addition, the driver IC 104 may support at least three settings for enable signals EN₁-EN₄, as shown in FIG. 2 and FIG. 3. The application processor 102 checks a de-compression capability and requirement of the driver IC 104 by sending a request to the driver IC 104 through the display interface 103, and the driver IC 104 informs the application processor 102 of its de-compression capability and requirement by sending a response to the application processor 102 through the display interface 103. Based on the information given by the driver IC 104, the application processor 102 determines the pixel data grouping setting DG_SET by using the pixel data grouping pattern #0. Hence, the indication information INF is set by an 8-bit code 8′h00 to indicate the use of the pixel data grouping pattern #0. The indication information INF is carried by the command set transmitted from the application processor 102 to the driver IC 104 via the display interface 103. The driver IC 104 receives the indication information INF through the display interface 103, and refers to the 8-bit code 8′h00 to know that the pixel data grouping pattern #0 is selected by the application processor 102. Hence, based on the indication information INF of the pixel data grouping setting DG_SET, the driver IC 104 sets the enable signals EN₁-EN₄ by {1, 1, 1, 1} correspondingly.

FIG. 6 is a flowchart illustrating a control and data flow of the data processing system 100 shown in FIG. 1 according to an embodiment of the present invention. Provided that the result is substantially the same, the steps are not required to be executed in the exact order shown in FIG. 6. The exemplary control and data flow may be briefly summarized by following steps.

Step 602: Check a de-compression capability and requirement of a driver IC.

Step 603: Inform an application processor of the de-compression capability and requirement.

Step 604: Determine a pixel data grouping setting according to a checking result. For example, one of the pixel data grouping patterns shown in FIG. 2 and FIG. 3 may be selected.

Step 606: Generate a plurality of compressed pixel data groups by using compressors to compress a plurality of pixel data groups obtained from pixel data of a plurality of pixels of a picture based on the pixel data grouping setting.

Step 608: Pack/packetize the compressed pixel data groups into an output bitstream.

Step 610: Record indication information of the pixel data grouping setting in the output bitstream. For example, the indication information is recorded in a command set of a payload portion of the output bitstream.

Step 612: Transmit the output bitstream via a display interface.

Step 614: Receive an input bitstream from the display interface.

Step 616: Parse indication information of the pixel data grouping setting from the input bitstream. For example, the indication information is obtained from a command set of a payload portion of the input bitstream.

Step 618: Un-pack/un-packetize the input bitstream into a plurality of compressed data groups.

Step 620: Select multiple de-compressors according to the indication information.

Step 622: Generate pixel data of a plurality of pixels of a reconstructed picture by using the selected de-compressors to de-compress the compressed pixel data groups, independently, and then merging a plurality of de-compressed pixel data groups based on the pixel data grouping setting as indicated by the indication information.

It should be noted that steps 602 and 604-612 are performed by the application processor (AP) 102, and steps 603 and 614-622 are performed by the driver IC 104. As a person skilled in the art can readily understand details of each step shown in FIG. 6 after reading above paragraphs, further description is omitted here for brevity.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. A data processing apparatus, comprising:

a compression circuit, configured to generate a plurality of compressed pixel data groups by compressing pixel data of a plurality of pixels of a picture based on a pixel data grouping setting of the picture; and

an output interface, configured to record indication information in an output bitstream and outputting the output bitstream via a display interface, wherein the output bitstream is derived from the compressed pixel data groups, and the indication information is set in response to the pixel data grouping setting employed by the compression circuit.

2. The data processing apparatus of claim 1, wherein the display interface is a display serial interface (DSI) standardized by a Mobile Industry Processor Interface (MIPI) or an embedded display port (eDP) standardized by a Video Electronics Standards Association (VESA).

3. The data processing apparatus of claim 1, wherein the output interface is configured to record the indication information by setting a command set in a payload portion of the output bitstream.

4. The data processing apparatus of claim 1, wherein the data processing apparatus is coupled to another data processing apparatus via the display interface, and the data processing apparatus further comprises:

a controller, configured to check a de-compression capability and requirement of the another data processing apparatus, and determine the pixel data grouping setting of the picture in response to a checking result.

5. A data processing apparatus, comprising:

a plurality of de-compressors, each configured to decompress a compressed pixel data group derived from an input bitstream when selected; and

an input interface, configured to receive the input bitstream via a display interface, and parse indication information included in the input bitstream, wherein multiple de-compressors are selected from the de-compressors according to the indication information.

6. The data processing apparatus of claim 5, wherein the display interface is a display serial interface (DSI) standardized by a Mobile Industry Processor Interface (MIPI) or an embedded display port (eDP) standardized by a Video Electronics Standards Association (VESA).

7. The data processing apparatus of claim 5, wherein the input interface is configured to obtain the indication information by parsing a command set in a payload portion of the input bitstream.

8. The data processing apparatus of claim 5, wherein the data processing apparatus is coupled to another data processing apparatus via the display interface, and the data processing apparatus further comprises:

a controller, configured to inform the another data processing apparatus of a de-compression capability and requirement of the data processing apparatus.

9. A data processing method, comprising:

generating a plurality of compressed pixel data groups by compressing pixel data of a plurality of pixels of a picture based on a pixel data grouping setting of the picture; and

recording indication information in an output bitstream, and outputting the output bitstream via a display interface, wherein the output bitstream is derived from the compressed pixel data groups, and the indication information is set in response to the pixel data grouping setting.

10. The data processing method of claim 9, wherein the display interface is a display serial interface (DSI) standardized by a Mobile Industry Processor Interface (MIPI) or an embedded display port (eDP) standardized by a Video Electronics Standards Association (VESA).

11. The data processing method of claim 9, wherein the step of recording the indication information in the output bitstream comprises:

recording the indication information by setting a command set in a payload portion of the output bitstream.

12. The data processing method of claim 9, wherein the output bitstream is transmitted from a first data processing apparatus to a second data processing apparatus via the display interface, and the data processing method further comprises:

checking a de-compression capability and requirement of the second data processing apparatus, and determining the pixel data grouping setting of the picture in response to a checking result.

13. A data processing method, comprising:

receiving an input bitstream via a display interface;

parsing indication information included in the input bitstream;

selecting multiple de-compressors from a plurality of de-compressors according to the indication information; and

utilizing the selected multiple de-compressors to de-compress a plurality of compressed pixel data groups derived from the input bitstream, respectively.

14. The data processing method of claim 13, wherein the display interface is a display serial interface (DSI) standardized by a Mobile Industry Processor Interface (MIPI) or an embedded display port (eDP) standardized by a Video Electronics Standards Association (VESA).

15. The data processing method of claim 13, wherein the step of parsing the indication information included in the input bitstream comprises:

obtaining the indication information by parsing a command set in a payload portion of the input bitstream.

16. The data processing method of claim 13, wherein the input bitstream is transmitted from a second data processing apparatus and received by a first data processing apparatus via the display interface, and the data processing method further comprises:

informing the second data processing apparatus of a de-compression capability and requirement of the first data processing apparatus.