DOUBLE-INTEGRATION TYPE A/D CONVERTER

Abstract

A double-integration type A/D converter for performing A/D conversion by integrating an input voltage and a reference voltage is disclosed. The A/D converter includes an integrator configured to integrate the input voltage and the reference voltage; a first switch configured to relay supply of the input voltage to an input terminal of the integrator; a second switch configured to relay supply of the reference voltage to the input terminal; and a control circuit configured to control switching on and off the first switch and the second switch. The control circuit generates a switching signal that switches on and off the first switch and the second switch individually and a switching signal that switches on and off the first switch and the second switch simultaneously. In addition, superimposition of the input voltage and the reference voltage is integrated when the first switch and the second switch are simultaneously switched on.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2014-038062, filed on Feb. 28, 2014, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to a double-integration type A/D (analog-to-digital) converter used for digital voltmeters, ohm meters, and so on, and more particularly, relates to a double-integration type A/D converter which is capable of achieving high noise tolerance and reduction of measuring time.

BACKGROUND

A double-integration type A/D converter performs A/D conversion by integrating an input voltage for a specified time, integrating a reference voltage whose polarity is opposite to that of the input voltage, and counting the time it takes for an output of an integration circuit to reach a predetermined level.

A conventional technology employs a double-integration type A/D converter which eliminates a zero point error by an offset voltage of an integrator using an operational amplifier. In this type of an A/D converter, integration is performed twice in the same integrator in order to eliminate the zero point error by the offset voltage of the integrator.

Another conventional technology uses an A/D converter in which current having a polarity opposite to that of an input voltage is discharged by a constant current circuit connected to an input side of an integrator during an input voltage integration period or a reference voltage integration period. Thus, this technology may achieve reduction of cost by reduction of A/D conversion time and reduction of the number of bits of a counter circuit.

A still yet another conventional technology adopts an integral type A/D converter which converts an output voltage of a detection circuit such as a bridge circuit for measurement of distortion (e.g., Wheatstone bridge circuit) or the like into digital data. Thus, this technology may achieve fast A/D conversion processing while appropriately eliminating unnecessary components including hum components caused by AC power.

SUMMARY

The present disclosure provides some embodiments of a double-integration type A/D converter, which is capable of improving noise tolerance and reducing measurement time.

According to one aspect of the present disclosure, there is provided a double-integration type A/D converter for performing A/D conversion by integrating an input voltage and a reference voltage, including an integrator configured to integrate the input voltage and the reference voltage; a first switch configured to relay supply of the input voltage to an input terminal of the integrator; a second switch configured to relay supply of the reference voltage to the input terminal; and a control circuit configured to control switching on and off the first switch and the second switch, wherein the control circuit generates a switching signal that switches on and off the first switch and the second switch individually and a switching signal that switches on and off the first switch and the second switch simultaneously, and wherein superimposition of the input voltage and the reference voltage is integrated when the first switch and the second switch are simultaneously switched on.

The control circuit in the double-integration type A/D converter according to the present disclosure may be configured to perform a first act for switching on the first switch and switching off the second switch, a second act for switching off the first switch and switching on the second switch, a third act for switching on the first switch and switching off the second switch, a fourth act for switching on the first switch and the second switch simultaneously, and a fifth act for switching off the first switch and switching on the second switch, and generates the switching signals in accordance with the first to fifth acts. Thus, at least one of the input voltage and the reference voltage may be integrated based on the switching signals.

In the double-integration type A/D converter according to the present disclosure, when a first integration period for the first act is denoted as T₁ and a second integration period for the second act is denoted as T₂, the second integration period may satisfy a condition of T₂≧αT₁, where 0.05≦α≦0.5. Further, when a third integration period for the third act is denoted as T₃, the third integration period may be expressed by an equation of T₃=M{(1+α)T₁−T₂}, where T₂≧αT₁ and 1≦M≦16. Furthermore, when a fourth integration period for the fourth act is denoted as T₄, the fourth integration period may be expressed by an equation of T₄=M(T₂−αT₁). In addition, when a fifth integration period for the fifth step is T₅, the fifth integration period may be expressed by an equation of T₅=αMT₁. Additionally, when a total integration period for the third act to the fifth act is denoted as T₂₀, the total integration period may be expressed by an equation of T₂₀=(1+α)MT₁. Moreover, the equation of the equation of T₂₀=(1+α)MT₁ may be established irrespective of a magnitude of the input voltage.

The control circuit in the double-integration type A/D converter according to the present disclosure may include a comparator configured to compares an output signal from the integrator with a reference voltage; a clock signal generating unit configured to generate a clock signal having a predetermined frequency and a predetermined pulse width; a counter configured to count an integration period required for integration operation based on the clock signal; and an A/D control circuit configured to output the switching signals at a predetermined timing in response to an output from the counter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a conceptual view of a double-integration type A/D converter according to the present disclosure.

FIGS. 2A to 2D illustrate timing diagrams of a double-integration type A/D converter provided for review before reaching an embodiment of the present disclosure.

FIGS. 3A to 3D illustrate timing diagrams of a double-integration type A/D converter according to an embodiment of the present disclosure.

FIGS. 4A to 4C illustrate timing diagrams of a double-integration type A/D converter depending on change of an input voltage, according to an embodiment of the present disclosure.

FIGS. 5A and 5B illustrate integration waveforms of a double-integration type A/D converter when a counter is stopped for a predetermined period of time, according to the present disclosure.

FIGS. 6A and 6B illustrate timing diagrams where integration waveforms are compared between a double-integration type A/D converter according to the present disclosure and a double-integration type A/D converter in a conventional scheme.

FIG. 7 illustrates a comparison in terms of several characteristics between a double-integration type A/D converter according to the present disclosure and a double-integration type A/D converter in a conventional scheme.

DETAILED DESCRIPTION

FIG. 1 conceptually illustrates a configuration of a double-integration type A/D converter 100 according to the present disclosure. The double-integration type A/D converter 100 includes an integrator 10, an input switching unit 20, a comparator 30, and a control circuit 40.

The integrator 10 includes an operational amplifier 11, a capacitor C, resistors R₁ and R₂, and a third switch SW₃. The third switch SW₃ is installed to initialize the integrator 10. Specifically, the third switch SW₃ is configured, when switched on, to remove charge that is accumulated in the capacitor C. The resistors R₁ and R₂ are connected to an inverted input terminal of the operational amplifier 11, and the capacitor C is connected between the inverted input terminal and an output terminal of the operational amplifier 11. The capacitor C and the third switch SW₃ are connected in parallel. A non-inverted input terminal of the operational amplifier 11 is connected to a reference voltage V_ref2. The resistor R₁ functions as an input integrator resistor for use in inputting an input voltage V_in to the inverted input terminal (−) of the operational amplifier 11, and the resistor R₂ functions as an input integrator resistor for use in inputting a reference voltage V_ref1 to the inverted input terminal (−) of the operational amplifier 11. Resistance values of the resistors R₁ and R₂ may be the same or different.

The integrator 10 is configured to integrate a difference between the reference voltage V_ref2 inputted to the non-inverted input terminal and the input voltage V_in (or the reference voltage V_ref1) inputted to the inverted input terminal by using a time constant which is determined based on the resistors R₁ (or R₂) and a capacitance of the capacitor C. A voltage according to a result of the above integration is then outputted by the integrator 10.

The input switching unit 20 may be configured to provide an input to the integrator 10 by switching between the input voltage V_in and the reference voltage V_ref1, whose polarity is opposite to that of the input voltage V_in. The input switching unit 20 includes a first switch SW₁ that relays the input voltage V_in to the operational amplifier 11, and a second switch SW₂ that relays the reference voltage V_ref1 to the operational amplifier 11.

An example of the input voltage V_in may include a voltage signal or the like obtained through amplifying an output voltage of a resistive sensor or a capacitive sensor (not shown) by using a pre-amplifier or the like. In addition, an input component may be a current component instead of a voltage component. Such a voltage signal or a current signal is an analog signal which is to be A/D converted, and is inputted to the inverted input terminal of the operational amplifier 11. A detailed configuration and a detection object of the above sensor may be modified in any other suitable manner.

The comparator 30 has an inverted input terminal, to which outputs of the integrator 10, specifically, output integration voltages V_o and V_o1, are inputted, and a non-inverted input terminal to which the reference voltage V_ref2 is inputted. When the output integration voltage V_o becomes equal to the reference voltage V_ref2, a high or low level signal is outputted from an output side of the comparator 30.

The control circuit 40 is implemented with a logic circuit, and includes a clock signal generation circuit 41, a counter 42, an A/D control circuit 43, and a switch control circuit 44. The A/D control circuit 43 includes a start timing measurement circuit 43a.

In the control circuit 40, the clock signal generation circuit 41 generates a clock signal CLK, the counter 42 counts the clock signal CLK, and the A/D control circuit 43 calculates an integration period of the reference voltage V_ref1 based on a counted value of the counter 42 and outputs the calculated integration period to the switch control circuit 44.

The counter 42 outputs an output digital voltage V_out which is obtained by counting and digitalizing a time of the integration period based on the clock signal CLK. The start timing measurement circuit 43a sets the time of the integration period and an integration starting timing. Switching the first switch SW₁ and the second SW₂ on and off is determined depending on the set timing and integration time.

FIGS. 2A to 2D illustrate timing diagrams of a double-integration type A/D converter provided for review before describing an embodiment of the present disclosure. An integration waveform shown in FIG. 2A is a conventionally used waveform. Specifically, FIGS. 2A to 2D of the present disclosure depict an integration method where double-integration is performed twice. As illustrated, a first double-integration includes a first integration period T₃₁ and a second integration period T₃₂. A first total integration period T₄₀ is equal to a sum of the first integration period T₃₁ and the second integration period T₃₂. A second double-integration includes a third integration period T₃₃, a fourth integration period T34, and a fifth integration period T₃₅. A second total integration period T₅₀ is equal to a sum of the third integration period T₃₃, the fourth integration period T34, the fifth integration period T35, and a reset period Tr. The present disclosure is significantly different from the conventional technology in integration of the third to fifth integration periods T₃₃ to T₃₅, and is characterized, for example, by the fourth integration period T₃₄, details of which will be described later.

FIG. 2A illustrates a change of an integration waveform of an output integration voltage V_o1 of the integrator 10, FIG. 2B illustrates on-and-off timings of the first switch SW₁, FIG. 2C illustrates on-and-off timings of the second switch SW₂, and FIG. 2D illustrates on-and-off timings of the third switch SW₃. The timing diagrams of FIGS. 2A to 2D is described below with reference to FIG. 1.

FIG. 2A depicts five integration periods and one reset period, specifically, the first integration period T₃₁ for integrating the input voltage V_in, the second integration period T₃₂ for integrating the reference voltage V_ref1 whose component is opposite to that of the input voltage V_in, the reset period T_r for removing residual charge of the integrator 10, the third integration period T₃₃ for integrating the input voltage V_in, the fourth integration period T₃₄ for integrating superimposition of the input voltage V_in and the reference voltage V_ref1, and the fifth integration period T₃₅ for integrating the reference voltage V_ref1.

FIGS. 2B, 2C, and 2D depict switching signals for switching on and off the first to third switches SW₁ to SW₃, respectively. The switching signals are generated by the control circuit 40. As used herein, the terms “first step” to “fifth step” indicate durations of switching on and off the first to third switches SW₁ to SW₃. The steps correspond to the above described first to fifth integration periods, respectively. For example, the first step corresponds to a switching state of the first to third switches SW₁ to SW₃ in the first integration period T₃₁. Similarly, the second step, the third step, the fourth step, and the fifth step correspond to switching states of the first to third switches SW₁ to SW₃ in the second integration period T₃₂, the third integration period T₃₃, the fourth integration period T₃₄, and the fifth integration period T₃₅, respectively.

As illustrated in FIG. 2A, in the first step (i.e., the first integration period T₃₁), the first switch SW₁, the second switch SW₂, and the third switch SW₃ are set to be on, off, and off, respectively. Thus, the input voltage V_in is applied to the inverted input terminal of the operational amplifier 11 via the resistor R₁, and integrated for a predetermined period of time.

In the second step (i.e., the second integration period T₃₂), the first switch SW₁, the second switch SW₂, and the third switch SW₃ are set to be off, on, and off, respectively. In this operation, the reference voltage V_ref1 is applied to the inverted input terminal of the operational amplifier 11 via the resistor R₂, and integrated for a predetermined period of time.

The reset period T_r is set to be a short period as a transition from the second step to the third step. In the reset period T_r, the first switch SW₁, the second switch SW₂, and the third switch SW₃ are set to be off, off, and on, respectively. The reset period T_r is provided to initialize (or reset) the integrator 10 by discharging charge that is accumulated in the capacitor C during transition to the following third step (i.e., the third integration period T₃₃).

In the third step (i.e., the third integration period T₃₃), the first switch SW₁, the second switch SW₂, and the third switch SW₃ are set to be on, off, and off, respectively. In the third step, the input voltage V_in is inputted to the integrator 10, and integrated for a predetermined period of time.

In the fourth step (i.e., the fourth integration period T₃₄), the first switch SW₁, the second switch SW₂, and the third switch SW₃ are set to be on, on, and off, respectively. In the fourth step, both of the input voltage V_in and the reference voltage V_ref1 are inputted to the integrator 10. In this operation, since a polarity of the reference voltage V_ref1 is opposite to that of the input voltage V_in, a voltage difference between the voltages is integrated. Specifically, in the fourth integration period T₃₄, superimposition of the input voltage V_in and the reference voltage V_ref1 is inputted to the integrator 10. Since the polarity of the input voltage V_in is opposite to that of the reference voltage V_ref1, noise in the input voltage V_in can be cancelled with noise in the reference voltage V_ref1 in the integration period of the above voltages. Therefore, tolerance to noise may be improved in the fourth integration period T₃₄.

In the fifth step (i.e., the fifth integration period T₃₅), the first switch SW₁, the second switch SW₂, and the third switch SW₃ are set to be off, on, and off, respectively. Thus, in the fifth step, only the reference voltage V_ref1 is integrated. In this operation, integrating only the reference voltage V_ref1 is to integrate the remainder of the reference voltage V_ref1.

FIGS. 2A to 2D show an integration scheme of performing the double-integration twice as described above. In this integration scheme, since the superimposition of the input voltage V_in and the reference voltage V_ref1 whose polarity is opposite to that of the input voltage V_in is integrated, tolerance to noise may be improved. However, since the above integration performs the double integration twice and, particularly, the first integration period T₃₁ and the second integration period T₃₂ are relatively long, a long integration time in total is still problematic.

FIGS. 3A to 3D illustrates an embodiment of the present disclosure, which is implemented to overcome the problem described with reference to FIGS. 2A to 2D. FIGS. 3A to 3D shows integration periods of the input voltage V_in and the reference voltage V_ref1 according to the present disclosure, in which the integration periods proceed according to on-and-off states of the first to third switches SW₁ to SW₃. FIGS. 3A to 3D are significantly different from FIGS. 2A to 2D in that a first integration period T₁ and a second integration period T₂ are shortened to reduce measurement time. An integration time of the integration period T₃₄, shown in FIG. 2A, in which the input voltage V_in and the reference voltage V_ref1 are superimposed, can be halved theoretically. Accordingly, the inventor of the present disclosure has attempted to reduce the first integration period T₁ and the second integration period T₂ such that the measurement time amounts to about 70% of the conventional measurement time. The first integration period T₁ and the second integration period T₂ are set to be 1/M (where M is an integration period factor, e.g., 1≦M≦16) of the integration periods T₃₁ and T₃₂ shown in FIG. 2A, respectively. From the viewpoint of integration time and integration accuracy, the integration period factor M may be set to fall within a range of 1≦M≦16 based on results from a simulation. The third integration period T₃ and the fourth integration period T₄ may be set to be suitable time periods determined by a user, and may be about 500 μs which is the same as the integration periods T₃₁ and T₃₂ shown in FIG. 2A.

If the integration period factor M is set to be 1, FIG. 3A has the same configuration as FIG. 2A. If the integration period factor M is set to be 8, an integration period T₁₀ corresponding to a sum of the first integration period T₁ and the second integration period T₂ is set to be about ⅛ of the integration period T₄₀ shown in FIG. 2A. The integration period factor M is set based on a total integration time. If the integration period factor M is set to be large, the total integration time can be reduced but the input voltage V_in and the reference voltage V_ref1 may not be integrated with high precision. On the other hand, if the integration period factor M is set to be small, the input voltage V_in and the reference voltage V_ref1 may be integrated with high precision, but the total integration time may not be reduced sufficiently.

FIG. 3A illustrates a change of an integration waveform of the output integration voltage V_o, FIG. 3B illustrates on-and-off timings of the first switch SW₁, FIG. 3C illustrates on-and-off timings of the second switch SW₂, and FIG. 3D illustrates on-and-off timings of the third switch SW₃.

FIG. 3A depicts the changes of the waveform of the output integration voltage V_o, which shortens the first integration period T₃₁ and the second integration period T₃₂ as illustrated in FIG. 2A by respective switching operations.

Assuming that the sum of the third integration period T₃ and the fourth integration period T₄ is to, the first integration period T₁ in FIG. 3A may be set as T₁=t₀/M (where M is the integration period factor, 1≦M≦16). A range of the integration period factor M is obtained according to simulation based on integration time and integration accuracy in the same manner as described above. The second integration period T₂ may be an integration period taken until the reference voltage V_ref1 reaches a predetermined level after the input voltage V_in is integrated for the first integration period T₁. The reset period T_r may be a period for removing charge remaining in the integrator 10. The third integration period T₃ may be determined based on the first integration period T₁ and the second integration period T₂, and thus, may be expressed as T₃=M{(1+α)T₁−T₂}, where 0.050≦α≦0.5, 1≦M≦16, and T₂≦αT₁. The fourth integration period T₄ may be a period for supplying the input voltage V_in and the reference voltage V_ref1 simultaneously. The fourth integration period T₄ may be expressed as T₄=M(T₂−αT₁), where 0.05≦α≦0.5, 1≦M≦16, and T₂≦αT₁. The fifth integration period T₅ is for the reference voltage V_ref1 and may be expressed as T₅=αCMT₁, where 0.05≦α≦0.5, 1≦M≦16 and T₂≦αT₁. From the viewpoint of integration time and integration accuracy, an integration period margin factor α may be set to fall within a range of 0.05≦α≦0.5 as results from a simulation.

FIG. 3B illustrates a timing diagram of a switching signal that switches the first switch SW₁ on and off. The switching signal in FIG. 3B controls the first switch SW₁ to input the input voltage V_in to the inverted input terminal of the operational amplifier 11 via the resistor R₁ when the switch SW₁ is switched on. The first switch SW₁ is controlled by the control circuit 40 to be switched on in the first integration period T₁, the third integration period T₃, and the fourth integration period T₄, and switched off in the second integration period T₂ and the fifth integration period T₅.

FIG. 3C illustrates a timing diagram of a switching signal that switches the second switch SW₂ on and off. The switching signal in FIG. 3C controls the second switch SW₂ to input the reference voltage V_ref1 to the inverted input terminal of the operational amplifier 11 via the resistor R₂ when the switch SW₂ is switched on. The second switch SW₂ is controlled by the control circuit 40 to be switched on in the second integration period T₂, the fourth integration period T₄, and the fifth integration period T₅, and switched off in the first integration period T₁ and the third integration period T₃.

FIG. 3D illustrates a timing diagram of a switching signal that switches the third switch SW₃ on and off. The switching signal in FIG. 3D switches on the third switch SW₃ to initialize the integrator 10 by discharging residual charge in the integrator 10. The third switch SW₃ is controlled by the control circuit 40 so that it can be switched on in the reset period T_r and switched off in the first integration period T₁, the second integration period T₂, the third integration period T₃, the fourth integration period T₄, and the fifth integration period T₅. The control circuit 40 generates the switching signals as shown in FIGS. 3B, 3C, and 3D.

FIGS. 4A to 4C schematically illustrate integration waveforms depending on a magnitude of the input voltage V_in in accordance with the embodiment of the present disclosure as described above with reference to FIGS. 1 and 3A to 3D.

FIGS. 4A, 4B, and 4C show changes of the output integration voltage V_o of the integrator 10 according to three cases. Specifically, the cases include when compared with a dynamic range of the integrator 10, a case where the input voltage V_in is relatively small, a case where the input voltage V_in is approximately intermediate, and a case where the input voltage V_in is large. Such cases of the input voltage V_in (i.e., small, intermediate, and large) may be based on relative comparison, not based on specified numerical values. For instance, the relatively small input voltage V_in corresponds, for example, to ⅓ of the large input voltage V_in, and the intermediate input voltage V_in corresponds, for example, to ⅔ of the large input voltage V_in. Here, the large input voltage V_in may indicate an input voltage of a full limit of the dynamic range of the integrator 10 or an input voltage close to the full limit.

Hereinafter, relationships between time period lengths from the first integration period T₁ to the fifth integration period T₅ and magnitudes of the input voltage V_in are described with reference to FIGS. 4A to 4C. The unit of each integration period will be omitted for convenience of description, and will be described using numerical values.

FIG. 4A schematically illustrates an integration waveform for the relatively small input voltage V_in and lengths of respective integration periods. In the case of a relatively small input voltage V_in (i.e., “Small V_in”), if 1.0 is set as the length of the first integration period T₁, 0.3 is designated to the second integration period T₂, 6.4 is designated to the third integration period T₃, 1.6 is designated to the fourth integration period T₄, and 0.8 is designated to the fifth integration period T₅. As such, the third integration period T₃ is four times as long as the fourth integration period T₄.

FIG. 4B schematically illustrates an integration waveform for the approximately intermediate input voltage V_in and lengths of respective integration periods. In the case of the approximately intermediate input voltage V_in (i.e., “Intermediate V_in”), if 1.0 is set for the length of the first integration period T₁, 0.5 is designated to the second integration period T₂, 4.8 is designated to the third integration period T₃, 3.2 is designated to the fourth integration period T₄, and 0.8 is designated to the fifth integration period T₅. As such, the third integration period T₃ is 1.5 times as long as the fourth integration period T₄, which reduces a difference between the periods when compared with the case of the relatively small input voltage V_in as shown in FIG. 4A.

FIG. 4C schematically illustrates an integration waveform for a relatively large input voltage V_in and lengths of respective integration periods. The relatively large input voltage V_in (i.e., “Large V_in”) indicates the case where the input voltage is applied with the full limit of the dynamic range of the integrator 10. If 1.0 is set for the length of the first integration period T₁, 1.0 is designated to the second integration period T₂, 0.8 is designated to the third integration period T₃, 7.2 is designated to the fourth integration period T₄, and 0.8 is designated to the fifth integration period T₅. As such, the fourth integration period T₄ is nine times as long as the third integration period T₃, which indicates that the relationship between the integration periods in FIG. 4B is reversed from that in FIG. 4A. Accordingly, as the input voltage V_in is increased, the fourth integration period T₄ is extended to increase the time for integrating superimposition of the input voltage V_in and the reference voltage V_ref1, which improves tolerance to noise.

The first integration periods T₁ in FIGS. 4A to 4C have the same length since they are set to a predetermined integration time irrespective of the magnitude of the input voltage V_in.

The second integration period T₂ indicates a period where the input voltage V_in is switched to the reference voltage V_ref1, which then starts to be integrated. Specifically, the second integration period T₂ indicates a period in which charge accumulated in the integrator 10 during the first integration period T₁ is discharged. The length of the second integration period T₂ is proportional to the magnitude of the input voltage V_in. Since a larger input voltage V_in extends the second integration period T₂, the second integration period T₂ is shortest in the case of the small input voltage V_in, as depicted in FIG. 4A, and longest in the case of the large input voltage V_in, as depicted in FIG. 4C. The longest second integration period T₂ has the same length as the first integration period T₁ (i.e., T₂=T₁). Generally, T₂ is equal to or smaller than T₁ (i.e., T₂≦T₁).

The reset period T_r indicates a period where charge remaining in the integrator 10 is removed, and is set to be a constant time irrespective of the magnitude of the input voltage V_in. Thus, the reset period T_r is set to be, for example, about 1/10 of the first integration period T₁ and the second integration period T₂.

The third integration period T₃ may be expressed by T₃=M{(1+α)T₁−T₂}, where T₂≧αT₁, 0.05≦α≦0.5, and 1≦M≦16. In this equation, since the second integration period T₂ increases as the input voltage V_in increases, the third integration period T₃ increases in a direction opposite to the magnitude of the input voltage V_in. Thus, the third integration period T₃ is shortened as the input voltage V_in increases, whereas the third integration period T₃ is extended as the input voltage V_in decreases.

The fourth integration period T₄ may be expressed by T₄=M(T₂−αT₁), where T₂≧αT₁, 0.05≦α≦0.5, and 1≦M≦16. The second integration period T₂ increases as the input voltage V_in increases, as described above. Accordingly, as the input voltage V_in increases and thus the second integration period T₂ is extended, the fourth integration period T₄ is extended. By contrast, as the input voltage V_in decreases, the second integration period T₄ is shortened.

The fifth integration period T₅ may be expressed by T₅=εMT₁, and thus, set to be a predetermined time period without being affected by the magnitude of the input voltage V_in.

In FIGS. 4A to 4C, the first integration period T₁ and the second integration period T₂ may correspond to preliminary integration periods, and the third integration period T₃, the fourth integration period T₄, and the fifth integration period T₅ correspond to main integration periods. As such, in the present disclosure, the first integration period T₁ and the second integration period T₂ need be positioned to be preliminary to performing the main integration. In other words, the first integration period T₁ and the second integration period T₂ may be pre-measurement for setting integration time periods of the third integration period T₃, the fourth integration period T₄, and the fifth integration period T₅.

FIGS. 4A to 4C, illustrating one embodiment of the present disclosure, show that the integration period T₁₀ corresponding to the sum of the first integration period T₁ and the second integration period T₂, which is required for the so-called pre-measurement, is proportional to the input voltage V_in. However, the total integration period T₂₀ of the third integration period T₃ to the fourth integration period T₅, which is required for the main measurement, may be expressed by T₂₀=M(1+α)T₁, and given a predetermined length without depending on the magnitude of the input voltage V_in. As such, the integration period T₂₀ may be characterized by being constantly set as T₂₀=M(1+α)T₁, irrespective of the magnitude of the input voltage V_in. By setting each of the above integration periods, a total integration time required for measurement of the input voltage V_in can be substantially constant regardless of whether the input voltage V_in is large or small.

FIGS. 4A to 4C schematically illustrate the output integration voltages V_o and maximum values V_top1, V_top2, and V_top3 of the output integration voltages V_o. As illustrated, the maximum values V_top1, V_top2, and V_top3 vary depending on the magnitudes of the input voltage V_in and the lengths of the third integration periods T₃. The magnitudes of the maximum values V_top1, V_top2, and V_top3 affect the dynamic range of the integrator 10. Specifically, a smaller maximum value provides a higher margin of dynamic range which is advantageous for variation of the output integration voltage V_o. A smaller dynamic range can reduce a power supply voltage of the integrator 10, which can lead to power saving.

FIGS. 4A to 4C depict that the maximum values V_top1, V_top2, and V_top3 have a relationship of V_top2>V_top1>V_top3. As depicted, the maximum values are not proportional to the magnitude of the input voltage V_in. The maximum value V_top2 in the case of the approximately intermediate input voltage V_in is largest. Here, as a result of simulation on a relationship between the maximum value V_top2 and the dynamic range in the case of the approximately intermediate input voltage V_in, it may be found that the maximum value V_top2 is about 30% of the dynamic range of the integrator 10. The above aspect can increase a margin of dynamic range of the integrator 10 and further achieve an effect of lowering the power supply voltage to the integrator 10.

FIGS. 5A and 5B illustrate integration waveforms of main measurement by the double-integration type A/D converter 100 according to the present disclosure and an integration waveform obtained by a conventional double-integration type A/D converter. It is assumed that the counter 42 shown in FIG. 1 is stopped, for example, due to noise or the like for a predetermined period of time.

FIG. 5A illustrates a timing diagram for the conventional double-integration type A/D converter and shows an output integration voltage V_o1 outputted from the integrator 10. A period from time t₀ to time t₁ is indicative of an integration period of the input voltage V_in, and a period from time t₁ to time t₃ is indicative of an integration period of the reference voltage V_ref1. A magnitude of an integration voltage obtained by integrating from time t₁ to time t₃ is outputted as an output digital voltage V_out from the counter 42.

In this case, if the counter 42 is stopped during a period from time t₁ to time t₂ due to noise or the like, integration operation is continued until time t₂ according to a difference with time t₁ that has been determined previously. Upon reaching time t₂, the integration operation is transitioned to integrate the reference voltage V_ref1. The reference voltage V_ref1 is integrated until time t₄ rather than originally expected time t₃, which is longer by an amount of time in which the counter 42 has been stopped due to noise or the like. As such, when the counter 42 is stopped, a time period for integrating the input voltage V_in is extended to be longer than a predetermined time period, and a time period for integrating the reference voltage V_ref1 is also extended by an extended amount of the time period for integrating the input voltage V_in, which results in an incorrect integration operation.

FIG. 5B illustrates a timing diagram of the double-integration type A/D converter 100 according to the present disclosure and shows an output integration voltage V_o outputted from the integrator 10. A period from time t₅ to time t₆ is indicative of an integration period of the input voltage V_in, a period from time t₆ to time t₇ is indicative of an integration period of superimposition of the input voltage V_in and the reference voltage V_ref1, and a period from time t₇ to time t₈ is indicative of an integration period of the reference voltage V_ref1. A magnitude of an integration voltage obtained by integrating from time t₆ to time t₈ is outputted as an output digital voltage V_out from the counter 42.

In this operation, even if the counter 42 is stopped due to noise or the like during the period from time t₇ to time t₈, the integration period for the reference voltage V_ref1 corresponds to a period from time t₆ to time t₉. A period where the output digital voltage V_out is outputted corresponds to the period from time t₆ to time t₉ except for the period from time t₇ to time t₈ where the counter 42 is stopped. In addition, the period from time t₈ to time t₉ and the period from time t₇ to time t₈ are substantially constant irrespective of the magnitude of the input voltage V_in. Therefore, a time period where the output digital voltage V_out is outputted, specifically, the period from time t₆ to time t₉ except for the period from time t₇ to time t₈ where the counter is stopped due to noise, becomes equal to a time period from time t₆ to time t₈. Accordingly, the output digital voltage V_out would not be varied due to noise.

FIGS. 6A and 6B illustrate timing diagrams where integration waveforms are compared between a double-integration type A/D converter according to the present disclosure and a double-integration type A/D converter in a conventional scheme.

FIG. 6A illustrates a timing diagram for the conventional double-integration type A/D converter, and shows an output integration voltage V_o1 outputted from the integrator 10. As used herein, the term “conventional” refers to an integration scheme performed with the first and second integration periods T₃₁ and T₃₂ in the manner illustrated in FIGS. 2A to 2D. In FIG. 6A, the first integration period T₃₁ corresponds to the integration period of the input voltage V_in, and the second integration period T₃₂ corresponds to the integration period of the reference voltage V_ref1. In the conventional scheme, the above integration periods may be relatively long depending on the magnitude of the input voltage V_in.

FIG. 6B illustrates a timing chart for the double-integration type A/D converter according to the present disclosure, and shows an output integration voltage V_o outputted from the integrator 10. By setting the first integration period T₁ and the second integration period T₂ to 1/M of the conventional integration periods T₃₁ and T₃₂ (where M is the integration period factor, for example, M=8), respectively, the integration periods can be reduced to ⅛ of the integration periods in the conventional scheme. In addition, as described above, a sum of the third integration period T₃, the fourth integration period T₄, and the fifth integration period T₅ is set based on the first integration period T₁ and the second integration period T₂, and is maintained to be constant irrespective of the magnitude of the input voltage V_in. Accordingly, the integration period T₃₀ from the first integration period T₁ to the fifth integration period T₅ amounts to about 70% of the integration period T₄₀ in the conventional scheme, which can lead to shortening an integration time.

FIG. 7 illustrates a comparison in terms of noise impact, a measurement time (or integration time), and dynamic range between the present disclosure and the conventional scheme. FIG. 7 is related to FIGS. 6A and 6B. FIG. 7 is described below in conjunction with FIGS. 6A and 6B.

The noise impact is first described below. In the present disclosure, if the integration period factor α is assumed to be 0.1, the noise impact is reduced to about 10% of that of the conventional integration scheme which includes the first integration period T₃₁ for integrating the input voltage V_in and the second integration period T₃₂ for integrating the reference voltage V_ref1, as shown in FIG. 6A. This is because the noise impact can be significantly suppressed by reducing the first integration period T₁ and the second integration period T₂ to about ⅛ of the integration periods T₃₁ and T₃₂ in the conventional scheme and setting an integration time for superimposition of the input voltage V_in and the reference voltage V_ref1 to about 50% or more of a total time period. In addition, if the integration period margin factor α is set to be 0.05, it is found that the noise impact may be further reduced to about 5% of that of the conventional integration scheme. Additionally, if the integration period margin factor α is set to be 0.5, it is found the noise impact may be further increased, when compared with the case where α=0.1, to about 63% of that of the conventional integration scheme. Furthermore, if the input voltage V_in is decreased to about ¼ of the large input voltage V_in, it is found tolerance to noise may be reduced when compared with the case of the large input voltage V_in.

The comparison of the measurement time (or integration period) is described below. If the integration period margin factor α is 0.1, it is found that the measurement time may be reduced to about 68% of that of the conventional integration scheme. As such, it is found the integration time of the present disclosure may be reduced by 30% or more when compared with the conventional measuring time. The present disclosure that performs a double-integration twice provides a shorter integration time when compared with the conventional scheme that performs a double-integration once. Further, if the integration period margin factor α is set to be 0.05, it is found that the measurement time is reduced to about 65% of that of the conventional integration scheme. Additionally, if the integration period margin factor α is set to be 0.5, it is found that the measurement time is reduced to about 88% of that of the conventional integration scheme. Thus, it can be confirmed that reduction of the measurement time depends on the integration period margin factor α.

The comparison of the dynamic range is described below. If the integration period margin factor α is 0.1, it is found that the dynamic range is reduced to about 30% of that of the conventional integration scheme. This can suppress output variation of the output integration voltage V_o. In addition, such a less dynamic range allows the integrator 10 to be driven with a lower power supply voltage, which can result in power savings.

Further, since the lower power supply voltage of the integrator 10 allows reduction of size of the capacitor C and the resistors R1 and R2 that constitutes the integrator 10, it is possible to further improve compactness and noise tolerance of ICs.

The double-integration type A/D converter according to the present disclosure has a very high industrial applicability since it can improve noise tolerance and reduce measuring time.

The double-integration type A/D converter according to the present disclosure includes a control circuit configured to generate timings at which an input voltage and a reference voltage are separately inputted to an integrator and a timing at which the input voltage and the reference voltage are simultaneously inputted to the integrator. With this configuration, since an addition (i.e., superimposition) of the input voltage and the reference voltage can be integrated based on separate integration of the input voltage and the reference voltage, it is possible to achieve excellent noise tolerance and reduced integration time.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel methods and apparatuses described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures.

Claims

1. A double-integration type A/D converter for performing A/D conversion by integrating an input voltage and a reference voltage, comprising:

an integrator configured to integrate the input voltage and the reference voltage;

a first switch configured to relay supply of the input voltage to an input terminal of the integrator;

a second switch configured to relay supply of the reference voltage to the input terminal; and

a control circuit configured to control switching on and off the first switch and the second switch,

wherein the control circuit generates a switching signal that switches on and off the first switch and the second switch individually and a switching signal that switches on and off the first switch and the second switch simultaneously, and

wherein superimposition of the input voltage and the reference voltage is integrated when the first switch and the second switch are simultaneously switched on.

2. The double-integration type A/D converter of claim 1, wherein the control circuit is configured to perform a first act for switching on the first switch and switching off the second switch, a second act for switching off the first switch and switching on the second switch, a third act for switching on the first switch and switching off the second switch, a fourth act for switching on the first switch and the second switch simultaneously, and a fifth act for switching off the first switch and switching on the second switch, and generates the switching signals in accordance with the first to fifth acts, and

wherein the integrator is configured to integrate at least one of the input voltage and the reference voltage based on the switching signals.

3. The double-integration type A/D converter of claim 2, wherein when a first integration period for the first act is denoted as T1 and a second integration period for the second act is denoted as T2, the second integration period satisfies a condition of T2≧αT1, where 0.05≦α≦0.5.

4. The double-integration type A/D converter of claim 3, wherein when a third integration period for the third act is denoted as T3, the third integration period is expressed by an equation of T3=M{(1+α)T1−T2}, where T2≧αT1 and 1≦M≦16.

5. The double-integration type A/D converter of claim 4, wherein when a fourth integration period for the fourth act is denoted as T4, the fourth integration period is expressed by an equation of T4=M(T2−αT1).

6. The double-integration type A/D converter of claim 5, wherein when a fifth integration period for the fifth act is T5, the fifth integration period is expressed by an equation of T5=αMT1.

7. The double-integration type A/D converter of claim 6, wherein when a total integration period for the third act to the fifth act is denoted as T20, the total integration period is expressed by an equation of T20=(1+α)MT1.

8. The double-integration type A/D converter of claim 7, wherein the equation of T20=(1+α)MT1 is established irrespective of a magnitude of the input voltage.

9. The double-integration type A/D converter of claim 1, wherein the control circuit includes:

a comparator configured to compare an output signal from the integrator with a reference voltage potential;

a clock signal generating unit configured to generate a clock signal having a predetermined frequency and a predetermined pulse width;

a counter configured to count an integration period required for integration operation based on the clock signal; and

an A/D control circuit configured to output the switching signals at a predetermined timing in response to an output from the counter.