Load Transient Asynchronous Boost for Pulse Width Modulation Modulator
A pulse width modulation controller (PWM) is disclosed which has a MOSFET (15) responsive to the error voltage (Verror) signal from the PWM amplifier (17) to detect a transient condition without delay ΔTd. The MOSFET drain generates and applies a detection signal (S) to a delaying circuit (D). The delaying circuit (D) is responsive to the transient detection signal (S) to asynchronously output two latch signals (S1) and (S2) which on application to respective latch circuits (L1, L2) cause a change in conduction state of PMOS (8) and NMOS (9). This arrangement reduces voltage undershoot.
The invention relates to the field of power management units (PMU) and especially to power management units requiring pulse width modulation controllers. Such PMU's are in common usage in many devices, but especially in mobile devices such as mobile phones, smartphones, tablet computers and other similar communication and data processing devices.
BACKGROUND OF THE INVENTIONMobiles devices imply high constraints in the embedded power management unit. Typically, these power management units are comprised of buck convertors which are synchronized by a main clock phased by a pulse width modulated (PWM) control.
The main clock 1 (CLK) is phase shifted by the blocks 2, 3, 4 (PH1, PH2, PH3). Each of these blocks shifts the clock phase by a different value so as to produce 3 different clocks, CLK_1, CLK_2, CLK_3. Each of these clocks drives a respective one of the buck convertors 5, 6, 7, respectively BUCK1, BUCK2, BUCK3. In the basic example of the
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- The clock CLK_1 may not be shifted with regard to the main clock CLK.
- The clock CLK_2 may be shifted by +60°, with regard to the main clock CLK.
- The clock CLK_3 may be shifted by +120° with regard to the main clock CLK.
In general where N is the number of buck convertors, the clock CLK_i driving the buck convertor BUCK_i may be shifted by 360×i/N, where i∈[0, N−1]. This architecture prevents all the buck convertors starting their conduction cycle on the same clock rising edge, which would lead to a large undershoot on the battery. For this reason, the buck convertors are often referred to as PWM synchronized voltage mode control.
At the beginning of the clock signal, the state machine SM operates a latch L1 to power PMOS 8 on to conduct the clock signal will synchronously keep the NMOS 9 non-conducting (off). Each time the error signal Verror crosses the Vramp signal, the state machine turns the PMOS 8 off and switches a latch L2 to power on an NMOS 9 to the conducting state. The end of the NMOS conduction cycle is set by the signal Vx at the end of the clock cycle. This is further illustrated by the
An important drawback of this architecture is that in case of high output load transients, the output voltage undershoots. The load transient performance is dependent not only on the output filters L and C but also on the phase difference between (ΔTd) the output load transient step and the clock rising edge. Due to the dependence on the phase difference between the output load transient step and the clock rising edge, the load transient performance can be impacted by 30%.
High output load transients are more and more a requirement from the market.
There is therefore a need for a technical solution which will reduce the impact on the performance of high output load transients.
STATEMENT OF INVENTIONAccordingly the present invention provides a pulse width modulation (PWM) controller having synchronized PWM voltage mode control architecture comprising:
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- means for detecting a transient load and
- means for asynchronously changing the state of the state machine.
The PWM preferably reduces the phase difference between the output load transient step and the clock rising edge in order to minimize or prevent output voltage undershoot. Preferably this is achieved by applying the output of an amplifier of the PWM to a transient load detection means provided by a transient load detection circuit. The transient load detection circuit may comprise a MOSFET or transistor with similar performance, having a gate terminal to which an error voltage signal output by the amplifier is applied to generate a detection signal at the drain terminal.
The detection signal may be applied to a delaying circuit. The delaying circuit is preferably responsive to a rapidly changing detection signal to generate signals to control the conduction states of each of a PMOS transistor and an NMOS transistor. The signals may be latch signals to actuate latches controlling each respective PMOS and NMOS transistor. The delaying circuit generates each latch signal at relatively different times, i.e. the delaying circuit provides the means for asynchronously changing the state of the state machine.
To minimise ΔTd the source of the MOSFET is connected to a load/source resistor in parallel with a capacitor. This minimizes current at the source and drain during steady state operation when the capacitor is does not conduct. However, under rapid transition the capacitor acts as if to short across the resistance to induce a detection signal with much reduced phase lag at the MOSFET drain terminal. The delaying circuit responds nearly instantaneously to the detection signal to induce the asynchronous conduction state switching of the PMOS and NMOS transistors.
A PMU and a method of operation of a PMU embodying the invention will now be described, by way of example only, with reference to the accompanying illustrative figures, in which:
The circuit DC enables detection of the load transient. It is based on fast change of the Verror signal. Indeed, when a fast and large load stress is applied at the output of the buck convertor, the Verror signal (measured at the output of the amplifier Amp) increases fast because of the large amplifier gain and bandwidth as a result of the output load step.
Turning back to
When the error voltage signal (Verror) increase rapidly, the source capacitor 19 conducts and causes a short circuit across the source/load resistor 18 during this fast transient event. During these few nanoseconds, a large current flows between the drain and the source. The current is large by comparison with the steady state condition. Consequently, the voltage at the drain makes a fast negative spike from Vcc and the inverted output voltage follows a very fast positive spike from zero to Vcc.
The power consumption is set mainly by the value of the load resistor 18 and can thus be kept low by keeping the source current through the load resistor below 1 pA. One of the advantages of the invention is to keep current consumption at a very low level.
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- 1—Reset the latch L2 in order to stop the conduction cycle on the NMOS.
- 2—Start a new cycle on the PMOS transistor by changing the state of the latch L1.
The detection signal S is applied to a delaying circuit D. The delaying circuit D generates two latch signals, S1, S2. As shown in
Various simulations have showed that the load transient performance is improved by 10% to 20%.
Claims
1. A pulse width modulation (PWM) controller having synchronized PWM voltage mode control architecture comprising:
- wherein there is provided means for detecting a transient load and means for asynchronously changing the state of the state machine.
2. A PWM controller according to claim 1 having an amplifier arranged to output an error signal to a transient load detection circuit which provides said means for detecting a transient load.
3. A PWM controller wherein the transient load detection circuit comprises a transistor having a gate communicating with the amplifier output to be responsive to the error signal, and
- a source resistance in parallel with a source capacitor connected to the source terminal whereby, in steady state operation all current flows through the source resistance and when the detection signal is rapidly changing the rapid voltage change at the source induces a current flow across the source capacitor to short circuit the resistor.
4. A PWM controller according to claim 3 wherein the value of the resistance is of the order of 1-999 MΩ.
5. A PWM controller according to claim 4 wherein transistor outputs a detections signal at the source terminal.
6. A PWM controller according to claim 5 wherein a delaying circuit is connected to the source terminal to be responsive to the detection signal.
7. A PWM controller according to claim 6 wherein the delaying circuit is responsive to the detection signal to generate first and second latch signals, which are applied, respectively to a PMOS latch and an NMOS latch said PMOS latch and said NMOS latch being connected to, respectively, a PMOS transistor and an NMOS transistor whereby, in response to said first and second latch signals the respective conduction state of the PMOS transistor and the NMOS transistor are switched.
8. A PWM controller according to claim 7 wherein the detection circuit is arranged to generate rectangular latch signals synchronized on the step of the detection signal.
9. A PWM controller according to claim 8 wherein the detection circuit is arranged to delay generation of one latch signal with regard to the other latch signal to provide the means for asynchronously changing the state of the state machine.
10. A power management unit incorporating a pulse width modulation controller according to claim 1.
11. A mobile device incorporating a PMU according to claim 10.
Type: Application
Filed: Nov 15, 2013
Publication Date: Sep 10, 2015
Patent Grant number: 9490776
Inventor: Philippe Pignolo (Crolles)
Application Number: 14/438,727