SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate, a plurality of element regions that are partitioned in a line-and-space shape and extend in a first direction in the substrate, a plurality of selection gates that are formed on the substrate to extend in a second direction intersecting the first direction. In addition, the semiconductor device includes a contact region that includes a plurality of contact plugs which are provided between two selection gates adjacent to each other and are connected to the respective element regions in the substrate. Further, the contact plug includes an upper portion and a lower portion. The upper portion has a first width and is formed of a first conductive film and a second conductive film. The lower portion has a second width smaller than the first width and is formed of the first conductive film.
This application is based upon and claims the benefit of priority from U.S. Provisional Patent Application No. 62/011,637, filed Jun. 13, 2014, the entire contents of which are incorporated herein by reference.
FIELDEmbodiments described herein relate to a semiconductor device.
BACKGROUNDIn semiconductor devices, a contact having a small dimension is formed on a conductive region, and adjacent contacts are separated from one another at a small pitch (small spacing). However, the deterioration of a breakdown voltage between conductive regions adjacent to each other and a contact opening can easily occur.
A semiconductor device according to this embodiment includes: a substrate; a plurality of element regions that are positioned in a line-and-space shape and extend in a first direction in the substrate; and a plurality of selection gates that are formed on the substrate to extend in a second direction intersecting the first direction. In addition, the semiconductor device includes a contact region that includes a plurality of contact plugs which are provided between two selection gates adjacent to each other and connected to the respective element regions in the substrate. Further, the contact plug includes an upper portion and a lower portion. The upper portion has a first width and comprises a stacked film including a first conductive film and a second conductive film. The lower portion has a second width smaller than the first width and comprises the first conductive film.
First EmbodimentHereinafter, a first embodiment in which a NAND-type flash memory device is applied as an example of a semiconductor device will be described with reference to
Meanwhile, in the following description, an XYZ orthogonal coordinate system is used for convenience of description. In the coordinate system, two directions which are parallel to the surface of a semiconductor substrate and perpendicular to each other are assumed to be an X direction and a Y direction, a direction in which word lines WL extend is assumed to be the X direction, and a direction which is perpendicular to the X direction and in which bit lines BL extend is assumed to be the Y direction. A direction perpendicular to both the X direction and the Y direction is assumed to be a Z direction.
First, the configuration of a NAND-type flash memory device 1 according to this embodiment will be described.
As shown in
In
A bit line contact CB (CBa and CBb in
The word line WL is formed extend along a direction (X-direction in the drawing) perpendicular to and crossing the element region Sa. The plurality of word lines WL each extend in the X-direction and are and spaced apart at predetermined intervals in the Y-direction in the drawing. A memory cell gate electrode MG of a memory cell transistor Trm is formed on the element region Sa crossing the word line WL.
As shown in
The plurality of selection gate transistors Trs1 are spaced apart in the X-direction, and selection gate electrodes SGD (see
In addition, as shown in
As shown in
Each of the plurality of bit line contacts CBa and CBb is formed on one of the plurality of element regions Sa extending across a bit line contact region C. Each of the bit line contacts CB is formed on the element region Sa between adjacent selection gate transistors Trs1-Trs1 on opposite sides of a bit line contact region C.
As shown in
On the other hand, adjacent pairs of bit line contacts CBa and CBb are oriented along a line L in a direction parallel to the semiconductor substrate 10 and which is not parallel to the X-direction and the Y-direction. Two of the bit line contacts CBa and CBb successively formed adjacent to each other are disposed on the element regions Sa1 and Sa2 successively formed adjacent to each other so as to be mounted on the straight line L. The two adjacent bit line contacts CBa and CBb are set as one unit, and this unit is repeatedly disposed in the X-direction. That is, the bit line contacts CBa and CBb are disposed so as to have a so-called two-adjacent staggered disposition.
As described above, in the third embodiment, the bit line contacts CBa and CBb are disposed in a zigzag shape (a so-called two-adjacent staggered disposition in which two-successive contacts are set as a repetition unit of a zigzag structure) in which the positions of the bit line contacts are sequentially shifted in the Y-direction on two directly adjacent element regions Sa (Sa1 and Sa2). Accordingly, a distance in the Y-direction between the adjacent bit line contacts CB (between CBa and CBb) is greater than the spacing between adjacent element formation regions, and thus it is possible to increase the distance between the adjacent bit line contacts CB. Although not shown in the drawing, a source line contact is formed on the element region Sa between the pair of selection gate lines SGL2 and SGL2.
As described above, this embodiment is applied to a case where the bit line contact CB is formed on the element region Sa which is formed to have a minimum dimension in the X-direction.
As shown in
This is a basic configuration of the NAND-type flash memory device 1 to which this embodiment is applied.
Next, a structure according to the first embodiment will be described with reference to
The element regions Sa and the element isolation areas Sb are alternately disposed in the X-direction in the semiconductor substrate 10. An element isolation insulating film 20 is formed in the element isolation area Sb. For example, a silicon substrate may be used as the semiconductor substrate 10. For example, a silicon oxide film may be used as the element isolation insulating film 20.
A first insulating film 22, a second insulating film 24, and a third insulating film 26 are formed on the semiconductor substrate 10. For example, a silicon substrate may be used as the semiconductor substrate 10. For example, a silicon oxide film may be used as the first insulating film 22 and the third insulating film 26. For example, a silicon nitride film may be used as the second insulating film 24.
The first contact plug 34 passes through the first, second and third insulating films 22, 24 and 26 and contacts the semiconductor substrate 10 at an element formation region Sa. The first contact plug 34 includes an outer first conductive film 28, an intermediate second conductive film 30, and an inner third conductive film 32. For example, titanium nitride (TiN) may be used as the first conductive film 28. In addition, a stacked film of titanium (Ti) and titanium nitride may be used as the first conductive film. The first conductive film 28 functions as a barrier metal for suppressing the formation of a silicide of the material of the third conductive film due to reaction between the third conductive film 32 and the semiconductor substrate 10 (silicon). It is possible to use a metal as the second conductive film 30 and the third conductive film 32 and to use, for example, tungsten as the metal. The second conductive film 30 and the third conductive film 32 may be different portions of one body, and a boundary therebetween may not be recognized in an actual device.
In addition, the first contact plug 34 includes the first not in the figures. The upper end of the first contact plug 34 in the Z-direction is the first portion 34a and the lower end thereof in the Z-direction is the second portion 34b. The width of the first portion 34a (minor axis of the first portion 34a which is an ellipse) is larger than the width of the second portion 34b (minor axis of the second portion 34b which is an ellipse). In addition, a step is present at the boundary between the first portion 34a and the second portion 34b. The step in the contact plug 34 is located in the second insulating film 24. Although not shown in the drawing, the same relationship is established also in the major axis direction of the first contact plug 34.
The second portion 34b is composed of the first conductive film 28, as the second conductive film 30 and the third conductive film 32 are not formed in the second portion. The first portion 34a is composed of a stacked film in which the first conductive film 28, the second conductive film 30, and the third conductive film 32 are sequentially located from the exterior of the contact plug 34.
The bottom of the first contact plug 34 (bottom of the second portion 34b) extends into a recessed portion in the element formation region Sa, which is formed as a groove extending downwardly in the Z-direction from the surface of the element region Sa (semiconductor substrate 10), and thus extends into the element region Sa. For this reason, the contact area between the first contact plug 34 and the element region Sa is increased in comparison to a situation where a flat bottom of a contact plug is contacted against the element formation region Sa, and thus it is possible to reduce contact resistance between the contact plug 34 and the element formation region Sa (semiconductor substrate 10).
A fourth insulating film 36 is formed on the third insulating film 26. A second contact plug 38 extends through the fourth insulating film 36 to contact the first contact plug 34. Wirings 40 are formed on the fourth insulating film 36 and contact the top surface of the second contact plug 38. The wirings 40 extend in the Y-direction and are disposed in parallel so as to have a line-and-space configuration in the X-direction. The second contact plug 38 and the wiring 40 are formed of a metal film, and it is possible to use, for example, tungsten as the metal film. The wiring 40 is disposed in substantially the same layout as the element region Sa when seen in a plan view.
As described above, in the NAND-type flash memory device 1 according to the first embodiment, the first contact plug 34 configuring the bit line contact CB includes the first portion 34a and the second portion 34b. The first portion 34a is formed on the upper end in the Z-direction, and the second portion 34b is disposed on the lower end in the Z-direction. The width of the first portion 34a (minor axis of the first portion 34a which is an ellipse) is larger than the width of the second portion 34b (minor axis of the second portion 34b which is an ellipse). The second portion 34b is composed of the first conductive film 28, and the second conductive film 30 and the third conductive film 32 are not formed in the second portion. The first portion 34a is composed of a stacked film of the first conductive film 28, the second conductive film 30, and the third conductive film 32.
Based on the above-described structure, the bit line contact CB may achieve a contact having a small bottom diameter in the second portion 34b located at the lower side. Thus, it is possible to suppress the deterioration of a breakdown voltage between the adjacent bit line contacts CB. In addition, it is possible to achieve a contact having a large diameter in the first portion 34a located at the upper side. For this reason, the formation of voids in the bit line contact plug structure is suppressed, and thus it is possible to reduce the occurrence of an open failure.
(Manufacturing Method According to First Embodiment)Next, a method of manufacturing the NAND-type flash memory device 1 according to the first embodiment will be described with reference to
First, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Meanwhile, the material of the spacer insulating film 52 (52b) is a silicon oxide film which is the same as those of the third insulating film 26 and the first insulating film 22, but the spacer insulating film 52 is formed so that the film material thereof becomes sparse. Accordingly, the spacer insulating film 52 has a higher etching rate based on the diluted hydrofluoric acid solution, and thus it is possible to selectively remove the sidewall film 52b.
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
According to this embodiment, it is possible to reduce the diameter of the contact in the second portion 34b which is a lower portion of the first contact plug 34. Thus, it is possible to suppress a short circuit between the element regions Sa (active areas) adjacent to each other and to suppress the deterioration of a breakdown voltage.
In addition, it is possible to increase the diameter of the contact in the first portion 34a which is the upper portion of the first contact plug 34. Thus, it is possible to suppress the occurrence of an open failure due to the formation of a void caused by defective filling of tungsten formed within the contact hole 50.
According, since the first contact plug 34 may be formed without reducing the thickness of the first conductive film 28, it is possible to exhibit a sufficient barrier effect on the formation of tungsten of the first conductive film 28 and to suppress the occurrence of a contact leakage.
In addition, since the first contact plug 34 may be formed without reducing the thickness of the second conductive film 30 serving as a seed layer for forming tungsten, it is possible to suppress the generation of a void due to a film formation failure of the third conductive film 32.
Therefore, it is possible to provide a semiconductor device with high reliability by using this embodiment.
Second EmbodimentNext, a second embodiment in which a NAND-type flash memory device is applied as a semiconductor device will be described with reference to
An equivalent circuit of a memory cell array and a layout pattern of a memory cell region M of a NAND-type flash memory device 1 according to a second embodiment have the same configurations as those shown in
According to the second embodiment, the same effects as in the first embodiment are obtained. In addition, according to the second embodiment, it is possible to control the size of the diameter of the first portion 34a which is an upper portion of the first contact plug 34 by adjusting the film thickness of the sidewall film 52c. Accordingly, it is possible to make the diameter of the first portion 34a have an appropriate size in association with the finished dimension of the contact hole 50 and the selection of the film thicknesses of the first conductive film 28, the second conductive film 30, and the third conductive film 32.
Third EmbodimentNext, a third embodiment in which a NAND-type flash memory device is applied as a semiconductor device will be described with reference to
An equivalent circuit of a memory cell array of a NAND-type flash memory device 1 according to the third embodiment has the same configuration as that shown in
As shown in
As described above, in the third embodiment, the bit line contacts CBa, CBb, and CBc are disposed in a zigzag shape (a so-called three-successive zigzag disposition in which three-successive contacts are set as a repetition unit of a zigzag structure) in which the positions of the bit line contacts are sequentially shifted in the Y-direction on three element regions Sa (Sa1, Sa2, and Sa3) which are successively adjacent to each other, when seen in a plan view (when seen in a top view). Accordingly, a distance in the Y-direction between the bit line contacts CB (between CBa and CBb) becomes longer, and thus it is possible to further increase the distance between the bit line contacts CB adjacent to each other.
As described above, according to the NAND-type flash memory device 1 according to the third embodiment the same effects as those in the first embodiment may be exhibited. In addition, according to the third embodiment, the bit line contacts CB successively disposed are formed to have a three-successive zigzag disposition, and thus a distance between the bit line contacts CB adjacent to each other is increased. Accordingly, it is possible to more remarkably obtain effects of suppressing a short circuit between the bit line contacts CB adjacent to each other, that is, between the element regions Sa (active areas) adjacent to each other and suppressing the deterioration of a breakdown voltage.
Other EmbodimentsAs described above, a two-successive staggering disposition is illustrated and described in the first and second embodiments and a three-successive zigzag disposition is illustrated and described in the third embodiment. However, this is just an example, and any N-successive zigzag disposition (N is a fixed integer of 2 or greater) such as a four-successive zigzag disposition and a five-successive zigzag disposition may be used.
In the above-described embodiments, a description is given on the assumption that the bit line contact CB has an elliptical shape when seen in a plan view, but the exemplary embodiment is not limited thereto. For example, the bit line contact may have substantially a perfect circle shape.
In the above-described embodiments, a case is described in which the bit line contacts CB are successively formed on the element regions Sa, having a line-and-space shape, which are disposed to have a minimum pitch and a minimum dimension, but the exemplary embodiment is not limited thereto. The effects of this embodiment may be obtained in a situation where a contact is formed on a narrow pattern. Accordingly, the above-described embodiment may be applied to, for example, a contact which is formed independently without being formed successively. In addition, a region to which a contact is connected is not limited to an element region and may be a wiring or the like.
In the above-described embodiments, an example in which a NAND-type flash memory device is used is described, but a NOR-type flash memory device, a non-volatile semiconductor memory device such as an EPROM, a semiconductor memory device such as a DRAM or an SRAM, or a logic semiconductor device such as a microcomputer may be used.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Claims
1. A semiconductor device comprising:
- a substrate;
- a plurality of element regions that are positioned in a line-and-space shape and extend in a first direction in the substrate;
- a plurality of selection gates that are formed on the substrate to extend in a second direction intersecting the first direction; and
- a contact region that includes a plurality of contact plugs which are provided between two selection gates adjacent to each other and connected to the respective element regions in the substrate,
- wherein the contact plug includes an upper portion and a lower portion, the upper portion having a first width and being buried by a stacked film including a first conductive film and a second conductive film and the lower portion having a second width smaller than the first width and being buried by the first conductive film.
2. The semiconductor device according to claim 1, wherein
- in the upper portion of the contact plug, the first conductive film is located around the second conductive film.
3. The semiconductor device according to claim 1, further comprising:
- a plurality of memory cells; and
- a plurality of memory blocks each of which includes the plurality of memory cells and the plurality of selection gates,
- wherein two selection gates adjacent to each other are included in the memory blocks adjacent to each other.
4. The semiconductor device according to claim 1, wherein
- the contact plug has a step in a boundary between the upper portion and the lower portion.
5. The semiconductor device according to claim 4, wherein
- the step of the contact plug is positioned higher than a surface of the substrate.
6. The semiconductor device according to claim 4, wherein
- a silicon oxide film is formed on the substrate,
- a silicon nitride film is formed on the silicon oxide film, and
- the step of the contact plug is positioned within the silicon nitride film.
7. The semiconductor device according to claim 1, wherein
- the second conductive film is a two-layered conductive film.
8. The semiconductor device according to claim 1, wherein
- a recessed portion is formed in the substrate positioned directly below the contact plug.
9. The semiconductor device according to claim 1, wherein
- the first conductive film contains titanium nitride, and
- the second conductive film contains tungsten.
10. A semiconductor device comprising:
- a substrate;
- a plurality of element regions that are partitioned in a line-and-space shape and extend in a first direction in the substrate;
- a plurality of selection gates that are formed on the substrate to extend in a second direction intersecting the first direction; and
- a contact region that includes a plurality of contact plugs which are provided between two selection gates adjacent to each other and connected to the respective element regions in the substrate,
- wherein the contact region includes a plurality of units in which N contact plugs, where N is an integer of 2 or greater, are formed on N adjacent element regions, wherein each plurality of units are spaced along a straight line intersecting the first direction and the second direction, and
- wherein the contact plug includes an upper portion and a lower portion, the upper portion having a first width and being buried by a stacked film including a first conductive film and a second conductive film and the lower portion having a second width smaller than the first width and being buried by the first conductive film.
11. The semiconductor device according to claim 10, wherein
- the contact plug further comprises a step at the boundary between the upper portion and the lower portion thereof.
12. The semiconductor device according to claim 11, wherein
- the step of the contact plug is positioned higher than a surface of the substrate.
13. The semiconductor device according to claim 11, wherein
- a silicon oxide film is formed on the substrate,
- a silicon nitride film is formed on the silicon oxide film, and
- the step of the contact plug is positioned within the silicon nitride film.
14. The semiconductor device according to claim 10, wherein
- the second conductive film is a two-layered conductive film.
15. The semiconductor device according to claim 10, wherein
- a recessed portion is formed in the substrate positioned directly below the contact plug.
16. The semiconductor device according to claim 10, wherein
- the first conductive film contains titanium nitride, and
- the second conductive film contains tungsten.
17. A semiconductor device comprising:
- a plurality of conductive regions which are arranged in a line-and-space shape and extend in a first direction; and
- a contact region that includes a plurality of contact plugs which are connected to the respective conductive regions,
- wherein the contact plug includes an upper portion and a lower portion, the upper portion having a first width and being buried by a stacked film including a first conductive film and a second conductive film and the lower portion having a second width smaller than the first width and being buried by the first conductive film.
18. The semiconductor device according to claim 17, wherein
- the contact plug has a step in a boundary between the upper portion and the lower portion.
19. The semiconductor device according to claim 18, wherein
- the step of the contact plug is positioned higher than a surface of the conductive region.
20. The semiconductor device according to claim 18, wherein
- a silicon oxide film is formed on the conductive region,
- a silicon nitride film is formed on the silicon oxide film, and
- the step of the contact plug is positioned within the silicon nitride film.
Type: Application
Filed: Mar 3, 2015
Publication Date: Dec 17, 2015
Inventor: Hideki INOKUMA (Yokkaichi Mie)
Application Number: 14/636,730