PEAK-BUCK PEAK-BOOST CURRENT-MODE CONTROL FOR SWITCHED STEP-UP STEP-DOWN REGULATORS
A peak-buck peak-boost current mode control structure and scheme for a synchronous four-switch and non-synchronous two-switch buck-boost regulators sense input and output voltages to smoothly transition between buck mode, buck-boost mode, and boost mode for high power efficiency and low output ripples. With the inductor current sensing, the control scheme achieves the best performance in continuous conduction and discontinuous condition mode operations.
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The present application is related to and claims priority of U.S. provisional patent application (“Provisional Application I”), Ser. No. 62/088,433, entitled “Peak-Buck Peak-Boost Current-Mode Control for Switched Step-up Step-down Regulators,” filed on Dec. 5, 2014. The disclosure of Provisional Application I is hereby incorporated by reference in its entirety.
The present application is also related to U.S. provisional patent application (“Provisional Application II”), Ser. No. 62/054,587, entitled “DCR inductor current sensing for 4 switch buck-boost converters,” filed on Sep. 24, 2014. The disclosure of the Provisional Application II is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to switched step-up step-down regulators, and more particularly, to the control of such switched step-up step-down regulators using a current-mode control scheme.
2. Discussion of the Related Art
Step up-step down or buck-boost switching regulators handle input voltages that can be above, below, or equal to the output voltage.
Hysteretic mode control schemes, e.g., those disclosed in Sluijs, typically switch among different operating states based on monitoring an output voltage using a window comparator. Disadvantages of a hysteretic mode control scheme include: the varying switching frequency is load-dependent, high output voltage ripples, and high noise mode transition.
Voltage mode control schemes, e.g., those disclosed in Volk, Dwelley and Ikezawa, are widely used in commercial buck-boost regulators. Voltage mode control schemes offer fixed switching frequency, low output voltage ripples, and low noise mode transition. However, the voltage mode control schemes typically run in forced continuous conduction mode, in which the inductor current can flow from the output terminal to the input terminal. The forced continuous conduction mode operation is not suitable for some applications (e.g., a battery charger application) that do not allow reverse currents. For such applications, a pulse-skip or burst discontinuous conduction mode operation handles the reverse current, when present. However, mode transitions in these control schemes generate large output transient ripples in the output load. Other disadvantages of the voltage mode control schemes include difficulty in compensating for a wide VIN range and no paralleling output capability.
The current mode control schemes, e.g., those disclosed in Zhou, Amram Summit, Flatness and Ren, allow easy compensation and parallel outputs.
According to one embodiment of the present invention, a peak-buck peak-boost current mode control scheme is applied to a synchronous four-switch buck-boost regulator or a non-synchronous two-switch buck-boost regulator. Such a peak-buck peak-boost current mode control scheme, which uses a single inductor sensing resistor to detect the inductor current, is capable of handling a reverse current, while achieving the benefits of low inductor current ripples, low output voltage ripples, and high power efficiency.
The control scheme of the present invention is applicable to both continuous conduction and discontinuous conduction operations, including pulse skip discontinuous conduction mode and burst mode discontinuous conduction mode operations. The peak-buck peak-boost current mode control scheme of the present invention may be applied to synchronous two-switch buck regulators, synchronous two-switch boost regulators, non-synchronous single-switch buck regulators and non-synchronous single-switch boost regulators.
According to one embodiment of the present invention, a peak-buck peak-boost control circuit for a voltage regulator may include (i) a mode selection circuit generating control signals representing (a) a first control state in which the input voltage is greater than the output voltage by at least a predetermined value; (b) a second control state in which the input voltage is greater than the output voltage less than or equal to the predetermined value; (c) a third control state in which the output voltage is greater than the input voltage by less than or equal to a second predetermined value; (d) a fourth control state in which the output voltage is greater than the input voltage by at least the predetermined value; and (ii) switch control signal generation circuit for generating control signals for operating switches in the voltage regulator, such that the voltage regulator is configured as (a) the buck regulator in the first control state, (b) a buck-boost regulator in the second and third control states, and (c) a boost regulator in the fourth control state.
The mode selection circuit may incorporate hysteresis for transitioning between the first and second control states, or for transitioning between the third and fourth control states. The output voltage may be provided as a scaled feedback signal. The voltage regulator may include an inductor and the peak-buck and peak-boost control scheme may use a ramping voltage signal to determine a peak value in a current flowing in the inductor. The peak value may be determined from the ramping voltage and an error signal derived from the output voltage. The occurrence of the peak value may be used to control switches in an output side of the voltage regulator. The error signal may be an amplified difference between a reference voltage and the output voltage. A compensation circuit receiving the error signal may be provided for ensuring loop stability in the voltage regulator.
The peak-buck peak-boost control scheme of the present invention may also determine an occurrence of the peak current using the ramping voltage, an offset voltage and an error signal derived from the output voltage. The offset voltage may be derived from a difference in voltage at two time points of the ramping voltage. The two time points are specific time points within a switching cycle of the peak-buck peak-boost control circuit. The occurrence of the peak value may be used to control switches in an input side of the voltage regulator.
The current mode control scheme of the present invention may also be used in conjunction with any inductor current-sensing method disclosed in provisional Application II.
The present invention is better understood upon consideration of the detailed description below in conjunction with the accompanying drawings.
To facilitate cross-referencing among the figures, like elements are assigned like reference numerals.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTSControl circuit 700 operates a regulator under one of four operating modes: (a) when input voltage VIN is much higher than output voltage VOUT; (b) when input voltage VIN is much lower than output voltage VOUT; (c) when input voltage VIN is slightly higher than output voltage VOUT, and (d) when input voltage VIN is slightly lower than output voltage VOUT. When input voltage VIN is much higher than output voltage VOUT, the regulator is operated under a pure buck mode with peak-buck current mode control (“peak-buck buck mode”). When input voltage VIN is much lower than output voltage VOUT, the regulator is operated under a pure boost mode with peak-boost current mode control (“peak-boost boost mode”). When input voltage VIN is slightly higher than output voltage VOUT, the regulator is operated under a buck-boost mode with peak-buck current mode control (“peak-buck buck-boost mode”). When input voltage VIN is slightly lower than output voltage VOUT, the regulator is operated under a buck-boost mode with peak-boost current mode control (“peak-boost buck-boost mode”).
Based on the values of input signal VIN and output signal VOUT, mode selection circuit 720 (
As shown in
In each of regulator circuits 500 and 600, current IL in inductor L is sensed through sense resistor RS. As shown in
Compensation network 711 provides loop stability based on error signal VC. The output signals from amplifier 702 and error amplifier 704, slope compensation signal VSLP, and slope compensation offset signal VOS are provided to buck current comparator 705 and boost current comparator 706. According to the operating mode set by mode selection circuit 720, buck logic circuit 721 and boost logic circuit 722 provide control signals A, B, C and D, which are used to the respective control switches SA, SB, SC, and SD in circuits 500 and 600.
The control schemes of the present invention are applicable to continuous conduction mode and pulse-skip and burst discontinuous conduction modes.
As shown in
When input voltage VIN is slightly higher than output voltage VOUT, the regulator is operated under peak-buck buck-boost mode (PK_BUK=‘1’, ON_BUK=‘1’, and ON_BST=‘1’) according to steps 1011-1013.
When input voltage VIN is much lower than output voltage VOUT (PK_BST=‘1’, ON_BUK=‘0’, and ON_BST=‘1’), the regulator is operated under the peak-boost boost mode, according to steps 1006-1007.
When input voltage VIN is slightly lower than output voltage VOUT (PK_BST=‘1’, ON_BUK=‘1’, and ON_BST=‘1’), the regulator is operated under a peak-boost buck-boost mode, according to steps 1008-1010.
In either peak-buck buck-boost mode (i.e., the operating condition of
The above detailed description is provided to illustrate the specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the claims.
Claims
1. A peak-buck peak-boost control circuit for a voltage regulator capable of being configured as a buck regulator, a buck-boost regulator or a boost regulator, the buck-boost regulator receiving an input voltage and providing an output voltage.
2. The peak-buck peak-boost control circuit of claim 1, comprising:
- a mode selection circuit generating control signals representing (a) a first control state in which the input voltage is greater than the output voltage by at least a predetermined value; (b) a second control state in which the input voltage is greater than the output voltage less than or equal to the predetermined value; (c) a third control state in which the output voltage is greater than the input voltage by less than or equal to a second predetermined value; (d) a fourth control state in which the output voltage is greater than the input voltage by at least the predetermined value; and
- a switch control signal generation circuit for generating control signals for operating switches in the voltage regulator, such that the voltage regulator is configured as (a) a buck regulator in the first control state, (b) a buck-boost regulator in the second and third control states, and (c) a boost regulator in the fourth control state.
3. The peak-buck peak-boost control circuit of claim 2, wherein the mode selection circuit incorporates hysteresis for transitioning between the first and second control states, or for transitioning between the third and fourth control states.
4. The peak-buck peak-boost control circuit of claim 2, wherein the output voltage is provided as a scaled feedback signal.
5. The peak-buck peak-boost control circuit of claim 2, wherein the voltage regulator comprises an inductor and wherein the switch control signal generation circuit includes a signal generator that provides a ramping voltage signal and a current sense amplifier that determines a peak value in a current flowing in the inductor.
6. The peak-buck peak-boost control circuit of claim 5, wherein the ramping voltage signal comprises a linear segment.
7. The peak-buck peak-boost control circuit of claim 5, wherein the current flowing in the inductor is determined from a voltage across a sense resistor.
8. The peak-buck peak-boost control circuit of claim 5, wherein the switch control signal generation circuit comprises a first comparator that determines an occurrence of the peak value using the ramping voltage, the inductor current, and an error signal derived from the output voltage.
9. The peak-buck peak-boost control circuit of claim 8, wherein the first comparator controls switches in an output side of the voltage regulator.
10. The peak-buck peak-boost control circuit of claim 9 wherein, when in either the third control state or the fourth control state, in response to the occurrence of the peak value, the switch control signal generation circuit closes a switch connecting the inductor from an output terminal of the voltage regulator and opens a switch connecting the inductor to a ground reference.
11. The peak-buck peak boost control circuit of claim 10 wherein, in the third control state, at a predetermined time following the occurrence of the peak value, the switch control signal generation circuit opens a switch connecting the inductor from an input terminal of the voltage regulator and closes a switch connecting the inductor to a ground reference.
12. The peak-buck peak-boost control circuit of claim 8, wherein the error signal is an amplified difference between a reference voltage and the output voltage.
13. The peak-buck peak-boost control circuit of claim 8, further comprising a compensation circuit receiving the error signal for providing loop stability in the voltage regulator.
14. The peak-buck peak-boost control circuit of claim 5, wherein the switch control signal generation circuit comprises a second comparator that determines an occurrence of the peak current using the ramping voltage, the inductor current, an offset voltage and an error signal derived from the output voltage.
15. The peak-buck peak-boost control circuit of claim 14, wherein the offset voltage is derived from a difference in voltage at two time points of the ramping voltage.
16. The peak-buck peak-boost control circuit of claim 15, wherein the two time points are specific time points within a switching cycle of the peak-buck peak-boost control circuit.
17. The peak-buck peak-boost control circuit of claim 14, wherein the comparator controls switches in an input side of the voltage regulator.
18. The peak-buck peak-boost control circuit of claim 17 wherein, when in either the first control state or the second control state, in response to the occurrence of the peak value, the switch control signal generation circuit opens a switch connecting the inductor from an input terminal of the voltage regulator and closes a switch connecting the inductor to a ground reference.
19. The peak-buck peak boost control circuit of claim 18 wherein, in the second control state, at a predetermined time, the switch control signal generation circuit closes a switch connecting the inductor from an output terminal of the voltage regulator and opens a switch connecting the inductor to a ground reference.
20. In a voltage regulator capable of being configured as a buck regulator, a buck-boost regulator or a boost regulator, the buck-boost regulator receiving an input voltage and providing an output voltage, a method for controlling the voltage regulator comprising:
- selecting a mode of operation based on determining (a) a first control state in which the input voltage is greater than the output voltage by at least a predetermined value; (b) a second control state in which the input voltage is greater than the output voltage less than or equal to the predetermined value; (c) a third control state in which the output voltage is greater than the input voltage by less than or equal to a second predetermined value; (d) a fourth control state in which the output voltage is greater than the input voltage by at least the predetermined value; and
- generating switch control signals for operating switches in the voltage regulator, such that the voltage regulator is configured as (a) a buck regulator in the first control state, (b) a buck-boost regulator in the second and third control states, and (c) a boost regulator in the fourth control state.
21. The method of claim 20, wherein selecting the mode of operation further comprises incorporating hysteresis for transitioning between the first and second control states, or for transitioning between the third and fourth control states.
22. The method of claim 20, wherein the output voltage is provided as a scaled feedback signal.
23. The method of claim 20, wherein the voltage regulator comprises an inductor and wherein generating the switch control signals includes using a ramping voltage signal to determine a peak value in a current flowing in the inductor.
24. The method of claim 23, wherein the ramping voltage signal comprises a linear segment.
25. The method of claim 23, wherein the current flowing in the inductor is determined from a voltage across a sense resistor.
26. The method of claim 23, wherein generating the switch control signals comprises determining an occurrence of the peak value using the ramping voltage, the inductor current, and an error signal derived from the output voltage.
27. The method of claim 26, wherein the occurrence of the peak value determines switching in switches in an output side of the voltage regulator.
28. The method of claim 27 further comprising, when in either the third control state or the fourth control state, in response to the occurrence of the peak value, closing a switch that connects the inductor from an output terminal of the voltage regulator and opening a switch that connects the inductor to a ground reference.
29. The method of claim 28 further comprising, in the third control state, at a predetermined time following the occurrence of the peak value, opening a switch that connects the inductor from an input terminal of the voltage regulator and closing a switch that connects the inductor to a ground reference.
30. The method of claim 26, wherein the error signal is an amplified difference between a reference voltage and the output voltage.
31. The method of claim 26, further comprising compensating for loop stability in the voltage regulator using the error signal.
32. The method of claim 23, wherein generating the switch control signals comprises determining an occurrence of the peak current using the ramping voltage, the inductor current, an offset voltage and an error signal derived from the output voltage.
33. The method of claim 32, wherein the offset voltage is derived from a difference in voltage at two time points of the ramping voltage.
34. The method of claim 33, wherein the two time points are specific time points within a switching cycle of the control method.
35. The method circuit of claim 33, wherein the occurrence of the peak current controls switching in switches in an input side of the voltage regulator.
36. The method of claim 35 further comprising, when in either the first control state or the second control state, in response to the occurrence of the peak value, opening a switch that connects the inductor from an input terminal of the voltage regulator and closing a switch that connects the inductor to a ground reference.
37. The peak-buck peak boost control circuit of claim 36 further comprising, in the second control state, at a predetermined time, the switch control signal generation circuit closing a switch that connects the inductor from an output terminal of the voltage regulator and opening a switch that connects the inductor to a ground reference.
Type: Application
Filed: Mar 17, 2015
Publication Date: Jun 9, 2016
Applicant:
Inventors: Min Chen (Milpitas, CA), Bryan Avery Legates (Los Altos, CA)
Application Number: 14/660,739