SILICON-GLASS HYBRID INTERPOSER CIRCUITRY
An interposer is provided. The interposer includes a silicon substrate layer, a glass substrate layer, and at least one through interposer via. The silicon substrate layer is formed on top of the glass substrate layer. The interposer may also be known as a hybrid interposer because it includes two different types of substrate layers forming one interposer. The through interposer via is formed to go through the silicon substrate layer and the glass substrate layer. The interposer may be used for forming an integrated circuit package. The integrated circuit package includes multiple integrated circuits that are mounted on the interposer.
This application is a continuation of U.S. patent application Ser. No. 14/185,631, filed Feb. 20, 2014, which is hereby incorporated by reference herein in its entirety. This application claims the benefit of and claims priority to U.S. patent application Ser. No. 14/185,631, filed Feb. 20, 2014.
BACKGROUNDIntegrated circuit devices with multiple stacked integrated circuits often include an interposer as a medium to couple the different integrated circuits together. The interposer is generally placed between the integrated circuits and a package substrate. The interposer may have signal pathways that can be used for transmitting data between two or more integrated circuits mounted on the interposer, or between one of the integrated circuits on the interposer and components mounted directly on the package substrate.
Interposers are typically formed from silicon substrates. However, interposers formed from silicon wafers may be brittle. Hence, complex manufacturing processes may be required to produce such interposers. Active and passive devices may be embedded in the silicon interposers. However, they usually have poor signal transmission characteristics (e.g., poor insertion loss and poor return loss). Therefore, silicon interposers may be unsuitable for high frequency applications.
Another type of wafer that may be used to form interposers is a glass wafer (or a non-semiconductor wafer). A glass interposer does not include any silicon substrate material and may exhibit better signal transmission characteristics compared to a silicon interposer. However, active circuits (i.e., transistor) cannot be embedded in a glass interposer.
SUMMARYEmbodiments described herein include a hybrid interposer and a method of manufacturing the hybrid interposer. It should be appreciated that the embodiments can be implemented in numerous ways, such as a process, an apparatus, a system, a device, or a method. Several embodiments are described below.
In one embodiment, an interposer is described. The interposer includes a silicon substrate layer, a glass substrate layer, and at least one through interposer via. The silicon substrate layer is formed on top of the glass substrate layer. The interposer may also be known as a hybrid interposer because it includes two different types of substrate layers forming one interposer. The through interposer via is formed to go through the silicon substrate layer and the glass substrate layer.
In another embodiment, the interposer described in the above embodiment may be used for forming an integrated circuit package. The integrated circuit package includes multiple integrated circuits that are mounted on the interposer.
In addition to that, a method of manufacturing a hybrid interposer having a glass wafer is described. The method includes a step to form a silicon wafer on the glass wafer. Next, the method includes a step to form a plurality of microbumps for the hybrid interposer. Finally, the method includes a step to form a plurality of flip-chip bumps for the hybrid interposer.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
The following embodiments describe a hybrid interposer and a method to manufacture the hybrid interposer. It will be obvious, however, to one skilled in the art, that the present exemplary embodiments may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail in order not to unnecessarily obscure the present embodiments.
Integrated circuit package 100 may be placed on a printed circuit board (PCB). Each solder ball 170 on integrated circuit package 100 may be coupled to a solder pad on the PCB (not shown). In one embodiment, integrated circuit package 100 may transmit signals to a device mounted on the PCB through signal pathways that are coupled to solder balls 170.
Integrated circuit package 100 may form a part of a wireless system, a wired system, or other types of systems. Hence, integrated circuit package 100 may include circuits that perform various functions that define the system.
In one embodiment, integrated circuit package 100 may be an application specific integrated circuit (ASIC) device or an application specific standard product (ASSP) device, such as, a memory controller device. The memory controller device may be utilized for controlling data transfer between a memory device and other devices, for example, a microprocessor device. In order to support the data transfer, integrated circuit package 100 may include circuits that handle different protocol standards.
Alternatively, integrated circuit package 100 may be a programmable logic device (PLD), for example, a field programmable gate array (FPGA) device. It should be noted that a PLD may be configured to implement different user designs or applications. In one exemplary embodiment, the PLD may be configured as a memory controller. In another exemplary embodiment, the PLD may be configured as an arithmetic logic unit (ALU).
Integrated circuit package 100 may also be a multi-chip package or system-on-package (SoP) device with more than one integrated circuit within integrated circuit package 100. Even though two integrated circuits 130 and 140 are shown in
Referring still to
In one embodiment, integrated circuits 130 and 140 may be different types of devices, for example, an FPGA die and a memory die, respectively. Alternatively, integrated circuit 130 and 140 may be similar types of devices, for example, FPGA dies. It should be appreciated that combining different types of integrated circuits 130 and 140 may yield different functions for integrated circuit package 100.
Referring still to
As described above, integrated circuits 130 and 140 are attached to interposer 150 instead of being directly attached to package substrate 160 because of the finer width signal pathways (not shown) achievable on interposer 150 compared to package substrate 160. It should be noted that interposer 150 may have finer width (e.g. 3-5 microns (μm)) signal pathways because manufacturing processes that are available for interposer 150 are generally more advanced than manufacturing processes that are available for package substrate 160. Furthermore, the fine width for signal pathways may also be achieved because the dielectric constant of interposer 150 may be greater than the dielectric constant of package substrate 160. A person skilled in the art appreciates that the width of signal pathways may be inversely proportional to the value of dielectric constant for a particular characteristic impedance. Therefore, a higher dielectric constant for interposer 150 may allow manufacturing of finer signal pathways (for particular characteristic impedance).
Referring still to
In one embodiment, glass substrate 210 may be a sodium-containing Borofloat or Pyrex® glass. It should be appreciated that there many other types of glass substrate that are available which may be used as glass substrate 210. Glass substrate 210 may have better chemical durability, thermal stability, and optical properties than silicon substrates. However, glass substrate 210 and silicon substrate generally have similar structural stability. Glass substrate 210 may also have better signal transmission properties than silicon substrates.
Alternatively, silicon layer 220 may be bonded to the top surface of glass substrate 210 using a direct oxide bonding process. The direct oxide bonding process may be similar to the Ziptronix™ Zibond™ bonding process. It should be appreciated that other direct oxide bonding processes may also exist to bond silicon layer 220 onto glass substrate 210.
Referring still to
STI 232 may be formed on silicon layer 220A to prevent electrical current leakage. For example, STI 232 may prevent electrical current leakage between two circuits formed on two different sides of STI 232 on the surface of silicon layer 220A.
Insulation liner 231 may be utilized to separate a conductive portion of a TIV (e.g., TIV 250A of
IMD layer 240 may be utilized to route signals to transistor 233 (or any other circuits that may be formed in silicon layer 220A). IMD layer 240 may be composed of a dielectric material, for example, silicon nitride (SiN) or silicon carbide (SiC). IMD layer 240 may also include passive circuits (not shown), for example, capacitors or inductors, in one embodiment. In one embodiment, IMD layer 240 may include multiple routing layers (not shown in
Hole 250 may be drilled for the purpose of forming TIV 250A of
Referring still to
Referring still to
At step 320, a bottom surface of the silicon substrate is bonded to an upper surface of the glass substrate. Anodic bonding or direct oxide bonding may be used to bond the two substrates and the bonded substrates may be similar to the structure shown in
At step 340, a through interposer via (TIV) that extends from an upper surface of silicon substrate to bottom surface of the glass substrate may be formed. The TIV may be similar to TIV 250A of
At step 350, an inter-metal dielectric (IMD) layer may be formed above the top surface of the silicon substrate. The IMD layer may be similar to IMD layer 240 of
Line 410 represents the insertion loss of a signal that is transmitted via a TIV while line 420 represents the insertion loss of a signal that is transmitted via a TSV. As shown in
The embodiments thus far have been described with respect to integrated circuits. The methods and apparatuses described herein may be incorporated into any suitable circuit. For example, they may be incorporated into numerous types of devices such as programmable logic devices, application specific standard products (ASSPs), and application specific integrated circuits (ASICs). Examples of programmable logic devices include programmable arrays logic (PALs), programmable logic arrays (PLAs), field programmable logic arrays (FPGAs), electrically programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), logic cell arrays (LCAs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs), just to name a few.
The programmable logic device described in one or more embodiments herein may be part of a data processing system that includes one or more of the following components: a processor; memory; IC circuitry; and peripheral devices. The data processing can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any suitable other application where the advantage of using programmable or re-programmable logic is desirable. The programmable logic device can be used to perform a variety of different logic functions. For example, the programmable logic device can be configured as a processor or controller that works in cooperation with a system processor. The programmable logic device may also be used as an arbiter for arbitrating access to a shared resource in the data processing system. In yet another example, the programmable logic device can be configured as an interface between a processor and one of the other components in the system. In one embodiment, the programmable logic device may be one of the family of devices owned by ALTERA Corporation.
Although the methods of operations were described in a specific order, it should be understood that other operations may be performed in between described operations, described operations may be adjusted so that they occur at slightly different times or described operations may be distributed in a system which allows occurrence of the processing operations at various intervals associated with the processing, as long as the processing of the overlay operations are performed in a desired way.
Although the foregoing invention has been described in some detail for the purposes of clarity, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.
Claims
1. An interposer, comprising:
- a glass substrate;
- a semiconductor layer formed on the glass substrate, wherein the semiconductor layer has a bottom surface that faces the glass substrate and a top surface;
- a transistor formed at the top surface of the semiconductor layer; and
- a dielectric layer formed over the transistor, wherein the dielectric layer and the glass substrate are formed from different materials.
2. The interposer of claim 1, wherein the glass substrate includes sodium.
3. The interposer of claim 1, wherein the glass substrate comprises Borofloat® glass.
4. The interposer of claim 1, wherein the glass substrate comprises Pyrex® glass.
5. The interposer of claim 1, wherein the semiconductor layer comprises a silicon layer, and wherein the glass substrate comprises a material that is different than the semiconductor layer.
6. The interposer of claim 1, wherein the glass substrate has a bottom surface that is at least partially exposed.
7. The interposer of claim 1, wherein the semiconductor layer exhibits a first signal transmission characteristic, and wherein the glass layer exhibits a second signal transmission characteristic that is better than the first signal transmission characteristic.
8. The interposer of claim 1, further comprising:
- a through-interposer via formed through the semiconductor layer and the glass substrate; and
- an insulating liner interposed between the through-interposer via and the semiconductor layer.
9. The interposer of claim 8, wherein the through-interposer via directly contacts the glass substrate.
10. The interposer of claim 1, further comprising:
- a bump metallization conductor formed directly on the glass substrate.
11. The interposer of claim 10, further comprising:
- a bump formed directly on the bump metallization conductor.
12. A method of fabricating a hybrid integrated circuit package interposer, comprising:
- forming a semiconductor layer on a glass substrate; and
- after forming the semiconductor layer on the glass substrate, forming a transistor in the semiconductor layer, wherein the semiconductor layer exhibits a first signal transmission property, and wherein the glass substrate exhibits a second signal transmission property that is better than the first signal transmission property.
13. The method of claim 12, wherein the glass substrate comprises material selected from the group consisting of: sodium, Borofloat® glass, and Pyrex® glass.
14. The method of claim 12, wherein the glass layer exhibits better insertion loss than the semiconductor layer.
15. The method of claim 12, further comprising:
- after forming the semiconductor layer on the glass substrate, forming a through hole in only the semiconductor layer but not the glass substrate.
16. A multichip package, comprising:
- a glass substrate;
- a silicon layer formed on the glass substrate;
- a dielectric layer formed on the silicon layer, wherein the dielectric layer and the glass substrate are formed from different materials; and
- an integrated circuit die mounted over the dielectric layer.
17. The multichip package of claim 16, wherein the silicon layer is thinner than the glass substrate.
18. The multichip package of claim 16, further comprising:
- a through-interposer via formed through the dielectric layer, the silicon layer, and the glass substrate.
19. The multichip package of claim 16, further comprising:
- an additional integrated circuit die mounted over the dielectric layer.
20. The multichip package of claim 16, further comprising:
- a package substrate to which the glass substrate is attached.
Type: Application
Filed: Jul 26, 2016
Publication Date: Nov 17, 2016
Inventor: Minghao Shen (San Jose, CA)
Application Number: 15/220,217