SYSTEMS AND METHODS FOR MONOLITHICALLY INTEGRATED BYPASS SWITCHES AND PHOTOVOLTAIC SOLAR CELLS
Structures and methods for a solar cell having an integrated bypass switch are provided. According to one embodiment, an integrated solar cell and bypass switch comprising a semiconductor layer has a background doping, a frontside, and a backside. A patterned first level metal is positioned over the layer backside and an electrically insulating backplane is positioned over the first level metal. A trench isolation pattern partitions the semiconductor layer into a solar cell region and at least one monolithically integrated bypass switch region. A patterned second level metal is positioned over the electrically insulating backplane and which connects to the first level metal through the backplane and electrically connects the monolithically integrated solar cell and bypass switch structure.
This application is a continuation of U.S. application Ser. No. 14/055,813 filed on Oct. 16, 2013 which claims the benefit of U.S. Provisional Application No. 61/714,723 filed on Oct. 16, 2012, which are hereby incorporated by reference in their entirety.
FIELD OF THE INVENTIONThe present disclosure relates in general to the fields of solar photovoltaic (PV) cells and modules, and more particularly to Monolithically Integrated Bypass Switches (MIBS) embedded in the module laminate for distributed integrated shade management resulting in enhanced power and energy harvesting in photovoltaic (PV) solar cells and modules.
BACKGROUNDCrystalline silicon photovoltaic (PV) modules currently (as of 2012), account for approximately over 85% of the overall global PV annual demand market and cumulative globally installed PV capacity. The manufacturing process for crystalline silicon PV is based on the use of crystalline silicon solar cells, starting with mono-crystalline or multi-crystalline silicon wafers made of czochralski (CZ) silicon ingots or cast silicon bricks. Non-crystalline-silicon-based thin film PV modules (e.g., such as CdTe, CIGS, organic, and amorphous silicon PV modules) may offer the potential for low cost manufacturing process, but typically provide much lower conversion efficiencies (in the range of single digit up to about 14% in STC module efficiency) for commercial thin-film PV modules compared to the mainstream crystalline silicon PV modules (which provide module efficiencies in the typical range of approximately 14% up to about 20%, and mostly in the range of about 14% to 17%, for commercial crystalline silicon modules), and an unproven long-term track record of field reliability compared to the well-established crystalline silicon solar PV modules. The leading-edge crystalline silicon PV modules offer superior overall energy conversion performance, long-term field reliability, non-toxicity, and life cycle sustainability compared to various other PV technologies. Moreover, recent progress and advancements have already driven the overall manufacturing cost of crystalline silicon PV modules to at or below approximately $0.65 to $0.80/Wp. Disruptive monocrystalline silicon technologies—such as high-efficiency thin monocrystalline silicon solar cells fabricated based on the use of reusable crystalline silicon templates, thin (e.g., crystalline silicon absorber thickness from approximately 10 μm up to about 100 μm, and typically ≦70 μm) epitaxial silicon, thin silicon support using backplane attachment/lamination, and porous silicon lift-off technology—offer the promise of high-efficiency (with solar cell and/or module efficiencies of at least 20% under Standard Test Conditions or STC) and PV module manufacturing cost at well below $0.50/Wp at mass manufacturing scale.
Solar cells used in photovoltaic (PV) modules are essentially photodiodes—they directly convert the sunlight arriving at their light-receiving surface to electrical power through photo-generated charge carriers (typically electrons and holes) in the semiconductor absorber. In a module with a plurality of solar cells, any shaded cells cannot produce the same amount of electrical power (or electrical current) as the non-shaded cells laminated within the same PV module. Since all the cells laminated in a typical PV module are usually connected in series strings, differences in power also cause differences in photo-generated electrical currents through the cells (shaded vs. non-shaded cells). If one attempts to drive the higher current of the series-connected non-shaded cells through a shaded (or partially shaded) cell which is also connected in series with the non-shaded cells, the voltage of the shaded cell (or partially shaded cell) actually becomes negative (i.e., the shaded cell effectively becomes reverse biased). Under this reverse bias condition the shaded cell is consuming or dissipating significant power instead of producing power. The power consumed and dissipated by the shaded or partially-shaded cell will cause the cell to heat up, creating a localized hot spot within the module where the shaded cell is located, and eventually possibly causing permanent cell and module failure, hence creating major reliability failure problems in the field (unless protective measures are implemented).
A standard (i.e., typically a PV module comprising 60 solar cells) crystalline silicon PV module is typically wired into three 20-cell (or 24 cells in the case of 72-cell modules or 32 cells in the case of 96-cell modules) series-connected strings within the PV module, with each string of 20 cells protected by an external bypass diode (typically either a pn junction diode or a Schottky diode) placed in an external junction box. These strings of 20 cells are electrically connected in series to each other within the junction box to form the final PV module assembly electrical interconnections and to provide the output electrical leads of the module, typically comprising series-connected solar cells. As long as the PV module receives relatively uniform solar irradiation on its surface and no cells are shaded, the cells within the module will produce essentially equal amounts of power (and electrical current), with a cell maximum-power voltage or Vmp on the order of approximately ˜0.5 V to 0.6 V for most crystalline silicon PV modules. Hence, the maximum-power voltage or Vmp across each string of 20 cells connected in series will be approximately on the order of 10 to 12 V for a 60-cell PV module comprising three 20-cell series-connected sub-strings using crystalline silicon cells. Under a uniform module illumination condition, each external bypass diode will have about −10 to −12 V reverse bias voltage across its terminals (for instance, while the module operates at its maximum-power point or MPP) and the bypass diode remains in the reverse-biased OFF state (hence, there would be no impact on the module power output by the reverse biased external bypass diodes located in the junction box). In the case where a solar cell in a 20-cell string is partially or fully shaded, it produces less electrical power (and less electrical current) than the non-shaded cells. Since the cells in the string are usually connected in electrical series, the shaded solar cell effectively becomes reverse biased and starts to dissipate electrical power, and therefore, would create localized hot spot at the location of the reverse-biased shaded cell, instead of producing power. Unless appropriate precautions are taken, the power dissipation and the resulting localized heating of the shaded cell may result in poor cell and module reliability due to possible catastrophic failure (such as failure of the reverse-biased shaded cell, failure of cell-to-cell electrical interconnections, and/or failure of the module lamination materials such as the module encapsulant and/or backsheet), as well as possible fire hazards due to excessive heating or hot spots in the installed PV systems.
Crystalline silicon modules often use external bypass diodes in order to eliminate the above-mentioned hot-spot effects caused by the partial or full shading of solar cells, and to prevent the resulting potential cell and module reliability failures and safety hazards due to cell reverse bias heating. Such hot-spot phenomena, which are caused by reverse biasing of the shaded cells, may permanently damage the affected PV cells and even cause fire hazards if the sunlight arriving at the surface of the PV cells in a PV module is not sufficiently uniform (for instance, due to full or even partial shading of one or more solar cells). Bypass diodes (rectifiers) are usually placed across the sub-strings of solar cells within the PV module, typically one external bypass diode per sub-string of 20 solar cells in a standard 60-cell crystalline silicon solar module with three 20-cell sub-strings (the configuration may be one external bypass diode per sub-string of 24 solar cells in a 72-cell crystalline silicon solar module with three 24-cell sub-strings; many other configurations are possible for modules with any number of solar cells). This connection configuration with external bypass diodes across the series-connected cell strings prevents the reverse bias hot spots in the modules and enables the PV modules to operate with high reliability throughout their lifetime under various real life shading or partial shading or soiling conditions. In the absence of cell shading, each cell in the string acts as a current source with relatively matched current values with the other cells in the sub-string, with the external bypass diode in the sub-string being reversed biased with the total voltage of the sub-string in the module (e.g., 20 cells in series create approximately about 10 V to 12 V reverse bias across the bypass diode in a crystalline silicon PV module). With shading of a cell in a sub-string, the shaded cell is reverse biased, turning on the bypass diode for the sub-string containing the shaded cell, thereby allowing the current from the good solar cells in the non-shaded sub-strings to flow through the external bypass diode associated with the sub-string with a shaded cell. While the external bypass diodes (typically three external bypass diodes included in the standard mainstream 60-cell crystalline silicon PV module junction box) protect the PV module and cells in case of shading of the cells, they can also actually result in significant loss of power harvesting and energy yield for the installed PV systems as a result of shading losses.
As an example, a typical prior art external PV module junction box may house three external bypass diodes in a 60-cell crystalline silicon solar module. The external junction box and related external bypass diodes contribute to a portion of the overall PV module Bill of Materials (BOM) cost and may contribute about 10% (or about 5% to 15%) of the PV module BOM cost (i.e., as a percentage of the PV Module BOM cost excluding the cost of solar cells). Moreover, the external junction box may also be a source of field reliability failures and fire hazards in the installed PV systems. While most current crystalline silicon PV modules predominantly use external junction boxes with external bypass diodes placed in the junction box, there have been some examples of PV modules with front-contact cells placing and laminating the three bypass diodes directly within the PV module assembly, but separate from the front-contact solar cells, during the module lamination process (however, still using one bypass diode per 20-cell sub-string of front-contact cells). This example still has the limitations of external bypass diodes, i.e., even when a single cell is shaded, the bypass diode shunts the entire substring of cells with the shaded cell within the sub-string, thus, reducing the power harvesting and energy yield capability of the installed PV system.
One known prior art method to minimize the reliability failure effects of shading on a module in a series string of modules is to use bypass diodes across modules connected in series, as schematically shown in
In crystalline silicon PV system installations with multiple module strings, the module shading effects and their detrimental impact on power harvesting and energy yield may be much larger than the examples shown above with a single series string of modules. In solar PV systems with multiple parallel strings of series-connected module strings, the parallel strings must produce approximately the same voltage as one another (i.e., the voltages of parallel strings must be closely matched, or else, there will be significant power losses). As a result, the electrical constraint of having all module strings connected in parallel operating at approximately the same voltage does not allow full flexibility for a shaded string to activate its bypass diodes without significant installed PV array power loss. Therefore, in essentially all cases, shade or even partial shading on PV modules affecting even one cell within one of the strings may actually cut off the power produced by the entire string. As a representative example, consider one non-shaded PV module string and one PV module string that is shaded as described in the previous example above. A Maximum-Power-Point-Tracking (MPPT) capability will enable the production of full power from the first PV module string and the production of 70% of full power from the second PV module string. In this way, both strings reach the same voltage (the currents from the parallel strings are additive at the same module string voltage for the parallel connected strings of series-connected modules). Therefore, in this example and using a centralized DC-to-AC inverter with centralized MPPT, the power produced by the PV module array would be 85% of the maximum possible power without any module shading. This represents a 15% power loss for the PV system.
Another representative example of a prior art implementation is the monolithic compound semiconductor bypass diode used with a front-contact (emitter contact fingers and busbars on the front-side of the solar cell), compound semiconductor (III-V) on germanium substrate, multi junction solar cell, primarily for Concentrator PV (or CPV) applications.
In general, while the prior art monolithic integration of the bypass diode (Schottky diode or pn junction diode) as shown, on an expensive multi junction front-contact solar cell on an expensive germanium substrate for very high concentration CPV applications, may be acceptable (although far from being a low-cost solution) for that specific application despite the extra processing steps and lack of harmonization between the material stacks and process steps, extra manufacturing cost, and added manufacturing process complexity of the monolithic integration with the solar cell, the prior art approaches demonstrated for the expensive compound semiconductor multi junction solar cells on expensive starting substrates (with expensive MOCVD-grown multi-junction compound semiconductor material stacks) would be prohibitively too complex, expensive, and not acceptable for mainstream flat-panel (non-concentrating or low to medium concentration) low-cost solar PV cells and modules. Also, as noted previously, because the prior art method of monolithic integration of the bypass diode consumes a fairly large area fraction, otherwise used by the expensive solar cell, it reduces the effective area for sunlight absorption and hence the effective cell efficiency due to loss of sunlight absorption area. In prior art demonstration of the monolithic bypass diode with an expensive compound semiconductor multi junction solar cell on an expensive germanium substrate, the electrical metallization and contacts of the solar cell and the bypass diode are on both sides of the devices and the substrate, including both on the sunnyside and on the backside of the substrate, making the overall monolithic interconnections of the solar cell and the bypass diode more complex and costly.
BRIEF SUMMARY OF THE INVENTIONTherefore, a need has arisen for high-efficiency solar cells, including but not limited to high-efficiency crystalline silicon solar cells as well as any crystalline semiconductor (using silicon and/or other semiconductor materials such as gallium arsenide-based) solar cells such as solar cells comprising a backplane and/or high-efficiency back-contact solar cells, with a bypass switch monolithically integrated with each solar cell, that provides distributed shade management, increased energy & power harvesting, and energy yield improvements for installed PV systems, as well as solar cell and PV module protection, based on a substantially harmonized manufacturing process flow and without increasing the solar cell manufacturing process complexity and cost as a result of such monolithic integration of cell-level bypass switches.
Structures and methods for a solar cell having an integrated bypass switch are provided. According to one embodiment, an integrated solar cell and bypass switch comprising a semiconductor layer has a background doping, a frontside, and a backside. A patterned first level metal is positioned over the layer backside and an electrically insulating backplane is positioned over the first level metal. A trench isolation pattern partitions the semiconductor layer into a solar cell region and at least one monolithically integrated bypass switch region. A patterned second level metal is positioned over the electrically insulating backplane and which connects to the first level metal through the backplane and electrically connects the monolithically integrated solar cell and bypass switch structure.
In accordance with one aspect of the disclosed subject matter, a back-contact solar cell with at least one monolithically-integrated on-cell electronic bypass switch (MIBS) is provided which substantially eliminates or reduces disadvantages and energy yield harvesting limitations associated with previously developed solar photovoltaic cells and modules, as well as the limitations and disadvantages of known monolithic and non-monolithic bypass diode implementations.
According to one aspect of the disclosed subject matter, a back-contact solar cell with monolithically integrated on-cell power electronics, more specifically at least one monolithic bypass switch per solar cell, such as a Schottky diode (including but not limited to Super Barrier Schottky Diode) or a pn junction diode or a transistor-based switch, is provided. The back-contact solar cell is comprised of a semiconductor absorber substrate (for instance, a crystalline silicon absorber formed by epitaxial growth or from Czochralski wafers or from cast multi-crystalline wafers) having a light capturing front side and a backside opposite the light capturing front side, as well as a backplane. The backside may also serve as a secondary light-capturing surface in case of a bifacial solar cell. A first interdigitated metallization pattern (first metallization level known as M1) is positioned on the backside of the semiconductor substrate and a thin backplane sheet or material layer (for example made of an electrically insulating rigid or flexible material) is attached (for example laminated) to and supports the backside of the semiconductor substrate. Formation methods for patterned M1 include, but are not limited to, physical-vapor deposition (PVD) and patterning (laser ablation or masked wet or dry etch patterning) of a suitable metallic stack (e.g., comprising Al, NiV) or by direct printing (such as screen printing or stencil printing or inkjet printing) of a suitable metallic paste (such a suitable aluminum or aluminum-silicon alloy paste). A second interdigitated metallization pattern (second solar cell metallization level known as M2) is positioned on the backplane (and electrically isolated and separated from M1 by the backplane except for the pre-specified via holes through which conductive via plugs interconnect the M1 and M2 levels) and is electrically interconnected to the first interdigitated metallization pattern at designated sites through a patterned array of conductive via holes through the backplane (thus creating a patterned two-level metallization structure). At least one monolithically-integrated on-cell electronic component, such as an electronic bypass switch (e.g., Schottky diode or bypass diode or a transistor switch), is monolithically fabricated within the same semiconductor substrate used for fabrication of the solar cell, concurrent with and using essentially the same process steps utilized for the fabrication of the solar cell, and is electrically interconnected as a parallel bypass switch (e.g., including but not limited to a rectifying Schottky diode or pn junction diode) with the desired polarity to the solar cell terminals (e.g., the solar cell base and emitter terminals) using the patterned solar cell metallization structure (M1 and/or M2).
These and other aspects of the disclosed subject matter, as well as additional novel features, will be apparent from the description provided herein. The intent of this summary is not to be a comprehensive description of the claimed subject matter, but rather to provide an overview of some of the subject matter's functionality and embodiments. Other systems, methods, features and advantages here provided will become apparent to one with skill in the art upon examination of the following FIGUREs and detailed description. For instance, while the representative embodiments of this invention are presented and described for use with back-contact/back-junction solar cells using thin monocrystalline silicon absorbers with interdigitated (or interdigitated back-contact: IBC) metallization structures, it should be understood that the monolithically integrated bypass switch embodiments (various structures and processing methods) and concepts of this invention can be applied to other solar cell absorber materials and other solar cell structures made with any suitable semiconductor absorber materials, including but not limited to those (with crystalline silicon or structures comprising other semiconductor materials such as GaAs, GaN, etc.) with front-junction/back-contact (and non-interdigitated patterned interconnects), solar cells (with crystalline silicon or structures comprising other semiconductor materials such as GaAs, GaN, etc.) with both front emitter contact and backside base contact, solar cells made of materials other than monocrystalline silicon, solar cells using thicker semiconductor absorber layers than those described here, metallization wrap-through (MWT) solar cells, PERC and PERL solar cells, silicon heterojunction (SHJ) solar cells, etc. It is intended that all such additional systems, methods, features and advantages that are included within this description, be within the scope of any claims.
The features, natures, and advantages of the disclosed subject matter may become more apparent from the detailed description set forth below when taken in conjunction with the drawings (various dimensions not shown to scale) in which like reference numerals indicate like features and wherein:
The following description is not to be taken in a limiting sense, but is made for the purpose of describing the general principles of the present disclosure. The scope of the present disclosure should be determined with reference to the claims. Exemplary embodiments of the present disclosure are illustrated in the drawings, like numbers being used to refer to like and corresponding parts of the various drawings.
And although the present disclosure is described with reference to specific embodiments, such as back contact solar cells using monocrystalline silicon substrates, monocrystalline silicon such as epitaxial silicon solar cell absorber layers, and other described fabrication materials, one skilled in the art could apply the principles discussed herein to other solar cells based on different substrate types and/or solar cell structures and/or overall solar cell manufacturing methods, including the back-contact solar cells made using czochralski (CZ) monocrystalline silicon or cast multi-crystalline silicon starting wafers (hence, solar cell substrates without epitaxial silicon deposition), other back-contact solar cells (such as MWT back-contact solar cells), front contact solar cells made using either epitaxial silicon absorber or czochralski (CZ) silicon starting wafers or cast multi-crystalline silicon starting wafers, other fabrication materials including various semiconductor materials other than crystalline silicon (such as crystalline gallium arsenide, gallium nitride, germanium, etc.), technical areas, and/or embodiments without undue experimentation. Further, the dopant concentration/profile of the starting semiconductor layer, for example p-type or n-type, is known as background doping.
Accordingly, while the embodiments herein are described for interdigitated back-contact (i.e., IBC) crystalline (either monocrystalline or multi-crystalline) silicon solar cells, it should be understood that the inventive aspects disclosed may be applied to a much wider range of solar cell architectures (e.g., Metallization-Wrap-Through or MWT back-contact solar cells, front contact solar cells, bifacial solar cells, etc.) and materials (e.g., GaAs, Ge, etc. besides crystalline silicon).
As noted above, current state-of-the-art solar cell protection and solar module shade-induced hot spot prevention solutions providing reliable module operation in the presence of shading, in known crystalline silicon (or other cell-based) PV systems are often based on utilizing one or a combination of the following: separate or discrete bypass diodes, most commonly one external discrete bypass diode (usually placed and electrically wired in a photovoltaic module junction box) per one substring of series-connected solar cells (e.g., 20 or 24 cells per substring in 60-cell or 72-cell PV modules, respectively) in a PV module (typically three external bypass diodes are placed in an external module junction box per crystalline silicon PV module to provide shade-induced hot-spot protection for all the solar cells in the module); moreover, maximum power point tracking (MPPT) may be provided at the module level using an external micro-inverter (DC to AC), or alternatively a DC-to-DC converter, connected to the PV module; and/or, using a so-called programmable interconnect technology between the cells packaged within the module, in order to increase the energy yield of the cell-based PV module.
While the prior art bypass diodes are used to protect shaded cells, prevent hot spots, and prevent module failures due to hot spots and shaded (or partially shaded) reverse biased cells, they may also result in significant energy harvest degradation or energy yield reduction (in terms of kWh of energy harvested per KWp installed PV modules over a specified duration of field operation, such as on an annual basis) in realistic field operations due to module power extraction losses when module shading or soiling is present. For instance, assuming a standard 60-cell PV module design, a single shaded cell may result in loss of about ⅓ (or 33.33%) of the module power (the prior art external bypass diode in the junction box would bypass the entire 20-cell sub-string containing the shaded cell in order to prevent reverse biasing of the cell) while the single cell typically accounts for only about 1/60 of the total module power (for a typical 60-cell PV module) during normal non-shaded module operating conditions in the field. Similarly, with three shaded cells and assuming one shaded cell per 20-cell sub-string in a 60-cell PV module (an example of which is shown in
In contrast, the distributed monolithic shade management solutions of this invention disclosed herein provide smart PV cells and smart PV modules with increased PV module power harvesting and increase energy yield using a Monolithically Integrated Bypass Switch (MIBS), which may be manufactured concurrently and monolithically integrated with each solar cell (thus eliminating the need for the external junction box with the external discrete bypass diodes), at essentially no incrementally added manufacturing cost while manufacturing the solar cells. The MIBS structures and implementation methods disclosed herein are also designed to increase the overall solar cell module reliability and extend operating lifetime in addition to other associated benefits.
In addition, the disclosed systems and methods enable smart PV cells and smart PV modules capable of integrating additional distributed cell-level (cellular) power electronics offering dramatic PV system cost and Levelized-Cost of Electricity (LCOE) reduction (supporting <$1/W installed PV system cost) and performance improvement in terms of energy yield (enabling less than about $0.10/kWh and even less than about $0.06/kWh Levelized Cost of Electricity or LCOE, depending on the specifics of PV installation sites and operating conditions). Important applications of the embodiments of this invention include cells and modules for the residential rooftop, Building-Integrated PhotoVoltaics (BIPV) in residential and commercial buildings, commercial rooftop, ground-mount utility-scale power plants, automotive, portable electronics, portable and transportable power generation, and other specialty applications.
As previously noted, crystalline silicon photovoltaics (PV) modules currently account for approximately over 85% of the overall global PV market. The silicon wafer material cost of these crystalline silicon PV modules currently constitutes approximately 30% to 50% of the total crystalline silicon PV module manufacturing cost.
The representative process flow shown in
After completion of a majority of solar cell processing steps (e.g., the backside doped emitter and base regions, the rear passivation structure, the rear base and emitter contacts, and the patterned on-cell busbarless M1 metallization layer with fine-pitch interdigitated fingers made of a suitable metallization material such as aluminum or an aluminum-silicon alloy), a relatively inexpensive backplane layer (such as a 50 to 250 micron thick flexible prepreg layer with relatively close CTE match to that of silicon) may bonded or laminated to the thin epitaxial silicon layer for permanent cell support and reinforcement as well as to enable the two-level cell metallization architecture of the solar cell. The backplane material may be made of a thin (for instance, about 50 to 250 microns), flexible (or if desired rigid), and electrically insulating material sheet such as an inexpensive flexible prepreg material (with relatively close CTE match to that of the semiconductor substrate, such an aramid fiber prepreg sheet) commonly used in applications such as printed circuit boards, which meets the process integration and reliability requirements of solar cells and PV modules. Besides prepreg, other suitable polymeric or plastic materials may be used as the solar cell and MIBS backplane material (flexible or semi-flexible or rigid). The mostly-processed (processed through the patterned M1 layer and laminated with the continuous backplane sheet) back-contact, back-junction backplane-reinforced large-area (for instance, a solar cell area of at least 125 mm×125 mm or larger such as with dimensions of at least 156 mm×156 mm full square or pseudo square formats) solar cell is then separated and lifted off from the reusable template along the mechanically-weakened sacrificial porous silicon layer (for example through a Mechanical Release—MR—process) while the template may be re-used many times (e.g., at least a few times and in some instances at least 10's of times) to further minimize the overall solar cell and PV module manufacturing costs. Final back-end cell processing (comprising completion of the sunnyside texture, passivation, and anti-reflection coating or ARC deposition followed by completion of the via plugs and second level metallization or M2) may then be performed, first on the solar cell sunny-side which is exposed after being released from the template. Sunny-side processing may include, for instance, completing frontside texturization (for instance, using alkaline or acidic wet chemistry) and surface passivation and anti-reflection coating (ARC) deposition (for instance, using a passivation and ARC layer or layer stack comprising SiNxHy or SiOwHz/SiNxHy or Al2O3/SiNxHy formed by PECVD or ALD and PECVD) process. One may use a process using a starting CZ or FZ or multi-crystalline silicon wafer (instead of using porous silicon and epitaxial growth on a reusable substrate) to manufacture the IBC cells described above (the first 3 blocks or steps shown to the left of
The MIBS implementation methods and designs of this application may be integrated into the disclosed solar cell fabrication process flow (as well as many other crystalline silicon solar cell process flows, including but not limited to those using either wire-sawn starting wafers or epitaxially grown solar cell substrates) without substantially altering or adding manufacturing process steps or tools, and thus without substantially adding to the cost of manufacturing the solar cell. In one embodiment, the combination of back-junction/back-contact (or IBC) cell designs in conjunction with a backplane-enabled two-level interconnection and backplane-enabled solar cell support provides an enabling solar cell architecture for Monolithically-Integrated Bypass Switch (MIBS) implementation at the cell level, hence, eliminating the need for the use of discrete components such as discrete diodes in conjunction with the module junction box or in conjunction with each cell. In addition to serving as a permanent structural support/reinforcement and providing backplane-enabled low-cost/high-conductivity (e.g., using aluminum and/or copper and/or their alloys or other suitable high-conductivity metallization materials) interconnects for the high-efficiency crystalline semiconductor solar cell (such as crystalline silicon solar cell), these backplane technologies also enable effective MIBS integration with each solar cell without significantly compromising solar cell power (since the MIBS area is a very small fraction of the solar cell area) and with negligible or no addition to the overall solar cell manufacturing cost. The embodiments of this invention enable very economic and reliable integrated shade management solution using MIBS, by eliminating the reliability concerns and component costs of prior art discrete bypass diodes (also eliminating the need for discrete component soldering or attachment to the solar cell or module junction box. They also provide excellent reliability similar to that of the solar cell itself (due to the monolithic integration of MIBS and solar cell and the fact that they use harmonized manufacturing process and materials).
The backplane material may be a thin (e.g., about 50 microns to 250 microns thick; may be thinner or thicker than this range too) sheet of a suitable material, for instance a flexible material such as a prepreg sheet or a polymeric or a plastic material, with sufficiently close coefficient of thermal expansion (CTE) match the CTE of the semiconductor substrate in order to avoid causing excessive thermally induced CTE-mismatch stresses on the thin semiconductor (e.g., crystalline silicon) layer. Moreover, the backplane material should meet process integration requirements for the backend cell fabrication processes, including in particular chemical resistance during wet etch/texturing of the solar cell frontside and sufficient thermal stability during the subsequent PECVD deposition of the frontside (single-layer or multi-layer) passivation and ARC layer(s). The electrically insulating backplane material sheet attached to the thin semiconductor substrate should also meet the subsequent module-level lamination process thermal budget and long-term field operation reliability requirements. While various suitable polymeric (such as plastics, fluoropolymers, prepregs, etc.) and suitable non-polymeric materials (such as glass, ceramics, etc.) may be used as the backplane material (either flexible or rigid backplane), backplane material choice depends on many considerations including, but not limited to: cost, ease of solar cell process integration, long term reliability, thermal stability, flexibility, pliability, etc.
A good material choice for backplane is prepreg comprising a suitable combination of fibers and resins. Prepreg sheets are used in many applications such as building blocks of printed circuit boards (PCB) and may be made from combinations of suitable resins and Coefficient of Thermal Expansion or CTE-reducing fibers (such as aramid fibers) or particles. The backplane material sheet may be an inexpensive, low-CTE (typically with CTE <10 ppm/° C., or in some instances with CTE <5 ppm/° C., since the semiconductor materials such as crystalline silicon have relatively low CTE values on the order of 3 ppm/° C.), thin (usually in the range of about 50 microns to 250 microns, and in some instances in the smaller range of about 50 microns to 100 microns for reduced backplane sheet cost and enhanced flexibility of the backplane-laminated solar cell) prepreg sheet which is relatively chemically resistant to wet etch/texturization chemicals (such as alkaline or acidic texturization chemistries) and is relatively thermally stable at temperatures up to at least about 180° C. (or even up to as high as about 400° C.-450° C.). In the case of crystalline silicon solar cells made using epitaxial silicon deposition on porous silicon on template, the prepreg sheet may be attached to the solar cell substrate backside after completion of the solar cell manufacturing process through the patterned M1 metallization layer (first-level metal on the solar cell backside) while the cell semiconductor substrate is still on the template (i.e., before the solar cell substrate lift off process) using a vacuum-thermal laminator. Alternatively, in the case of crystalline silicon solar cells made using starting CZ monocrystalline or FZ monocrystalline or cast multicrystalline wafers (and not using epitaxial silicon deposition on porous silicon on template), the prepreg sheet may be attached to the solar cell wafer backside after completion of the solar cell manufacturing process through the patterned M1 metallization layer (first-level metal on the solar cell backside) and before completion of the back-end process steps (such as the sunnyside texture, passivation, and ARC as well as the conductive vi plugs through the backplane and the second-level metallization level or M2 formed on the backplane). Upon applying a combination of heat (for instance, to temperatures of up to about 200° C. to 300° C.) and pressure (for instance, pressures of up to several to about 20 atmospheres), the thin prepreg sheet is permanently laminated or attached to the backside of the partially-processed back-contact solar cell. In the case of crystalline silicon solar cells made using epitaxial silicon deposition on porous silicon on template, the lift-off release peripheral boundary is defined around the periphery of the solar cell (near the template edges based on some pre-specified exclusion zone), for example by using a pulsed laser scribing tool, and the backplane-laminated solar cell substrate is then separated and lifted off from the reusable template using a mechanical release or lift-off process. The released backplane-attached solar cell may then be optionally laser trimmed around the edges to prepare the final straight solar cell peripheral edges according to the final specified solar cell dimensions. Alternatively, in the case of crystalline silicon solar cells made using starting CZ monocrystalline or FZ monocrystalline or cast multicrystalline wafers (and not using epitaxial silicon deposition on porous silicon on template), there is no release process and an optional post-lamination laser trimming process may be used to remove any excess prepreg extending from the active edges of the solar cell (and MIBS). The subsequent process steps (either with epitaxial cells or with CZ/FZ/Multi-crystalline silicon wafer-based cells) may include: (i) completion of the frontside texture and passivation/ARC processes on the solar cell sunnyside, (ii) completion of the solar cell high conductivity metallization (the second-level metallization or M2 may be formed in conjunction with the associated M1-M2 conductive plugs, with metallization materials comprising aluminum and/or copper and/or their alloys or other suitable metallic materials) on the cell backside (which is the solar cell backplane). The high-conductivity metallization (for example comprising rather inexpensive aluminum and/or copper, as opposed to silver to reduce the overall solar cell material and manufacturing costs) including the interconnections to both the solar cell emitter and base polarities (fingers and busbars) are formed on the laminated solar cell backplane using the patterned M2 layer.
In the back-contact solar cell and MIBS embodiments of this invention, solar cell designs and manufacturing processes described herein have two levels of metallization (on-cell M1 or first metallization level and on-backplane M2 or second metallization level) which are separated by the electrically insulating backplane layer, and interconnected according to a pre-specified pattern of via holes through conductive via plugs interconnecting the patterned M2 and M1 metallization regions based on a pre-specified interconnection arrangement. For the IBC cells using the embodiments of this invention, the M1 pattern may be a relatively fine-pitch pattern of interdigitated base and emitter metallization fingers (without any busbars on M1 to eliminate the electrical shading degradation effects on solar cell efficiency), while the M2 pattern may be a relatively coarse pitch pattern of interdigitated base and emitter metallization fingers, with the M2 fingers being substantially orthogonal or perpendicular to the M1 fingers, and the M2 finger count being substantially less than the M1 finger count (for instance, by a factor of about 5 to 50). Prior to the backplane lamination process, the solar cell base and emitter contact metallization pattern is formed directly on the cell backside (the M1 metallization level), for example by using a relatively thin (with a thickness of about a fraction of one micron up to about 20 microns; typically thinner layers formed by PVD and thicker layers formed by screen printing) layer of screen printed or plasma sputtered (PVD) aluminum (or aluminum silicon alloy) material layer. This first layer of metallization formed on the solar cell rear side or backside prior to the backplane attachment or lamination process (herein referred to as M1) defines the solar cell contact metallization pattern, such as fine-pitch (e.g., base and emitter metallization finger pitch on the order of about 0.5 millimeter up to few millimeters) interdigitated back-contact (IBC) M1 conductor fingers defining the base and emitter regions of the IBC cell. In some instances, the patterned M1 layer does not have any solar cell busbars in order to eliminate any detrimental electrical shading losses associated with the solar cell metallization busbars. The M1 layer (also known as the solar cell contact metallization) extracts the solar cell current and voltage (or the solar cell electrical power) and transfers the solar cell electrical power to the second level/layer of relatively higher-conductivity solar cell metallization (herein referred to as M2) formed after M1 on the backplane surface (and physically separated from the patterned M1 layer by the laminated or attached backplane sheet). After attachment or lamination of the backplane sheet to the solar cell backside following formation of the patterned M1 layer, and in the case of epitaxial silicon solar cell after subsequent detachment of the backplane-supported solar cell from the template (not applicable if the solar cell is fabricated on CZ or FZ monocrystalline silicon wafer or on cast multi-crystalline silicon wafer), and following completion of the frontside texture and passivation and ARC formation fabrication processes, the via holes are formed through the backplane sheet (holes landing on designated pads on patterned M1 layer) and the relatively higher sheet-conductance layer M2 is formed on the backplane (for instance, using a relatively inexpensive high-conductivity metal or metal alloy comprising aluminum and/or copper). Via holes (in some instances up to hundreds or thousands of via holes within the area of the continuous backplane) are drilled into the backplane (for example by a pulsed laser drilling process). These via holes land on pre-specified regions of patterned M1 fingers (solar cell base and emitter metal fingers) for subsequent electrical interconnections between the patterned M2 and M1 layers through electrically conductive plugs formed in these via holes. Subsequently, the patterned higher-conductivity metallization layer M2 is formed (for example by plasma sputtering, electrochemical deposition or plating, attachment of a metallic foil to the backplane, or a combination thereof—using an M2 material, for example a relatively inexpensive and high-conductivity electrical conductor comprising aluminum and/or copper). For an interdigitated back-contact (IBC) solar cell with fine-pitch IBC fingers on M1 (for instance, hundreds of M1 metal fingers per IBC solar cell), the patterned M2 layer may be designed and fabricated with its conductor fingers to be substantially orthogonal or perpendicular to M1—i.e., the M2 base and emitter fingers are made essentially perpendicular to the M1 base and emitter fingers. The M2 fingers alternate between base and emitter polarities and connect to the respective base and emitter busbars formed as part of the M2 layer. Because of this orthogonal transformation for M2 with respect to M1, the M2 layer may have far fewer IBC fingers than the M1 layer (for instance, by a factor of about 5 to 50 fewer M2 fingers compared to M1 fingers). Hence, the M2 layer may have a much coarser pattern with much wider M2 IBC fingers than the M1 layer. For instance, the average width of M2 fingers may be several millimeters to over 1 centimeter whereas the average width of M1 fingers may be 100's of microns up to over 1 millimeter. Solar cell busbars may be positioned on the M2 layer, and not on the M1 layer, in order to eliminate the electrical shading losses associated with busbars on a solar cell. And as both the base and emitter interconnections and busbars may be positioned on the M2 layer on the solar cell backside backplane, electrical access is provided to both the base and emitter terminals of the solar cell on the backplane. The patterned M2 layer also forms the conductive via plugs (for instance, using the same deposited metal layer used for the patterned M2 layer fingers and busbars).
Intelligent Cellular Shade Impact Suppression (ISIS) or Integrated Shade Management Using MIBS.
Often due to the series wiring and interconnections of the solar cells within a PV module, a small amount of obstruction on a PV module light-absorbing face may lead to large output loss. The same is true when considering an installed PV system comprising an array of PV modules connected in electrical series and parallel arrangement. Examples of power harvesting capability loss as a result of cell and module shading (partial or full shading) include the following. For instance, one published study determining that obstruction on 0.15%, 2.6%, and 11.1% of the PV module surface area may cause 3.7%, 16.7%, and 36.5% of output power loss, respectively, hence resulting in a significant reduction of the installed PV system energy yield in case of even partial shading. As described earlier, when the electrical current of one obstructed cell drops due to partial or full shading of the cell, the shaded cell may drag down the current of all the other cells wired in series in a string or sub-string, or alternatively the shaded solar cell may be reverse biased by the larger electrical current generated by the unshaded cells resulting in a hot spot and reliability problem at the shaded cell area, unless corrective action is taken in the design and build of the PV module.
MIBS-based ISIS or shade management designs disclosed herein monolithically integrate a bypass switch (a pn junction diode or a Schottky diode—or alternatively another semiconductor switch such as a suitable transistor switch) to provide for the automatic re-routing (or bypassing) of electricity around any obstructed or shaded cells with minimal impact on the series string and the PV module—thereby maximizing the power generation capability of the PV module and the overall energy yield output of the PV modules—without substantially changing the solar cell fabrication process flow (hence, a so-called harmonized process flow) and with negligible or no incremental addition to the overall solar cell manufacturing cost. The MIBS-based ISIS or shade management structures and methods described in this invention improve the overall cell and module reliability by substantially mitigating any thermally induced stresses from heat dissipation associated with mismatched electrical current within the PV modules; they also eliminate the need for a module junction box with external bypass diodes and eliminate the need for any discrete bypass switch components, thus reducing the cost per watt of the resulting smart PV module; and, they also eliminate thermal and mechanical stresses associated with mounting and soldering discrete bypass diode components on the solar cells.
Intelligent Cellular Shade Impact Suppression (ISIS) or Shade Management Solutions Using Monolithically-Integrated Bypass Switches (MIBS) with Solar Cells:
The following section describes various shade management MIBS implementation embodiments of this invention. As a representative example, considerations and criteria relating to selection of a MIBS ON resistance for use in the distributed cellular shade management (ISIS) systems disclosed, without substantial power dissipation losses in the distributed switches, include but are not limited to:
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- A cellular bypass switch with a small on-state voltage drop, in some instances far smaller than that of a forward-biased diode. For example, assuming Vmp=575 mV (maximum-power-point voltage) and Imp=9.00 A (maximum-power-point current) (corresponding to open-circuit voltage of approximately Voc=660 mV and short-circuit current of about ISC=9.75 A), an on-state voltage of 50 mV would result in an on-state power dissipation of 0.45 W which is less than about 10% of that of a diode (this calculation excludes any loss associated with the switch series resistance Rseries).
- A cellular bypass switch with a very small on-state series resistance to minimize the on-state switch power dissipation, such as an on-state switch Rseries less than or equal to 10 mΩ (for example Rseries=5 mΩ, ohmic power dissipation of switch=0.405 W).
- MIBS may use low-forward-bias voltage Schottky diode with an on-state or forward-bias voltage of ˜0.2 V to ˜0.5V, or alternatively a pn junction diode with an on-state forward bias voltage of ˜0.6 V to ˜0.7 V. The use of an optimal Schottky diode can result in lower power dissipation compared to a pn junction diode, when the MIBS switch is activated due to cell shading.
MIBS structures with the following functionality may be used:
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- Low power dissipation when the MIBS is turned ON (the MIBS diode is forward biased) due to cell shading. For example, the MIBS power dissipation due to its ohmic losses may be limited to about no larger than the average cell power production, and in some instances to a fraction of the average solar cell power production. For instance, for a 5 Wp (watt peak) solar cell, the MIBS device design (such as a Schottky diode or a pn junction diode) may limit the power dissipation in the shaded cell in a series-connected string of solar cells to no more than about 2 W up to about 5 W when the full cell string current passes through the shaded cell MIBS device (lower power dissipation with Schottky diode MIBS compared to pn junction MIBS due to the lower forward-bias voltage of the Schottky diode compared to the pn junction diode). The MIBS diode is designed to provide a very low on-resistance in order to minimize the MIBS power dissipation when the MIBS device is activated.
- Relatively low reverse leakage current in the MIBS device when the solar cell MIBS is OFF (reverse biased) or when the cell is not shaded and is operating under normal un-shaded conditions. For instance, the MIBS device may be designed such that its reverse leakage current is substantially below 1% or even below 0.1% of the solar cell photo-generated current.
Monolithically-Integrated Bypass Switch (MIBS) for Distributed Shade Management in PV Modules.
Various examples of smart solar cells with monolithically integrated shade management solutions eliminating the need for the external bypass switches and discrete bypass switch components are described herein. The MIBS structures and methods provide, for example and among other benefits, the following advantages:
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- A monolithically integrated bypass switch (MIBS) may be implemented on each cell at essentially zero incremental manufacturing cost to the cell manufacturing cost (i.e., negligible or no increase in manufacturing cost per cell as a result of the MIBS implementation with each solar cell).
- MIBS enabled solar cells provide distributed shade management directly at the cell level for enhanced energy yield and enhanced energy harvesting in PV modules as compared to traditional PV modules comprising external discrete bypass diodes in PV module junction boxes.
- In numerous fabrication embodiments, including those described herein, fabricating MIBS-enabled solar cells may add essentially no additional cell/module manufacturing cost and may incur negligible cell efficiency/power penalty while providing substantially enhanced energy harvest and higher energy yield for PV modules operating in realistic field conditions with environmental shading and/or soiling of modules (for instance, on residential rooftop PV installations).
- Monolithic integration solutions and processes of this invention utilizing MIBS are provided for relatively thin (e.g., semiconductor absorber or substrate thickness in the range of a few microns up to over 100 microns in thickness) semiconductor (e.g., thin epitaxial silicon substrate or thin crystalline silicon wafer) solar cells with attached or laminated backplane support with essentially no change to the solar cell process flow (hence, harmonized manufacturing process flow), essentially no added solar cell processing complexity, and essentially no added solar cell processing cost. Moreover, the MIBS embodiments described herein may use the same material stack layers (semiconductor, dielectric, and metal layers) as the solar cell itself—thus the fabrication processing of the solar cell and the MIBS device associated with the solar cell may be performed concurrently and in a harmonized manner using the same process tools utilized for the solar cell fabrication.
- Exemplary monolithic integration solutions for MIBS cells using either pn junction diodes or metal-electrode Schottky diodes that eliminate the need for discrete bypass switch components and their attachment to the solar cells are provided.
- Low cost and reliable integrated shade management solutions which eliminate reliability concerns and component costs of discrete diode components (and also eliminate the need for discrete switch component soldering or attachment by conductive adhesive to the solar cell) are provided.
- Because the MIBS methods and structures disclosed utilize the same materials as the solar cell, they have excellent long-term reliability identical to that of the solar cell itself. The MIBS and its associated solar cell are interconnected as required using the solar cell metallization structures, for instance, the M1 layer and/or the M2 layer.
- MIBS methods and structures disclosed may also provide mitigation of thin semiconductor micro-cracks (micro-crack generation and/or propagation) since there is no discrete soldered bypass diode component attached to the solar cell and a peripheral MIBS device may serve as a micro-crack prevention shield or guard for the solar cell.
For example, key attributes and benefits of MIBS solar cells, include, but are not limited to:
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- MIBS embodiments disclosed herein may be applied to various cell-based PV modules in general, and specifically to crystalline semiconductor solar cells including thin (e.g., from about 1 μm up to about 100 μm thick or even thicker semiconductor absorber) crystalline semiconductor (e.g., silicon and gallium arsenide) solar cells.
- MIBS embodiments disclosed herein provide structures and manufacturing methods for producing relatively thin-crystalline semiconductor, such as thin crystalline silicon, solar cells with at least one relatively low-power-dissipation monolithically-integrated bypass switch (MIBS) on each solar cell which provide reliable cell-level shade management in a PV module made of a plurality of MIBS-enabled solar cells.
- Structures and methods disclosed herein are described for high-efficiency back-contact/back-junction (also called IBC) solar cells fabricated using thin (e.g., from about 1 micron up to about 100 microns or even thicker) epitaxial silicon lift-off processing or alternatively fabricated using starting crystalline silicon wafers (CZ or FZ or multi-crystalline silicon wafers) and comprising a laminated or attached backplane support. However, the structures and methods of the disclosed subject matter are also applicable to solar cells made of semiconductor absorber materials other than crystalline silicon (e.g., gallium arsenide, germanium, gallium nitride, etc.) as well as other solar cell designs (e.g., front-contact cells or other back-contact non-IBC cells).
- MIBS solar cell embodiments disclosed herein may be facilitated and enabled by the combination of thin (with the semiconductor cell absorber thickness less than about 200 microns and in some instances less than about 100 microns) semiconductor absorber and a permanently laminated or attached continuous backplane support layer on the backside of the solar cell.
- MIBS solar cells may have a monolithically-integrated bypass switch (either a pn junction diode or a Schottky diode), for example on a peripheral rim of the solar cell, formed during the solar cell manufacturing process flow without adding any appreciable incremental cost to the cell manufacturing process and without compromising the cell power output because the MIBS device area consumption is only a relatively small fraction of the active solar cell area (for example, the MIBS area can be chosen to be less than about 1% of the solar cell area and even less than a fraction of one percent, for instance, about 0.1% up to 1%).
- For a polygonal shaped solar cell, a peripheral rim (edge located) bypass switch diode may be formed on any one of the polygon sides or on a plurality of the polygon sides or continually along all the polygon sides. For a relatively common square-shaped solar cell format (for instance, with typical dimensions of 156 mm×156 mm, 210 mm×210 mm, or any other desirable solar cell dimensions, for example, a solar cell with cell area in the range of less than about 100 cm2 to over 1,000 cm2) a peripheral rim diode (pn junction diode or Schottky diode) may be formed on at least a portion of the solar cell periphery (on at least one side or a corner or at least a portion of one side or a portion of one corner, or a combination thereof), or as a continuous closed-loop (or continuous segmented closed loop) full-periphery rim surrounding the entire solar cell around its periphery forming a larger solar cell island area enclosed by the much smaller area island rim, both supported on the continuous backplane (as shown in
FIG. 14 ). - The MIBS bypass diode and the solar cell share the same common continuous backplane and their semiconductor layers (e.g., epitaxial silicon or semiconductor substrate made of CZ or FZ or multi-crystalline wafer) are fully isolated from each other using a trench isolation process performed during the cell manufacturing process, for example by using a through-semiconductor pulsed laser scribe to form the device isolation trenches. The isolation trench may penetrate the entire thickness of the semiconductor layer (e.g., thin epitaxial Si) and stop on the electrically insulating backplane. The width of the trench isolation depends on the properties of the laser beam (for example a pulsed nanoseconds laser beam) used for isolation scribe and the semiconductor layer thickness and may be, for example, in the range of about 1 micron up to about 100 microns or even more (narrower trenches may be formed in order to reduce the area-related losses). Generally, a narrower trench isolation width may be advantageous. In practice, the trench isolation width may be on the order of 10's of microns. Alternatively, the trench isolation regions may be formed by using a technique other than pulsed laser scribing, for instance, by mechanical dicing or ultrasonic scribing or another method. A suitable trench isolation formation process such as a pulsed laser scribing or cutting process selectively cuts through the semiconductor layer and effectively stops on the backplane sheet after cutting through the thickness of the semiconductor substrate without a substantial removal of the backplane material (hence, maintaining the integrity of the continuous backplane sheet).
Further, monolithically integrated bypass switch (MIBS) fabricated concurrently with the solar cell using a shared manufacturing process flow may offer the following advantages, among others:
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- Integrated bypass switches may be fabricated at negligible or essentially zero incremental manufacturing cost added to the solar cell or PV module.
- Eliminate the need for attachment of discrete bypass switches to the solar cells or solar cell backplanes.
- Resolve the potential reliability concerns of attaching (e.g., soldering) discrete components, such as discrete diodes, to the solar cells and permanently laminating such cells with attached discrete components in solar modules.
- Maintain overall planarity for the solar cells with monolithically integrated bypass switches as there are no discrete component bumps, as well as eliminate the need to use thicker module encapsulant (such as EVA or polyolefin) to accommodate discrete component topography and bumps.
- Eliminate the cost of the discrete bypass switches (e.g., diodes or transistors) and/or the external junction box with external bypass diodes.
- Eliminate the cost of discrete bypass switch component assembly process (e.g., component soldering) on the solar cells.
MIBS solar cells may have substantial identical reliability as compared to the solar cell itself because the MIBS structures may be made from the same solar cell materials and processes (semiconductor substrate, dielectric, metallization, and backplane materials) and are monolithically integrated with the solar cell. This minimizes bankability issues and concerns as the overall reliability of the solar cell and PV module is not compromised (due to the use of robust monolithic bypass diode instead of discrete component soldered to the cell).
The monolithically-integrated bypass switch (MIBS) may be a pn junction diode, such as a rim pn junction diode around the solar cell island. Alternatively, the MIBS be a metal-contact Schottky diode (which usually can provide a smaller forward-bias voltage than a pn junction diode), such as a rim Schottky diode around the solar cell island, made of, for example, an aluminum or aluminum-silicon alloy Schottky contact on n-type silicon.
If a rim diode design is utilized, the monolithically integrated bypass switch (MIBS) rim may also provide the additional benefit of mitigating or eliminating the generation and/or propagation of micro-cracks in the solar cell during and/or after fabrication of the solar cells. This is due to the fact the MIBS rim separated from the solar cell island by the trench isolation region can also serve as a shield or guard against edge-induced and edge-propagating microcracks.
The solar cell embodiments described herein enable smart solar cells and smart solar modules, such as back-contact solar cells including back-contact/back-junction IBC cells, with permanently attached (e.g., laminated) backplanes and integrated MIBS devices with the cells.
The full-periphery through-silicon trench separating and isolating the rim bypass diode from the solar cell may have, for example, an isolation width in the approximate range of a few microns up to about 100 microns (maybe even larger width than about 100 microns, though less desirable to use larger width) depending on the laser beam diameter and semiconductor layer thickness. A typical trench isolation width formed by pulsed nanoseconds (ns) laser scribing may be around 20 up to about 100 microns although the trench isolation width may be smaller. While pulsed laser ablation or scribing is an effective and proven method to form the trench isolation regions, it should be noted that other non-mechanical and mechanical scribing techniques may also be used instead of pulsed laser scribing to form the trench isolation regions for all MIBS solar cell embodiments. Alternative non-laser methods include plasma scribing, ultrasonic or acoustic drilling/scribing, water jet drilling/scribing, or other suitable mechanical dicing or scribing methods capable of selective cutting or scribing of the semiconductor substrate (absorber) layer with sufficient special resolution (i.e., relatively narrow trench isolation width).
The term monolithic integrated circuit is used to describe a plurality of semiconductor devices and corresponding electrical interconnections that are fabricated onto a slice of semiconductor material layer, also known as the semiconductor substrate. Hence, a monolithic integrated circuit is typically manufactured on a thin continuous slice or layer of a semiconductor material such as crystalline silicon. The integrated solar cell and bypass switch structures described herein are monolithic semiconductor integrated circuits as the integrated solar cell and bypass switch (MIBS) device are both formed/manufactured on a slice of semiconductor substrate layer (from either a starting semiconductor wafer or a grown semiconductor layer formed by epitaxial deposition). Further, the combination of a continuous backplane attached to the semiconductor substrate layer backside enables the monolithic integrated solar cell and bypass switch (or monolithically-integrated bypass switch—MIBS) embodiments in accordance with the disclosed subject matter.
As a representative example,
Further, the mini-cells comprising a master cell or iCell™ (a master cell refers to an array of mini-cells sharing a common continuous backplane sheet and all originating from the same original solar cell semiconductor substrate (from a starting wire-sawn wafer or grown by a deposition method such as epitaxial growth) subsequently partitioned into the mini-cell regions through the trench isolation regions) may optionally have substantially equal areas although this is not required. The mini-cells in the mini-cell array may be electrically isolated from each other using trench isolation formed by a suitable cutting or scribing technique such as laser scribing or plasma scribing (or water jet scribing or ultrasonic scribing or etc.). Moreover, each mini-cell semiconductor substrate is electrically isolated from its corresponding adjacent full-periphery closed-loop MIBS diode semiconductor substrate using trench isolation gap while the substrates share the same continuous electrically insulating backplane. All the trench isolation regions on the solar cell may be formed during the same manufacturing process step, for example a single process step such as a pulsed laser-scribe process step during the cell fabrication process flow.
The MIBS diode may be a pn junction diode used as the MIBS device or shade management switch. A pn junction MIBS diode fabrication process to produce a MIBS-enabled solar cell of may have the following, among others, attributes and benefits:
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- In some solar cell processing designs such as the IBC solar cells with backplane-enabled two-level metallization architecture as described in this invention, there may be essentially no change to or added process steps/tools in the main solar cell fabrication process flow to implement MIBS (for example assuming back-junction/back-contact crystalline silicon solar cell fabrication using either epitaxial silicon and porous silicon/lift-off processing in conjunction with a reusable crystalline silicon template or silicon substrate from a starting CZ/FZ monocrystalline silicon wafer or silicon substrate from a starting cast multicrystalline silicon wafer, and using an electrically insulating continuous backplane shared between the solar cell and MIBS devices). Thus, there is essentially no added manufacturing cost to implement MIBS along with the solar cell.
- In a back-contact/back-junction (or IBC) solar cell design utilizing a crystalline semiconductor absorber layer such as a semiconductor substrate layer formed by an epitaxial lift-off cell process or from a starting crystalline (CZ monocrystalline or FZ monocrystalline or cast multi-crystalline wafer), following the completion of the cell processing involving most of the back-contact, back-junction cell process steps (backside doped base and emitter regions, backside passivation, base and emitter contact openings, and patterned M1 metallization layer), the following processes may be performed (provided as an example of various possible process flows—many variations and embodiments of IBC process flows are possible and not all are included and described specifically in this invention): (i) backplane sheet attachment or lamination to the solar cell backside; (ii) in the case of using an epitaxially grown silicon layer on porous silicon on reusable template: pre-release trench isolation scribe (for example using a pulsed nanoseconds laser scribe tool or alternatively using another scribing tool such as plasma scribe or mechanical dicing scribe) of the semiconductor substrate (i.e., the thin epitaxial silicon substrate) to define the epitaxial silicon lift-off release boundary (Note: This step is not required when the solar cell and MIBS are fabricated on CZ monocrystalline wafer or FZ monocrystalline wafer or cast multi-crystalline wafer, without using epitaxial growth of silicon on a reusable template); (iii) in the case of using an epitaxially grown silicon layer on porous silicon on reusable template: mechanical lift-off release of the backplane-supported cell and its detachment from the reusable crystalline silicon template (Note: This step is not required when the solar cell and MIBS are fabricated on CZ monocrystalline wafer or FZ monocrystalline wafer or cast multi-crystalline wafer, without using epitaxial growth of silicon on a reusable template); (iv) optional laser trim (for example using a pulsed nanoseconds or microseconds or picoseconds laser source) of the backplane-laminated cell for precision trim and to establish the final desired precise dimensions for the solar cell in conjunction with its associated MIBS; (v) pulsed nanoseconds laser scribing (or plasma scribing or mechanical dicing scribing or water jet scribing or another suitable scribing technique) on the sunny-side of the solar cell to form the trench isolation region(s) and to define the inner solar cell semiconductor island(s) and the peripheral rim diode(s) semiconductor regions, this step providing and defining the MIBS region with its semiconductor region electrically isolated from the solar cell semiconductor region through the trench isolation (trench gap) regions; (vi) and, subsequent cell sunny-side optional wet etch as needed (e.g., to thin the silicon substrate if desired), texture and post-texture surface clean, followed by additional cell process steps such as PECVD sunny-side passivation and anti-reflection coating layer(s) deposition, and final completion of rear side cell metallization including via holes through the backplane to provide access to pre-specified regions of patterned M1 layer, and formation of patterned second level metallization (or patterned M2) and conductive via plugs (for instance, by penetration of M2 metal through the drilled via holes to interconnect patterned M2 and patterned M1 layers according to a pre-specified pattern of conductive via plugs). In the representative process flow described above and in the case of using an epitaxially grown silicon layer on porous silicon on reusable template for the solar cell and its associated MIBS, the trench isolation scribing process and tool may optionally be the same as the process and tool used for pre-release trench scribe and/or the post-release precision trim of the backplane-laminated solar cell and MIBS substrate.
- The laser scribed (or any suitable scribe or cut process capable of forming relatively narrow trenches through the entire thickness of the semiconductor substrate layer, terminating and landing on the backplane sheet with negligible removal or trenching of the backplane sheet material and without compromising the integrity of the continuous backplane sheet) trench isolation process may be performed (for example using a pulsed nanoseconds laser source) to create complete through-semiconductor (e.g., through-silicon in the case of silicon-based solar cell and MIBS) trench regions within thin semiconductor substrate layer through the entire thickness of the semiconductor layer (e.g., epitaxial silicon or silicon substrate from a starting crystalline silicon wafer) and substantially stopping at the backplane with minimal or negligible removal of the backplane material—thus forming the electrically isolated semiconductor rim region (e.g., n-type crystalline silicon when forming n-type IBC cells) for the MIBS diode and the semiconductor island region for solar cell, assuming an n-type base (hence, n-type semiconductor cell and MIBS substrate layer) and p+ emitter solar cell (which is common doping type for a back-contact/back-junction or IBC solar cell). If desired, the semiconductor substrate may be a p-type silicon layer (hence, p-type base for the solar cell) and the doped field emitter region on the cell backside may be an n+ doped (e.g., phosphorus or arsenic doped) junction region.
The pn junction MIBS diode pattern may be one of many possible pattern designs. For instance, in one MIBS diode pattern, the peripheral rim diode p+ emitter region (formed concurrently with the IBC solar cell doped emitter region) may be a continuous closed-loop band sandwiched between (or surrounded by) the n-type base regions (n-type semiconductor is also used within the solar cell island as the base of the solar cell), this pattern is shown in
The full-periphery p+ doped region 34 (enveloped and surrounded by the n-type substrate region) may occupy a portion to most (for instance, from about 5% to about 95%, and more particularly about 20% to about 80%) of the trench-isolated rim semiconductor substrate surface area and may be separated from the edges of the trench-isolated rim diode and the sidewall edge of the MIBS by the inner n-type region 38 and outer n-type region 32 (the inner and outer n-type regions are essentially the n-type substrate region) to keep the p+n junction edge and depletion region edge away from the MIBS rim pn junction diode edges or sidewalls (in order to prevent degradation or increase of the reverse leakage current and prevent degradation or decrease of the breakdown voltage of the pn junction diode). The p+ doped region (formed concurrently with the solar cell emitter) forms the MIBS pn junction rim diode for integrated cell-level shade management and reverse bias protection of the solar cell in case of partial or full shading. The MIBS p+n junction diode and its related depletion region edges may be kept away (recessed) from the passivated edges of the rim diode (the inner boundary at isolation trench 36 and outer boundary forming the sidewall edge of the rim diode) in order to ensure good bypass diode performance and related low reverse leakage current and high reverse breakdown voltage. The edges of the trench-isolated MIBS rim pn junction diode may also be passivated at the same time and using the same passivation and ARC process that is used to form the solar cell sunny-side passivation and ARC layer(s) is, for example by a Plasma-Enhanced Chemical-Vapor Deposition or PECVD process to deposit hydrogenated silicon nitride or a combination of hydrogenated silicon nitride and an underlying passivation layer comprising amorphous silicon or amorphous silicon oxide or amorphous silicon oxynitride or amorphous silicon oxycarbide or silicon dioxide or aluminum oxide or a combination thereof. As an example, assuming a total rim (comprising inner n-type region 38, outer n-type region 32, and p+ doped region 34) semiconductor (e.g., crystalline silicon) width of, for example, about 400 microns, the doped p+ region may have a width of about 300 microns and is separated from each sidewall edge by about 50 microns (in other words inner n-type region 38 outer n-type region 32 each having a width of about 50 microns). Alternatively and as another example, assuming a total rim (comprising inner n-type region 38, outer n-type region 32, and p+ doped region 34) semiconductor (e.g., crystalline silicon) width of, for example, about 600 microns, the doped p+ region may have a width of about 200 microns and is separated from each sidewall edge by about 200 microns (in other words inner n-type region 38 outer n-type region 32 each having a width of about 200 microns). Other absolute and relative dimensions both smaller and larger are possible in accordance with the disclosed subject matter. And while the MIBS diode embodiment of
Alternatively, and described in reference to structure shown
The full-periphery aluminum/n-type silicon Schottky barrier contact region of the MIBS device may occupy from a small fraction (as low as a few percentage points) up to most (for instance, as large as about 95%) of the trench-isolated peripheral rim surface area and in some instances may be spaced and separated from the edges of the trench-isolated rim diode and the sidewall edges of the structure by the inner and outer n-type regions (passivated and n+ contacted n-type regions surrounding the Schottky barrier contact region) to keep the Schottky barrier (e.g., aluminum/n-type silicon) Schottky contact edge and semiconductor depletion region edge away from the passivated MIBS rim diode edges or sidewalls (in order to prevent degradation of the Schottky barrier diode characteristics such as the reverse bias current and reverse breakdown voltage as well as the forward-bias characteristics). The aluminum/n-type silicon Schottky contact region forms the MIBS Schottky rim diode for cell-level shade management and reverse bias protection. The Schottky barrier metal (e.g., aluminum or aluminum silicon alloy) contact to lightly doped n-type region as well as the ohmic metal (e.g., aluminum or aluminum silicon alloy) contact to the surrounding n-type regions through the heavily doped n+ contact regions can be formed on the MIBS device using the same metal layer as patterned M1 and at the same time and using the same process used to form the patterned M1 layer for the solar cell. The MIBS device Schottky barrier contact such as the aluminum/n-type silicon or aluminum-silicon alloy/n-type silicon Schottky barrier contact may be kept away from the passivated edges of the rim diode by the inner and outer n-type silicon region (the surrounding n-type region not covered by the Schottky barrier metal) boundaries in order to ensure a good bypass diode performance characteristics, including both the forward-bias and reverse bias characteristics. The edges of the trench-isolated MIBS rim Schottky diode may also be passivated at the same time that the solar cell sunny-side passivation and ARC layer(s) is/are deposited, for example by a PECVD (to deposit single-layer or multi-layer passivation and ARC) process or a combination of Atomic-Layer Deposition or ALD (e.g., to deposit Aluminum Oxide passivation layer) and PECVD (to deposit hydrogenated silicon nitride passivation/ARC layer) process. The same passivation and ARC process and films used for the solar cell sunnyside also form the passivation on the MIBS frontside (the side opposite the patterned M1 side).
MIBS device plurality of pn-junction diode islands may be made in any geometrical shapes, for example including but not limited to square or circular or rectangular or other polygonal shapes, and have side dimensions, for example, in the range of less than about 100 microns up to about 100's of microns and may be as large as several millimeters. The number of trench-isolated MIBS diode islands may be in the range of at least 2 to tens or even several hundreds of MIBS islands. The MIBS islands may be distributed throughout the solar cell substrate according to any desired distribution pattern (including but not limited to a uniform regular distribution pattern throughout the solar cell substrate area or clustered around and near the edge of the solar cell or any other desired distribution pattern). All MIBS diode islands 48 have trench isolated edges for proper electrical isolation of the MIBS diode silicon islands from the solar cell silicon substrate region (all sharing the same continuous electrically insulating backplane sheet or substrate). As shown in
As can be seen in
In one fabrication embodiment,
As can be seen in
The MIBS embodiments disclosed herein employ trench isolation in conjunction with a shared backplane substrate to establish partitioning and electrical isolation between the semiconductor substrate regions of the MIBS device and the solar cell. One method to create the trench isolation regions is pulsed (such as pulsed nanoseconds) laser scribing. Below is a summary of key considerations and laser attributes for using a laser scribing process to form the trench isolation regions which partition and electrically isolate the MIBS diode substrate region(s) from the solar cell substrate region(s), such as for the previously described full-periphery MIBS rim diode or pn junction or Schottky diode:
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- Pulsed laser scribing for trench isolation formation may use a pulsed nanoseconds (ns) laser source at a suitable wavelength (e.g., green, or infrared or another suitable wavelength to ablate the semiconductor layer with relatively good selectivity to cut through the semiconductor substrate layer with respect to the backplane material) commonly used and proven for scribing and cutting through silicon. The laser source may have a flat-top (also known as top-hat) or a non-flat-top (e.g., Gaussian) laser beam profile. It's possible to use a pulsed laser source wavelength which is highly absorptive in silicon but can partially or fully transmit through the backplane (hence, cut through the semiconductor layer without substantially removing the backplane material after the through-semiconductor layer laser cutting is complete and the beam reaches the backplane sheet). For instance, we may use a pulsed nanoseconds IR or green laser beam which may effectively cut through the silicon substrate layer and partially transmit through the backplane material (hence, removing little to negligible amount of backplane material during the trench isolation cut).
- The pulsed laser beam diameter and other properties of the pulsed nanoseconds laser source may be chosen such that the isolation scribe width is in the range of a few microns up to 10's of microns as a width much larger than about 100 microns would be rather excessive and result in unnecessary waste of precious silicon substrate area and some reduction of the total-area efficiency of the solar cells and modules. Thus, it is beneficial to minimize the trench isolation areas as compared to the highly desirable solar cell area. In practice, pulsed nanoseconds laser cutting can produce trench isolation regions with width in the desirable range of about 20 microns up to about 60 microns. For instance, for a 156 mm×156 mm solar cell, a trench isolation width of 30 microns corresponds to an area ratio of 0.077% for the trench isolation area as a fraction of the cell area. This represents a rather negligible area compared to the solar cell area, in other words, this small ratio provides negligible waste of solar cell area and ensures negligible loss of total-area solar cell and module efficiency.
- Pulsed nanoseconds (ns) laser scribing or cutting to form trench isolation may be performed immediately after the backplane lamination process when using starting crystalline silicon wafers to fabricate the solar cells and associated MIBS devices (and in the case of solar cells and MIBS fabricated using epitaxial silicon lift-off processing, after completion of the backplane lamination process and subsequent lift-off release of the laminated cell from the reusable template and after or before pulsed laser trimming of the solar cell) in a back-contact/back-junction solar cell fabrication process as described herein. In the case of solar cells and MIBS fabricated using epitaxial silicon lift-off processing, the trench isolation scribing or cutting process may optionally use the same pulsed laser tool and source used for pre-release scribing of the epitaxial silicon layer to define the lift-off release boundary and/or used for post-release trimming of the laminated solar cell. Thus, no additional laser process tool may be needed in order to form the trench isolation regions.
- Pulsed nanoseconds (ns) laser scribing to form trench isolation may also be used to define the fully isolated MIBS rim diode region outside an isolated solar cell island surrounded by and defined by the rim. Alternatively, the pulsed ns laser scribing process may form other designs of the MIBS diode, such as in a multiple MIBS diode island design as well as and many other possible MIBS pattern designs.
- Pulsed laser scribing may be used to cut through the thin (such as sub-200 microns and more particularly sub-100 microns) silicon substrate layer (from the sunny side) and substantially stop on the backplane material sheet. If desired and/or required, a simple real-time in-situ laser scribe process end-pointing, such as using reflectance monitoring, may be used for process control and endpointing to minimize trenching or material removal in the backplane sheet while enabling complete through-semiconductor-layer laser cut.
- The sidewalls of the solar cell and the MIBS rim diode regions may be subsequently wet etched (for instance, as part of the solar cell sunny-side wet etch/texture process), post-texture cleaned, and passivated (by deposition of the passivation and ARC layer) during the remaining solar cell fabrication process steps.
Below, key process flow attributes are described in relation to a solar cell utilizing a pn junction diode used as a MIBS device implementation.
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- The solar cell process flow may remain essentially unchanged and harmonized (hence negligible to no added incremental fabrication cost) for MIBS device implementation with no additional fabrication process tools required to implement the MIBS pn junction diode with each solar cell.
- Trench isolation processes defining the full-periphery MIBS rim diode region and the solar cell island (or any other design for the MIBS diode arrangement) may be performed on the sunny-side or frontside, for example after completion of the cell processing through patterned M1 layer and backplane lamination to the silicon substrate (and in the case of solar cells made from epitaxial silicon lift-off processing, after epitaxial substrate release process), and in the case of solar cells made from epitaxial silicon lift-off processing, may use the same pulsed laser source used for pre-release silicon scribing as part of the release tool. The trench isolation laser scribing completely scribes the silicon substrate layer and substantially stops on the backplane with little or negligible removal of the backplane material.
- A MIBS pn junction diode p+ doped junction region may be formed concurrently with the same process steps that form the solar cell p+ doped field emitter (or the solar cell p+ doped emitter contact regions in case of an IBC cell process with selective emitter process comprising two different emitter heavily doped regions for the field emitter and for the emitter contact regions). The MIBS pn junction diode n-doped region may be same as the starting n-type crystalline silicon wafer used as the solar cell substrate and base region (or in the case of solar cells made from epitaxial silicon lift-off processing, the same as the in-situ-doped epitaxial solar cell base region). For instance, the same solar cell emitter and base doping processes (such as with APCVD, laser ablation, and thermal processing) used to fabricate the back-junction/back-contact solar cell may also be used to form the desired p+/n rim diode device structure concurrently and without added incremental process cost.
- Metal-1 (M1) and Metal-2 (M2) conductor patterns may be designed such that the p+ doped electrode of the MIBS pn junction diode is connected to the n-type base of the solar cell and the n-type substrate region ohmic contact (through n+ doped contact regions formed together with the solar cell n+ doped base contact regions) electrode of the MIBS diode is connected to the p+ emitter of the solar cell. These properly formed connections may be designed in a distributed format to minimize undesirable current crowding and localized hot spots whenever the MIBS diode is activated and bypasses the solar cell as a result of solar cell shading.
- Cell busbars (base and emitter busbars) and final coarser pitch pattern of interdigitated based and emitter fingers may be formed on the second level metal M2 pattern (which may be formed on the exposed surface of the backplane, in other words the opposite plane of the solar cell sunny-side). Patterned M2 also monolithically completes the interconnections of the solar cell with its MIBS device. The M1 pattern only has fine-pitch interdigitated base and emitter fingers without busbars to eliminate electrical shading due to busbars.
In the following section, the required MIBS diode area using a pn junction diode MIBS implementation embodiment is described. For exemplary purposes, this example is described for a 156 mm×156 mm solar cell. The minimum MIBS bypass diode area is governed by considerations such as the maximum allowable forward-bias (ON-state) resistance of the diode—or in other words when the MIBS diode is activated and forward biased as a result of solar cell shading. Assuming an n-type substrate region, the solar cell base, with phosphorus doping of about 3×1015 cm−3, this corresponds to an n-type substrate (or n-type base region) resistivity of about 1.60 Ω·cm. And further assuming a relatively thin crystalline silicon base region thickness of about 40 μm (microns), the required MIBS bypass diode area for three different levels of allowable series resistance values (excluding contact resistance) may be calculated as follows (this example is provided as a very approximate order of magnitude calculation as a rough guideline):
For a maximum allowable series resistance of Rs=0.010 Ω (max R·I2=1 W power dissipation for 5 W cell):
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- Area=(1.6 Ω·cm×40×10−4 cm)/0.01 Ω=0.64 cm2 (MIBS device area ˜0.26% of solar cell area)
- The rim width for 156 mm×156 mm cell: 0.64/(15.6×4)=0.010 cm=0.10 mm or 100 microns
For a max allowable series resistance of Rs=0.005Ω (max R·I2=0.5 W power dissipation for 5 W cell):
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- Area=(1.6 Ω·cm×40×10−4 cm)/0.005 Ω=1.28 cm2 (MIBS device area ˜0.52% of solar cell area)
- The rim width for 156 mm×156 mm cell: 1.28/(15.6×4)=0.020 cm=0.20 mm or 200 microns
For a max allowable series resistance of Rs=0.002Ω (max R·I2=0.1 W power dissipation for 5 W cell):
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- Area=(1.6 Ω·cm×40×10−4 cm)/0.002 Ω=3.20 cm2 (MIBS device area ˜1.30% of solar cell area)
- The rim width for 156 mm×156 mm cell: 3.20/(15.6×4)=0.050 cm=0.50 mm or 500 microns
Based on the above approximate calculations, for a 156 mm×156 mm solar cell a MIBS rim diode width in the range of about 100 μm to 500 μm is reasonable (in terms of limiting the on-resistance-induced power dissipation while maintaining a relatively small MIBS to solar cell area ratio) with the rim diode area being approximately ˜0.26% to ˜1.3% of solar cell area.
Alternatively, in a peripheral MIBS rim Schottky diode MIBS implementation embodiment of a back-contact back-junction (IBC) solar cell, the first-level metallization (M1) pattern (for example aluminum or aluminum-silicon alloy metallization) may be the same that shown in
The back-contact/back-junction IBC solar cell and associated MIBS diode are metallized and interconnected to form a completed solar cell. Example metallization uses a two-level metallization structure in conjunction with and enabled by the solar cell and MIBS shared backplane with a first-level contact metallization pattern (M1), for example made of aluminum or a suitable aluminum alloy such as aluminum with a small percentage of silicon, formed prior to the backplane attachment/lamination and a second-level final patterned metallization layer (M2), for example made of a thicker high-conductivity conductor comprising aluminum and/or copper or a combination thereof and optionally having additional layers such as a barrier layer and/or a top solder layer. The inter-level connections between M1 and M2 may be made using conductive via plugs through via holes drilled or formed in the backplane layer prior to the formation of the patterned M2 layer with the backplane serving as the electrically insulating inter-level dielectric layer. Key attributes of the two-level monolithic solar cell and MIBS metallization structure described above are as follows:
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- First-level metal M1 (for example formed on the solar cell backside prior to the backplane attachment and lamination) may be a patterned aluminum layer (and/or an alloy comprising aluminum such as Al and Si), made of PVD (plasma sputtering evaporation, ion-beam deposition, etc.) aluminum (or aluminum alloy) or screen printed aluminum (or aluminum alloy) paste.
- Patterned M1 serves as the contact metallization and forms the interdigitated base and emitter metallization lines on the solar cell (in some embodiments there are no busbars on M1 in order to eliminate or minimize electrical shading associated with busbars).
- In some embodiments, the patterned interdigitated M1 metallization fingers do not extend beyond the solar cell island to overlap underneath the trench isolation region and extend to the MIBS rim diode region. The electrical interconnections between the solar cell and its associated MIBS device are made using the patterned M2 layer and the conductive via plugs making patterned interconnections between the patterned M1 and M2 layers according to a pre-specified interconnection design.
- In the case of a full-periphery rim diode design used for MIBS, the M1 aluminum or aluminum alloy metallization level may be designed to form three concentric full-periphery continuous aluminum metallization loops (shown as square shaped loops for square-shaped cells) to make electrical ohmic contacts to the p+ doped junction region as well as to the inner and outer n-doped substrate regions (through n+ doped contact diffusion regions) of the MIBS rim diode.
- The M2 metal level may be formed using screen printing and/or PVD (such as plasma sputtering and/or thermal evaporation and/or electron-beam evaporation, for instance for metallization comprising aluminum) and/or electrochemical deposition or plating (for instance, for metallization comprising copper), or other metallization processes (or a combination thereof) with a relatively inexpensive, low-resistivity conductor material comprising copper and/or aluminum (or a combination thereof).
- The patterned M2 metal may be patterned in substantially orthogonal interdigitated fingers connected to the interdigitated on-cell M1 fingers through a plurality of conductive via plugs. In this design, the orthogonal arrangement of the coarser pitch M2 fingers of the solar cell with respect to the interdigitated finer pitch M1 fingers of the solar cell allow for the number of M2 fingers to be substantially less than the number of M1 fingers. For instance, the solar cell may have hundreds of M1 fingers directly formed on the cell prior to the backplane lamination while the number of M2 fingers formed after the backplane lamination may be typically a factor of approximately 5 to about 50 less than the number of M1 fingers.
- Patterned M2 metal may also connect the heavily p+ doped and n-type substrate contact M1 metallization of MIBS pn junction diode to the base and emitter busbars of the solar cell, respectively. Alternatively, in the case of using a Schottky barrier diode for MIBS, patterned M2 metal may also connect the Schottky barrier contact (for instance, aluminum or aluminum-silicon alloy non-ohmic Schottky contact on lightly doped n-type silicon) and n-type ohmic contact M1 metallization of MIBS Schottky diode to the base and emitter busbars of the solar cell, respectively.
Again it is important to note that while the embodiments described herein have been largely explained in conjunction with back-contact/back-junction crystalline silicon solar cells using thin crystalline silicon absorber layers and continuous backplanes, it should be understood that aspects of the disclosed subject matter may be applied to other solar cell and module implementations by one skilled in the art, including but not limited to: non-IBC back-contact solar cells (including but not limited to the MWT solar cells), front contact solar cells and corresponding PV modules; non-crystalline silicon solar cells and modules such as those made from crystalline GaAs, GaN, Ge, and/or other elemental and compound semiconductors; and, various wafer-based solar cells including back-contact/front-junction, back-contact/back-junction and front-contact solar cells made from crystalline semiconductor wafers, such as CZ mono-crystalline silicon wafers, FZ mono-crystalline silicon wafers, and cast multi-crystalline silicon wafers.
However, as noted earlier, the use of back-contact cells may be advantageous in some respects as MIBS implementations may be applied to back-contact cells without substantially impacting final module manufacturing. Further, availability of both the emitter and base interconnection leads on the backsides of the cells may further simplify the overall implementation of on-cell electronics for enhanced energy harvesting as well as additional cell-level monitoring and control functions.
For the purpose of electrical polarity differentiation,
The MIBS rim diode (pn junction diode or Schottky barrier diode) and solar cell and the related metallization dimensions are not shown to relative scale. Plurality of conductive via plugs 120 connect the desired portions of M2 metallization to the specified portions of M1 metallization layer and may be formed by drilling vias through the backplane to the intended M1 regions then forming the conductive via plugs during M2 metallization. The combination of M1 pattern as depicted in
For the purpose of electrical polarity differentiation,
The MIBS devices described herein utilize either a Schottky barrier diode or a pn junction diode. If a Schottky barrier diode is used as MIBS, an aluminum metal electrode, or aluminum with some silicon content, positioned on the lightly-doped n-type silicon in the MIBS silicon substrate regions as the Schottky contact may be used. Key attributes and descriptions relating to Schottky barrier diode MIBS embodiments include:
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- A MIBS Schottky barrier diode may be made by forming two metal contacts (from the same M1 layer) on a semiconductor surface (such as on silicon). One metallic contact, which may be formed on a heavily doped region of the semiconductor substrate, is an ohmic contact (for instance, formed through n+ doped regions placed on designated areas of the n-type substrate) and the other contact is formed on a lightly doped n-type region of the semiconductor substrate and forms a metal-to-n-type semiconductor Schottky barrier (non-ohmic) contact that provides diode rectification electrical properties. The same metal (M1 pattern) may be used for both the Schottky barrier (non-ohmic) contact and n-type substrate ohmic contact (the latter through doped n+ regions on n-type substrate) of the MIBS Schottky diode at minimal or no additional fabrication costs for the solar cell manufacturing.
- If n-type silicon is used for the semiconductor substrate (such as for the solar cell base region for a crystalline-silicon back-contact/back-junction cell as described herein), aluminum or an alloy of aluminum with some silicon content may be used as the Schottky barrier metal. These materials provide excellent Schottky barrier diode performance properties and are compatible with the solar cell process flow and materials. Aluminum has a work function which is less than the n-type silicon work function and forms a good Schottky barrier on lightly doped n-type silicon where the lightly doped silicon surface is provided by the n-type silicon substrate layer also used as the solar cell base and absorber. Aluminum, or an alloy of aluminum with some silicon content, may also be used as the ohmic contact on n+ doped silicon for the other terminal of the Schottky diode (i.e., ohmic contact to the n-type silicon substrate through n+ doped regions).
- For a high-performance Schottky barrier diode, whether for a front contact or back contact solar cell, n-type silicon substrates may be used as compared to p-type silicon substrates. The use of n-type silicon substrate is also advantageous for fabrication of high-efficiency solar cells without any bulk light-induced degradation (commonly observed with p-type silicon wafers).
- Applying a positive potential to the aluminum Schottky barrier contact metal electrode on n-doped silicon (also called the Schottky contact) results in a smaller potential drop across the silicon layer—thus, decreasing the barrier height for electron injection from the lightly doped n-type silicon substrate to the aluminum Schottky contact electrode. Thus, more electrons will diffuse toward the metal than into the silicon and a net electrical current will flow through the junction. This is the forward bias or ON state of the Schottky barrier diode. This forward-bias condition is the MIBS state providing protection for the solar cell in case of shading.
- As a negative voltage (or reverse bias voltage) is applied to the Schottky aluminum metal electrode, the potential across the barrier rises increasing the depletion layer width and suppressing electron injection from the n-type silicon substrate into the metal electrode. The resulting potential barrier limits the electrons flowing to the metal electrode and results in negligible current (OFF state of the MIBS Schottky diode—This reverse-bias condition represents the MIBS state when there is no solar cell shading). An aluminum-semiconductor Schottky contact junction can provide excellent rectifying properties to be used as MIBS. While a large current may exist under forward bias (ON state), negligible current flows under reverse bias (OFF state), both desirable properties for MIBS.
- In some instances, a Schottky barrier diode may used as compared to a pn junction diode in a MIBS implementation. A Schottky barrier diode has a smaller ON-state forward-bias voltage than a pn junction diode (e.g., on the order of ˜0.2 V to 0.5V for Schottky diode vs ˜0.6 V to 0.8 V for a pn junction diode) resulting in a lower power dissipation by the MIBS device when a Schottky barrier diode is used as MIBS (when the solar cell is shaded, the MIBS device is turned on to protect the solar cell). The smaller power dissipation of the Schottky barrier diode compared to the pn junction diode is quite advantageous and makes the Schottky barrier diode a superior choice for the MIBS device.
- A MIBS rim Schottky diode MIBS implementation may use a relatively lightly doped n-type silicon substrate as the main doped diode region. In a solar cell substrate fabrication process using epitaxial silicon lift-off solar cell processes with epitaxially grown n-type base and a back-contact/back-junction solar cell design, the n-type silicon region for the MIBS diode may be formed from the same substrate as the epitaxial n-doped silicon (or the base region of the solar cell) and which are subsequently electrically isolated from each other using trench isolation during cell processing. In this case, the region used for the Schottky aluminum contact has light n-type doping, the same as the solar cell base doping (e.g., phosphorus doping on the order of 3×1015 cm−3, while the doping may be larger or smaller than this amount depending on the solar cell design requirements), without the heavily-doped n+ base contact diffusion region. The ohmic contact to the n-type silicon substrate (the second terminal of the Schottky diode) may be also be made using aluminum (or an alloy of aluminum with some silicon content) as part of the patterned M1 metallization layer through n+ doped (heavily doped phosphorus) ohmic contact regions formed on the designated regions of the n-type substrate.
- The ohmic contact of the MIBS Schottky barrier diode is formed by using the aluminum ohmic contact to the n-type silicon substrate region, through the heavily-doped n+ doped contact diffusion regions (this is formed using and during the same process that also forms the n+ doped regions used for the base ohmic contact of the back-junction/back-contact solar cell).
- The aluminum (or Al/Si alloy) layer utilized to make the aluminum (or aluminum silicon) to n-type silicon Schottky contact and aluminum (or aluminum silicon) to n+ silicon (and n-type silicon) ohmic contact may be the same Metal-1 (M1) aluminum (and/or aluminum silicon) layer used to make the interdigitated base and emitter contact metallization in the solar cell. For example, it may be a high conductivity aluminum layer with some silicon content (a few percentage points of silicon to prevent junction spiking or aluminum spiking into silicon) to make high-quality electrical ohmic (and Schottky) contacts to silicon. The patterned M1 aluminum layer may be made using screen printing, stencil printing, aerosol jet printing, or inkjet printing of aluminum (or aluminum alloy) paste or aluminum (or aluminum alloy) ink (again, for example, with a silicon content percentage to prevent junction spiking), followed by thermal curing of the paste or ink. Alternatively, Metal 1 (M1) may be formed by another suitable method, for instance, a deposition method such as plasma sputtering, thermal or electron-beam evaporation, ion beam deposition, or another blanket deposition method followed by M1 patterning (e.g., by laser ablation or wet etch patterning). The thickness of M1 aluminum or aluminum alloy layer may depend on the resistivity of the aluminum layer. Typically, techniques such as physical-vapor deposition or PVD (e.g., plasma sputtering or thermal evaporation or electron-beam evaporation) deposit aluminum layers with near-bulk electrical conductivity (e.g., resistivity ˜3 μΩ·cm), thus the required thickness of M1 aluminum layer may be in the approximate range of about 100 nm up to about 2000 nm (thicker M1 metal would not be required due to the two-level M1-M2 metallization architecture). On the other hand, formation of M1 from aluminum or aluminum alloy paste or ink typically results in a lower resulting metal conductivity (much lower conductivity than that of bulk aluminum), such as material resistivity in the range of ˜30 μΩ·cm to ˜200 μΩ·cm. Therefore, a thicker metal layer would be required if M1 is produced from paste or ink (for instance, screen printed M1 in the thickness range of about 1 micron up to about 20 microns).
For instance,
As another embodiment,
In another embodiment shown in
In another embodiment shown in
The representative structures shown in
In the process flow of
Again, the n-type epitaxial silicon layer (or the n-type crystalline silicon wafer in the case of using CZ or FZ or multi-crystalline wafers instead of epitaxial silicon substrates) serves as the monolithic substrate for both the solar cell and the MIBS device. This n-type layer serves as the absorber substrate and base of the solar cell as well as the n-type substrate region of the MIBS pn junction diode. The emitter process forming the p+ field emitter and p++ doped emitter contact regions also forms the MIBS p+(and/or p++) regions for the pn junction diode. The APCVD PSG assisted process to form the n+ heavily doped regions is used both for the solar cell base ohmic contact regions and also for the MIBS ohmic contact to the n-type substrate region of the pn junction diode. The solar cell M1-M2 metallization makes contact to the MIBS pn junction diode and completes monolithic interconnections with the solar cell as an integrated shade management bypass switch.
One specific process tool is added to the flow (Tool 8) to perform pulsed picoseconds (or pulsed femtoseconds or nanoseconds) laser ablation of the PSG/UGS layer immediately after the APCVD PSG/USG process and prior to the furnace anneal process to enable fabrication of the MIBS Schottky barrier diode. This single added process step and tool allows for subsequent fabrication of the Schottky contact (aluminum or aluminum-silicon to n-type silicon) during the patterned M1 process. Next, the backplane is permanently attached and laminated to the backside of the solar cell on the template (Tool 13). Subsequently (in Tool 14), the solar cell (and its associated MIBS) is lifted off and detached from the reusable template (by laser scribing to define the release boundary, mechanical lift-off release, and laser trimming of the lifted solar cell) and the trench isolation region(s) to define and electrically isolate the MIBS region(s) is (are) formed by scribing from the sunny-side of the detached backplane-laminated solar cell, for example using the same pulsed laser source or tool used to perform the pre-release scribing of silicon and/or the post-release trimming of the solar cell and MIBS peripheral boundary. Then, the remaining back-end solar cell (and MIBS) processing steps are completed (Tools 15 through 19), including sunny-side texture and post-texture wet clean (which may also clean the laser-scribed isolation trenches), PECVD sunny-side passivation and ARC deposition (which may also passivate the MIBS front surface and sidewalls/edges), and final high-conductivity M2 metallization on the backplane (using one or an appropriate combination of screen printing, PVD, and/or plating).
The MIBS Schottky diode solar cell implementation of
The process flow of
The above-mentioned representative process flows show several embodiments of this invention to implement either Schottky barrier diode or pn junction diode MIBS devices with the solar cells using a monolithic fabrication process with negligible or small cost addition to the main solar cell process flow.
A peripheral MIBS diode may have continuous closed-loop p+ doped junction sandwiched between the n-type regions (as seen in
For an Al/n-Si Schottky barrier diode MIBS, the aluminum contact on n-type Silicon for Schottky contact may be either a paste made of pure aluminum or an alloy of aluminum with some silicon addition in order to mitigate or eliminate the possibility of aluminum spiking into silicon (same paste used for solar cell M1 single print or double print).
Optionally, any solar photo-generation effect in the MIBS pn junction diode may be suppressed or mitigated by one of several techniques including an end-of-the-line laser irradiation of the MIBS diode rim on the solar cell sunny-side to degrade passivation and substantially increase the front surface recombination velocity (FSRV) on the MIBS rim diode. Alternatively, the MIBS diode rim surface may be coated with a suitable inexpensive black light blocker ink, such light-blocking ink may be applied by inkjet or screen printing. Alternatively, an M1 pattern design which maximizes the M1 metal contact area coverage of the pn junction contacts, and thus increases the metal contact recombination losses in the MIBS device (and not in the solar cell) may be used.
Metallization structures described above have metallization and interconnections of the solar cell and the MIBS diode (for example a pn junction diode or Schottky barrier diode) using the combination of both M1 and M2 layers in a two-level metallization scheme. In another metallization structure, full metallization of the MIBS occurs at the M1 level and M2 is used only for the solar cell final high-conductivity metallization. This approach may be particularly attractive when the MIBS pn junction or Schottky diodes are integrated with an array of mini-cells or tiled mini-cell cell array, forming the master cell (master cell made of series-connected mini-cells or trench-isolated tiles)—as shown in
An M1-only MIBS metallization and MIBS diode (pn junction diode or Schottky barrier diode) interconnection to the associated solar cell allows for: (i) M2 to be dedicated only to the solar cell metallization and interconnection through conductive M2-M1 via plugs landing on the interdigitated M1 fingers of the solar cell; (ii) the elimination of M2-M1 via plugs landing on the MIBS diode metallization area; (iii) making M2 recessed and offset with respect to the overall MIBS-integrated solar cell peripheral edges which may be attractive for certain M2 metallization processes such as one-sided M2 copper plating tool when using copper plating.
Similarly,
In a first-level only metallization and MIBS/solar cell interconnection pattern (M1) for a full-periphery rim diode using aluminum on n-type silicon Schottky barrier diode implementation as described with reference to
While the MIBS embodiments have been described herein in conjunction with back-contact back-junction crystalline silicon solar cells using thin (sub-200 μm thickness and as thin as sub-100 μm thickness) crystalline silicon absorber layers formed by porous silicon sacrificial and epitaxial silicon lift-off processing as well as associated continuous backplanes, it should be understood that the MIBS embodiments in accordance with the disclosed subject matter may be applied to other solar cell and PV module implementations, including but not limited to the following:
-
- Solar cell substrates and resulting solar cells made of crystalline silicon fabricated by kerfless thin silicon exfoliation techniques such as proton or hydrogen ion implantation and exfoliation, metal stress induced thin silicon exfoliation, or any thickness of crystalline silicon wafers made by slurry or diamond wire saw.
- Solar cells made using other crystalline semiconductor materials such as crystalline gallium arsenide, gallium nitride, germanium, silicon carbide, other compound semiconductors, etc.
- Non-IBC back-contact solar cells (including but not limited to the MWT solar cells).
- Front contact solar cells and PV modules comprising such front-contact cells.
- Wafer-based solar cells including both back-contact/back-junction and front-contact solar cells made from crystalline semiconductor wafers (such as CZ or FZ mono-crystalline silicon wafers or cast multi-crystalline silicon wafers) made using wire saw and other wafering techniques, with solar cell wafers attached to backplanes
Back-contact/back-junction cells may be advantageous in some applications as MIBS embodiments may be implemented without detrimentally impacting the final module assembly. Availability of both the emitter and base interconnection leads on the backsides of the cells (for instance, using the back-contact/back-junction (IBC) solar cells such as thin crystalline semiconductor supported on a backplane) is advantageous for various MIBS embodiments.
Further, the solar cell embodiments disclosed herein may be packaged as cell modules in a variety of materials such as rigid glass covered modules or flexible light weight photovoltaic module laminate without a glass cover.
The foregoing description of the exemplary embodiments is provided to enable any person skilled in the art to make or use the claimed subject matter. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the innovative faculty. Thus, the claimed subject matter is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A monolithically integrated solar cell and bypass switch structure, comprising:
- a semiconductor layer forming a solar cell region and a bypass switch region, said solar cell region and said bypass switch region partitioned by an electrical isolation trench, said semiconductor layer having a light receiving frontside and a backside opposite said frontside;
- a patterned first-level metal layer positioned over said semiconductor layer backside providing base and emitter metallization of said solar cell region and metallization of said bypass switch region;
- an electrically insulating backplane positioned over said patterned first-level metal layer;
- said electrical isolation trench formed through said semiconductor layer to said electrically insulating backplane and electrically isolating said solar cell region and said bypass switch region;
- a patterned second-level metal layer positioned over said electrically insulating backplane; and
- a plurality of electrically conductive via plugs formed through said electrically insulating backplane connecting select portions of said patterned second-level metal layer to select portions of said patterned first-level metal layer;
- said patterned first-level metal layer, said patterned second-level metal layer, and said plurality of electrically conductive via plugs electrically connecting said integrated solar cell and bypass switch structure.
2. The integrated solar cell and bypass switch structure of claim 1, wherein said patterned first-level metal (M1) is an interdigitated pattern of busbarless base and emitter fingers.
3. The integrated solar cell and bypass switch structure of claim 1, wherein said patterned second-level metal (M2) is an interdigitated pattern of base and emitter fingers with solar cell busbars.
4. The integrated solar cell and bypass switch structure of claim 1, wherein said patterned second-level metal (M2) is substantially orthogonal to the patterned first-level metal (M1).
5. The integrated solar cell and bypass switch structure of claim 1, wherein said semiconductor layer is a mono-crystalline silicon layer.
6. The integrated solar cell and bypass switch structure of claim 1, further comprising a passivation layer on said backside of said semiconductor layer.
7. The integrated solar cell and bypass switch structure of claim 1, wherein said solar cell is a back-contact solar cell.
8. The integrated solar cell and bypass switch structure of claim 1, wherein said solar cell is an interdigitated back-contact (IBC) solar cell.
9. The integrated solar cell and bypass switch structure of claim 1, wherein said bypass switch region comprises a bypass diode.
10. The integrated solar cell and bypass switch structure of claim 1, wherein said bypass switch is a pn junction diode.
11. The integrated solar cell and bypass switch structure of claim 10, wherein the p-type and n-type terminals of said pn junction diode are connected to the n-type and p-type terminals of said solar cell, respectively.
12. The integrated solar cell and bypass switch structure of claim 1, wherein said bypass switch is a Schottky barrier diode.
13. The integrated solar cell and bypass switch structure of claim 1, wherein said bypass switch is a transistor.
14. The integrated solar cell and bypass switch structure of claim 1, wherein said electrically insulating backplane is a flexible prepreg sheet.
15. The integrated solar cell and bypass switch structure of claim 1, wherein said electrically insulating backplane sheet is rigid.
16. The integrated solar cell and bypass switch structure of claim 1, wherein said electrically insulating backplane is a flexible aramid fiber and resin prepreg sheet.
17. The integrated solar cell and bypass switch structure of claim 1, wherein said semiconductor layer comprises a plurality of mini solar cell regions and corresponding bypass switch regions.
18. The integrated solar cell and bypass switch structure of claim 1, wherein said bypass switch is a full-periphery rim diode surrounding said solar cell region and separated from said solar cell region by said trench isolation pattern.
19. The integrated solar cell and bypass switch structure of claim 1, wherein said bypass switch region comprises a plurality of diodes.
20. The integrated solar cell and bypass switch structure of claim 1, wherein said bypass switch is a diode located on at least one side of said solar cell region and separated from said solar cell region by said trench isolation pattern.
21. The integrated solar cell and bypass switch structure of claim 1, wherein said bypass switch is a diode located on at least one corner of said solar cell region and separated from said solar cell region by said trench isolation pattern.
22. The integrated solar cell and bypass switch structure of claim 1, wherein said bypass switch comprises at least one diode island located within the area of said solar cell region and separated from said solar cell region by said trench isolation pattern.
23. The integrated solar cell and bypass switch structure of claim 1, wherein said bypass switch comprises at least one diagonal diode island positioned between two opposite diagonal corners of said solar cell region and separated from said solar cell region by said trench isolation pattern.
24. The integrated solar cell and bypass switch structure of claim 1, further comprising a plurality of monolithically integrated solar cells and bypass switches supported in a module laminate.
25. The integrated solar cell and bypass switch structure of claim 24, wherein said module laminate is a flexible laminate.
26. The integrated solar cell and bypass switch structure of claim 24, wherein said module laminate is a rigid glass-covered module laminate.
Type: Application
Filed: Dec 18, 2015
Publication Date: Dec 15, 2016
Inventor: Mehrdad M. Moslehi (Los Altos, CA)
Application Number: 14/975,496