Semiconductor Substrate
A semiconductor substrate includes a device carrier, a plurality of stiffener structures and a plurality of spaced areas. The device carrier includes a plurality of trace layout units and a periphery around the trace layout units. The stiffener structures are disposed on the device carrier along the periphery of the trace layout units. The spaced areas are disposed between the stiffener structures.
This application is a continuation application of U.S. patent application Ser. No. 13/128,252 filed May 9, 2011, which is a national stage of PCT application PCT/SG2009/000439, filed Nov. 20, 2009, claiming priority of U.S. Provisional Patent Application 61/116,703, filed Nov. 21, 2008, the subject matters of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION Field of the InventionThe invention relates in general to a substrate, and more particularly to a semiconductor substrate.
Description of the Related ArtIn the past, the semiconductor industry has seen integrated circuits (IC) being produced with fewer IC pads and interconnecting structures. This enables the spacing between the leads and interconnecting structures in the IC. However, recently, the IC packages have become more compact and require increased functions to be incorporated into a semiconductor chip. Additionally, the chip has to be dimensionally small to enable the IC packages to be compact. It is therefore desirable for the interconnecting structures to be spaced apart while increasing the number of interconnection due to the increased logic function on the chip. The increased logic function on the chip means an increase in circuit density of the chip. As circuit density increases on the small-sized chip, it becomes important to provide a thin, reliable and robust packaging for forming the miniature packages. Also, the mechanical, electrical and heat dissipation properties of such miniature packages need to be carefully considered without affecting the overall performance of the IC.
Furthermore, a general concern for IC packaging of a semiconductor device is on the integrity of the IC package structure. The IC package structure typically comprises a substrate on which the semiconductor device is disposed. Typically, the substrate may be damaged due to, for example, cracks in the substrate when the substrate is subjected to stress. The substrate may be stressed during the coupling of the semiconductor device to the substrate or the handling of the IC package.
Additionally, after coupling the semiconductor device to the substrate, the structure of the IC package may also be weakened due to additional stress on the substrate and hence renders the IC package more susceptible to damages. Damages in the substrate adversely affect the integrity of the IC package structure, leading to insufficient support for the semiconductor device. It is therefore desirable to provide a solution to address at least one of the foregoing problems of the conventional operations.
SUMMARY OF THE INVENTIONIt is therefore an object of the invention to provide a semiconductor substrate. The semiconductor substrate includes a device carrier, a plurality of stiffener structures and a plurality of spaced areas. The device carrier includes a plurality of trace layout units and a periphery around the trace layout units. The stiffener structures are disposed on the device carrier along the periphery of the trace layout units. The spaced areas are disposed between the stiffener structures.
Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
Referring to
The conductive layer has at least one trace layout unit 119a having a periphery 119b. The conductive layer includes a plurality of electro-isolated package traces 118a and a plurality of studs 118b. The location and number of the studs 118b are preferably in accordance with that of the package traces 118a. Preferably, the package traces 118a are embedded in the first surface 110a, and the studs 118b are embedded in the second surface 110b and electrically connected to the package traces 118a. At least one of the studs 118b is used for electrically connecting to other element or any peripheral device. The peripheral device is a printed circuit board (PCB), for example, which has a plurality of contact pads in the form of an array. The semiconductor package 100 can be assembled to the PCB by welding the studs 118b to connect to the contact pads.
As shown in
Referring to
As shown in
The device carrier 110 of the semiconductor package receives one or more semiconductor chips for forming a semiconductor assembly. As shown in
The semiconductor assembly 200 further includes an interconnecting structure disposed in the cavity 130 for electrically connecting the chip 205 to the device carrier 110. Preferably, the transmission of signal between the studs 118b, which are electrically connected to other elements, and the chip 205 is achieved by the interconnecting structure 240.
The interconnecting structure 240 includes one or more electrical paths. Each of the electrical paths has at least one interconnecting layer. Preferably, the electrical path has two interconnecting layers, one interconnecting layer is preferably formed from a conductive material such as copper, and the other interconnecting layer is preferably formed from a solder material such as lead or tin. Examples of the electrical paths are pillar bumps and solder bumps.
Furthermore, as shown in
The cavity 130 defined by the stiffener structure 120 facilitates the disposition of the filling structure, and easily controls the range and volume of the filling structure within the semiconductor package 300. Besides, the stiffener structure 120 and the filling structure thicken the structure of the device carrier 110, which reduces the possibility of flexure and crack on the device carrier 110 and provides additional support for the semiconductor package 300.
The semiconductor package 300 further includes a sealing cap 310 disposed above the chip 205 and assembled to the stiffener structure 120 for encapsulating and protecting the chip 205 and the filling structure. The sealing cap 310 and the stiffener structure 120 are combined by an adhesive layer or a solder layer 315. The sealing cap 310 is preferably formed from metals and is used for applications such as electrostatic discharge protection, heat dissipation, and moisture proof. In the case of heat dissipation application, a heat conductive layer 320 is preferably disposed between the sealing cap 310 and the chip 205 to conduct the heat generated from the chip 205 to the external space.
Referring to
Preferably, as shown in
The guiding elements 540 are embedded in the device carrier 510 in the disclosure however the invention is not limited thereto. The guiding elements 540 can also be protruded from the upper surface of the device carrier 510 and partially embedded in the device carrier 510.
A manufacturing method of semiconductor package is disclosed. The manufacturing method includes the steps of: providing a base layer; forming a patterned trace layout on the base layer; forming an insulating layer on the base layer and covering the patterned trace layout for forming a semiconductor substrate; forming a plurality of stiffener structures on the insulating layer to form a plurality of cavities with the insulating layer; and, breaking the semiconductor substrate along a plurality of spaced areas between the stiffener structures for forming a plurality of device carriers. The carrier array 500 of
Next, a patterned trace layout is formed on the base layer 700. As shown in
Then, as shown in
Next, an insulating layer is formed on the patterned trace layout for forming a semiconductor substrate of the carrier array. Preferably the insulating layer is formed using a molding material. Preferably, the molding material has a brittle nature. As shown in
Then, a plurality of stiffener structures are formed on the insulating layer 727. As shown in
If the stiffener structures 520 each have a multi-layer structure, one layer of the stiffener structures 520 can be formed by patterning the base layer 700, and another layer of the stiffener structures 520 can be additionally formed in accordance with the previous layer.
The manufacture of the carrier array 500 is hence finished. Before the step of separating the carrier array 500 to form a plurality of carrier units (such as the carrier units 500a and 500b of
A filling structure is then disposed in the cavities 730. In this step, as shown in
When forming individual carrier unit, the carrier array 500 of
According to the semiconductor package and the manufacturing method thereof disclosed in the embodiment of the invention, the stiffener structure is disposed on the device carrier for predetermining the location of the filling structure and controlling the volume of the filling structure in the subsequent process. Besides, the stiffener structure and the filling structure located between the chip and the device carrier provide additional support for the chip and the semiconductor package, enhancing the structural strength of the semiconductor package and impeding the flexure to the package, which largely increases the yield of the manufacturing process. Furthermore, when manufacturing the semiconductor package, the semiconductor substrate is separated via the bending or shear mechanism along predetermined spaced areas in which the guiding elements are located. Therefore, individual device carrier is produced without the use of blade, which is quite different from the conventional manufacturing method accompanied by the problem of worn blade.
While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
Claims
1. A semiconductor substrate, comprising:
- a device carrier comprising a plurality of trace layout units and a periphery around the trace layout units;
- a plurality of stiffener structures disposed on the device carrier along the periphery of the trace layout units; and
- a plurality of spaced areas disposed between the stiffener structures.
2. The semiconductor substrate according to claim 1, wherein the device carrier having a first surface and a second surface opposite to the first surface, the plurality of stiffener structures disposed on the first surface of the device carrier.
3. The semiconductor substrate according to claim 2, wherein the plurality of stiffener structures extend on the first surface in a direction away from the second surface to form a cavity with the device carrier.
4. The semiconductor substrate according to claim 2, further comprising:
- a plurality of locking elements disposed below the plurality of stiffener structures and embedded within the device carrier, wherein the plurality of locking elements adjoins the plurality of stiffener structures and extends away from the stiffener structure towards the second surface of the device carrier.
5. The semiconductor substrate according to claim 4, wherein the plurality of locking elements extend from the first surface of the device carrier to the second surface of the device carrier, and exposed on the second surface of the device carrier.
6. The semiconductor substrate according to claim 2, wherein the device carrier comprises at least one conductive layer, wherein the at least one conductive layer connects the first surface of the device carrier to the second surface of the device carrier.
7. The semiconductor substrate according to claim 6, wherein the device carrier comprises a plurality of conductive layers disposed on the different locations of the device carrier.
8. The semiconductor substrate according to claim 7, wherein the plurality of conductive layers comprises:
- a first conductive layer comprising a plurality of traces; and
- a second conductive layer comprising a plurality of studs, wherein the plurality of studs are disposed correspondingly on the plurality of traces;
- wherein the plurality of traces and studs are embedded in the insulating layer between the first and second surface of the device carrier, the plurality of traces and studs form the plurality of trace layout units.
9. The semiconductor substrate according to claim 7, wherein at least one of plurality of conductive layers is electrically connected to the stiffener structure.
10. The semiconductor substrate according to claim 1, wherein the stiffener structure comprises at least one metallic material.
11. The semiconductor substrate according to claim 10, wherein the stiffener structure further comprises at least one polymeric material disposed between the first surface of the device carrier and the stiffener structure.
12. The semiconductor substrate according to claim 1, wherein the stiffener structure comprises a metallic material and a polymeric material.
13. The semiconductor substrate according to claim 1, wherein the stiffener structure comprises a metallic material and a solderable material.
14. The semiconductor substrate according to claim 1, wherein the stiffener structure comprises a continuous ring-shaped structure.
15. The semiconductor substrate according to claim 1, wherein the stiffener structure comprises a discontinuous ring-shaped structure.
16. The semiconductor substrate according to claim 1, wherein the stiffener structure is disposed on the edge of the semiconductor substrate.
17. The semiconductor substrate according to claim 1, further comprising:
- a plurality of guiding elements disposed on the device carrier in accordance with the spaced areas.
18. The semiconductor substrate according to claim 17, wherein the guiding elements each have at least one portion embedded in the device carrier.
19. The semiconductor substrate according to claim 17, wherein the guiding elements each comprise a first guiding layer and a second guiding layer.
20. The semiconductor substrate according to claim 19, wherein the second guiding layer is a discontinuous guiding layer.
21. The semiconductor substrate according to claim 19, wherein the width of the first guiding layer is larger than the width of the second guiding layer.
22. The semiconductor substrate according to claim 17, wherein the shape of each guiding element is irregular.
23. The semiconductor substrate according to claim 17, wherein the plurality of trace layout units is in the form of array, the plurality of spaced areas forms at least one breaking line between the plurality of trace layout units.
24. The semiconductor substrate according to claim 23, wherein the breaking line is disposed between the stiffener structure and the guiding element.
25. The semiconductor substrate according to claim 24, wherein the semiconductor substrate is separated along the breaking line.
26. The semiconductor substrate according to claim 17, wherein the device carrier comprises:
- at least one insulating layer formed using a molding material.
27. The semiconductor substrate according to claim 1, wherein the semiconductor substrate is separated via the bending mechanism along the spaced area.
28. The semiconductor substrate according to claim 1, wherein the semiconductor substrate is separated via the shear mechanism along the spaced area.
Type: Application
Filed: Dec 18, 2017
Publication Date: Apr 19, 2018
Inventors: Shoa-Siong Lim (Singapore), Kian Hock Lim (Singapore)
Application Number: 15/844,837