BUMP-IN-THE-WIRE TIME CODE SIGNAL DECODER AND DEBUGGER
A bump-in-the-wire time code signal decoder and debugger apparatus includes a controller structured and configured to: receive an encoded time code signal, decode the encoded time code signal, and produce a parsed signal based on the decoding of the encoded time code signal. The apparatus also includes a communications interface coupled to the controller, wherein the communications interface is structured to receive the parsed signal and generate an output signal based on the parsed signal.
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The disclosed concept pertains generally to time codes/signals that are used by various electronic devices for data correlation with time, and, more particularly, to a bump-in-the-wire device that is capable of decoding and parsing time codes/signals, such as, without limitation, IRIG time codes, for use by downstream electronic devices and/or for clock debugging purposes.
Background InformationModern-day electronic systems, such as communication systems, data handling systems, and power distribution systems, require precise time information for data correlation with time. Inter-range instrumentation group time codes, commonly known as IRIG time codes, are standard time code formats that were created by the Telecommunications Working Group of the US military's Inter-Range Instrumentation Group (IRIG).
IRIG time codes are widely used for transferring time information. An IRIG time code is made up of repeating frames of various types of time information. The codes are generated by a clock or “time-of-day” source, such as an atomic frequency standard or a GPS receiver, and are provided to remote terminal devices for time correlation purposes.
The IRIG time code standard defines a number of different time code protocols, each identified by unique alphabetic designation. The main difference between the various codes is their rate, which varies between one pulse per minute and 10,000 pulses per second.
The IRIG-B time code protocol is widely used by electric utilities, industrials, and others to ensure precise time synchronization of power system devices, such as breakers, phase measurement units, relays and meters. An IRIG-B time code signal consists of a frame containing 100 bits of information that is generated every second. In each frame, 74 of the bits contain various time and date information in binary form (logical ones and zeros), with the remainder of bits being used as position identifiers or padding. IRIG-B time code signals thus provide a reliable method of transmitting time to synchronize power equipment devices.
When an IRIG-B time code signal is received by the electronic device, it must be decoded prior to being utilized. IRIG-B decoding, however, can be expensive in terms of CPU power. For example, in a typical application, decoding the IRIG-B signal takes about 30% of the CPU time just due to the interrupts generated by the signal. In addition, many systems use IRIG-B clock sources from different manufacturers. As a result, it is often necessary to debug those clocks and devices that use those clocks. For example, a clock source may configure the IRIG-B signal in a manner that does not match up with what the receiving device is expecting. In such a situation, it may be necessary to change the settings of either the clock source or the receiving device. In order to do so, the IRIG-B signal must be obtained in a format that allows for the analysis to be performed.
SUMMARYIn one embodiment, a time code signal decoder and debugger apparatus is provided. The apparatus includes a controller structured and configured to: (i) receive an encoded time code signal, (ii) decode the encoded time code signal, and (iii) produce a parsed signal based on the decoding of the encoded time code signal. The apparatus also includes a communications interface coupled to the controller, wherein the communications interface is structured to receive the parsed signal and generate an output signal based on the parsed signal.
In another embodiment, a method of processing an encoded time code signal is provided. The method includes receiving the encoded time code signal in an apparatus including a housing that houses a controller and a communications interface coupled to the controller, decoding the encoded time code signal within the apparatus, producing a parsed signal based on the decoding of the encoded time code signal within the apparatus, and generating in and transmitting from the apparatus an output signal based on the parsed signal.
A full understanding of the disclosed concept can be gained from the following description of the preferred embodiments when read in conjunction with the accompanying drawings in which:
Directional phrases used herein, such as, for example, left, right, front, back, top, bottom and derivatives thereof, relate to the orientation of the elements shown in the drawings and are not limiting upon the claims unless expressly recited therein.
As used herein, the singular form of “a”, “an”, and “the” include plural references unless the context clearly dictates otherwise.
As used herein, the term “number” shall mean one or an integer greater than one (i.e., a plurality).
As used herein, the statement that two or more parts are “coupled” together shall mean that the parts are joined together either directly or joined through one or more intermediate parts.
As used herein, the term “controller” means a programmable analog and/or digital device (including an associated memory part or portion) that can store, retrieve, execute and process data (e.g., software routines and/or information used by such routines), including, without limitation, a programmable system on a chip (PSOC), a field programmable gate array (FPGA), a microprocessor, a microcontroller, a programmable logic controller, or any other suitable processing device or apparatus. The memory portion can be any one or more of a variety of types of internal and/or external storage media such as, without limitation, RAM, ROM, EPROM(s), EEPROM(s), FLASH, and the like that provide a storage register, i.e., a non-transitory machine readable medium, for data and program code storage such as in the fashion of an internal storage area of a computer, and can be volatile memory or nonvolatile memory.
As used herein, the term “parse” means to convert a decoded binary signal into a predetermined format and/or structure for use by a downstream receiving device, wherein the predetermined format and/or structure is based upon the configuration and/or rules of the downstream receiving device.
Referring to
In connection with the isolation function, circuitry 4 may include, for example, and without limitation, an opto-coupler device that provides the isolation functionality by transferring electrical signals between two isolated circuits using light. In connection with the circuit protection functionality, circuitry 4 may include a number of transient voltage suppressor diodes for providing transient voltage suppression functionality for decoder and debugger apparatus 2. With respect to the energy harvesting functionality, in the exemplary embodiment, circuitry 4 is structured to harvest energy from the received IRIG-B signal 6 and output DC power, which harvested DC power is used to provide power for operation of decoder and debugger apparatus 2. In this manner, in the exemplary embodiment, decoder and debugger apparatus 2 does not require a separate on-board or connected battery or other power supply device. In one particular embodiment, circuitry 4 may include a voltage boosting and rectifying circuit, preferably in the form of one or more stage charge pump, for energy harvesting purposes. Charge pumps are well known in the art. Basically, one stage of a charge pump increases the effective amplitude of an AC input voltage with the resulting increased DC voltage appearing on an output capacitor. Successive stages of a charge pump, if present, will essentially increase the voltage from the previous stage resulting in an increased output voltage. As seen in
Decoder and debugger apparatus 2 further includes a controller 12. Controller 12 is coupled to circuitry 4 such that is structured and configured to receive power signal 8 and conditioned IRIG-B signal 10. As described in greater detail herein, controller 12 is provided with a number of routines that receive the conditioned IRIG-B signal 10, and decode and parse the conditioned IRIG-B signal 10 and thereby generate a parsed signal 16, which, as described herein, may be in machine readable and/or human readable (i.e., text) form. Parsed signal 16 may then, as described in more detail herein, be output by decoder and debugger apparatus 2 in a suitable format to a downstream device for use thereby for data correlation with time and/or used for debugging purposes.
Controller 12 further outputs a one-pulse-per-second (PPS) signal 17 synchronized to the unconditioned IRIG-B signal 6 by compensating for any delay circuitry 4 may have introduced conditioning the signal. This PPS signal is suitable for a downstream device for use thereby for highly accurate time synchronization purposes.
As seen in
Energy harvesting is also possible on communications interface 14, particularly if there is a desire to diagnose signal tension levels.
As seen in
The exemplary embodiment of decoder and debugger apparatus 2 shown in
The operation of decoder and debugger apparatus 2 will now be described in more detail. First, as described elsewhere herein, IRIG-B signal 6 is received by circuitry 4. Upon receipt of IRIG-B signal 6, circuitry 4 conditions that signal and outputs conditioned IRIG-B signal 10. In addition, circuitry 4 will harvest DC energy from the received IRIG-B signal 6 and generate DC power signal 8. As described elsewhere herein, DC power signal 8 is used to provide operating power for decoder and debugger apparatus 2.
Moreover, controller 12, in response to receiving the conditioned IRIG-B signal 10, will decode and parse that signal to produce and output parsed signal 16. This decoding and parsing operation is illustrated in more detail in
According to one non-limiting, exemplary embodiment, controller 12 is structured to perform decoding and parsing simultaneously (i.e., in parallel).
In addition, controller 12 is structured and configured to control status LED 24 such that it will be lit each time that a frame of IRIG-B signal 6 is decoded and parsed as just described. Thus, in the exemplary embodiment using IRIG-B signal 6, status LED 24 will be caused to be lit once every second because IRIG-B time codes have a 1 Hz frame rate.
While specific embodiments of the disclosed concept have been described in detail, it will be appreciated by those skilled in the art that various modifications and alternatives to those details could be developed in light of the overall teachings of the disclosure. Accordingly, the particular arrangements disclosed are meant to be illustrative only and not limiting as to the scope of the disclosed concept which is to be given the full breadth of the claims appended and any and all equivalents thereof.
Claims
1. (canceled)
2. The time code signal decoder and debugger apparatus according to claim 9, wherein the encoded time code signal is an Inter-Range Instrumentation Group signal.
3. The time code signal decoder and debugger apparatus according to claim 2, wherein the encoded time code signal is an Inter-Range Instrumentation Group-B signal.
4. The time code signal decoder and debugger apparatus according to claim 9, wherein the parsed signal is a parsed machine-readable signal.
5. The time code signal decoder and debugger apparatus according to claim 9, wherein the parsed signal is a parsed text signal.
6. The time code signal decoder and debugger apparatus according to claim 9, further comprising a display coupled to the controller, the display being structured to receive and visually display the parsed signal, in whole or in part.
7. The time code signal decoder and debugger apparatus according to claim 9, wherein the communications interface comprises one of a serial interface and a wireless interface.
8. The time code signal decoder and debugger apparatus according to claim 7, wherein the serial interface is a USB interface and wherein the time code signal decoder and debugger apparatus receives power through the USB interface.
9. A time code signal decoder and debugger apparatus, comprising:
- a controller structured and configured to: receive an encoded time code signal, decode the encoded time code signal, and produce a parsed signal based on the decoding of the encoded time code signal;
- a communications interface coupled to the controller, wherein the communications interface is structured to receive the parsed signal and generate an output signal based on the parsed signal; and
- circuitry structured to receive an input encoded time code signal, wherein the circuitry includes: energy harvesting circuitry structured to generate DC power for powering the time code signal decoder and debugger apparatus from the input encoded time code signal, and signal conditioning circuitry structured to generate the encoded time code signal from the input encoded time code signal.
10. The time code signal decoder and debugger apparatus according to claim 9, further comprising a status indicator, wherein the encoded time code signal includes a plurality of frames and wherein the status indicator is structured to output a signal each time a frame of the encoded time code signal is decoded and parsed.
11. (canceled)
12. The method according to claim 18, wherein the encoded time code signal is an Inter-Range Instrumentation Group signal.
13. The method according to claim 12, wherein the encoded time code signal is an Inter-Range Instrumentation Group-B signal.
14. The method according to claim 18, wherein the parsed signal is a parsed machine-readable signal.
15. The method according to claim 18, wherein the parsed signal is a parsed text signal.
16. The method according to claim 18, further visually displaying the parsed signal from the apparatus.
17. The method according to claim 18, further comprising providing power to the apparatus through the communications interface.
18. A method of processing an encoded time code signal, comprising:
- receiving the encoded time code signal in an apparatus including a housing that houses a controller and a communications interface coupled to the controller;
- decoding the encoded time code signal within the apparatus;
- producing a parsed signal based on the decoding of the encoded time code signal within the apparatus;
- generating in and transmitting from the apparatus an output signal based on the parsed signal; receiving an input encoded time code signal, generating DC power for powering the apparatus by harvesting energy from the input encoded time code signal, and generating the encoded time code signal from the input encoded time code signal.
19. The method according to claim 18, wherein the encoded time code signal includes a plurality of frames, the method further comprising generating and outputting from the apparatus a status signal each time a frame of the encoded time code signal is decoded and parsed.
Type: Application
Filed: Nov 1, 2016
Publication Date: May 3, 2018
Applicant: COOPER TECHNOLOGIES COMPANY (Houston, TX)
Inventors: ALAIN PICOTTE (LEVIS), RONALD LANDHEER (QUEBEC), HUGUES BILODEAU (QUEBEC)
Application Number: 15/340,591