DYNAMIC CALIBRATION FOR TRANSCEIVERS
The present disclosure relates to a method and system for calibrating transceivers by providing a stored index that was calculated of a race condition count. The race condition is based at least in part to a rat race between a clock signal and an input signal that has been sampled by a random or jitter signal. The stored index corresponds to a relative timing error between the clock signal and the sampled input signal. The stored index is used to scramble subsequent input signals that are thermo-coded signals, thereby eliminating timing errors.
The present disclosure generally relates to modem technology and, in particular, to dynamic calibration of transceivers using novel integrated circuits and algorithms.
BACKGROUNDA network for communications, including for cable television, phone, and internet traffic, typically includes a base station, one or more head-ends, one or more intermediate hubs, and the subscriber facilities. The subscriber facilities typically represent the end of the line and include one or more modems, routers, and other consuming technology—such as, phones, televisions, computers, laptops, electronic tablets, smartphones, InternetOfThings (IoT) devices, and other internet-enabled devices.
Communications and related networks, such as the networks described above, utilize one or more devices to communicate data in various forms. In an example of the cable television network, the subscriber side may include transmitting and receiving components—including a modem, a router, and other related equipment. Many of these devices rely on calibration for transmitting signals at high speed and in a seamless manner, via one or more protocols.
Typical calibration techniques attempt to calibrate systems using random prediction and compensation for the timing errors. Techniques that sense timing errors among switches and clock signals use the random calibration techniques, but encounter complexities due to the nature of the timing errors. Pertinently, timing errors in present networks are random and nondeterministic.
SUMMARYThe present disclosure resolves deficiencies in typical processes for dynamic calibration of transceivers in a communications network. Pertinently, the present disclosure relates to calibrating transceivers and associated digital to analog converters (DACs) by providing a stored index, which was calculated of a race condition count. The stored index is used to scramble subsequent input signals that are thermo-coded signals. The race condition is based at least in part to statistical analysis of a rat race between a clock signal and an input signal that has been sampled by a random or a generated jitter signal over a period of time. The stored index corresponds to a relative timing error between the clock signal and the sampled input signal.
In one aspect, the present disclosure is to a method for calibrating a transceiver. The method includes providing a jitter signal to the transceiver. A sampling is performed for an input signal in accordance with the jitter signal to provide sampled input signals. A receiving step is applied at each of a number of electronic elements in a circuit to receive one of the sampled input signals and a clock signal. A determining function is conducted, for each of the plurality of electronic elements, to determine that a rare condition exists between the one sampled input signal and the clock signal. Revision is applied to a count value in accordance with the determination of the race condition for each of the plurality of electronic elements. A calculation is applied, from the count value for each of the plurality of electronic elements, to determine a relative timing error between the respective sampled input signals and the clock signal. A scrambling is performed for the output signals from each of the electronic elements to provide calibrated versions of the sampled input signals. Pertinently, each scrambled output signal corresponds to each sampled input signals and the scrambling is in accordance with an index corresponding to the relative timing error. The index is stored for use with subsequent input signals, thereby calibrating the transceiver.
In another aspect of the present disclosure, a transceiver circuit is disclosed. The transceiver circuit includes a signal generator for providing a jitter signal and a sampler circuit for sampling an input signal in accordance with the jitter signal to provide sampled input signals. A number of electronic elements of the transceiver circuit are provided for receiving one of the sampled input signals and a clock signal. A sensor circuit is provided for determining that a race condition exists between the one sampled input signal and the clock signal for each of the electronic element. The sensor circuit is also for revising a count value in accordance with the determination of the race condition. Further, the sensor circuit provides configuration for calculating, from the count value for each of the electronic elements, a relative timing error between the respective sampled input signals and the clock signal. A scrambler circuit is provided for scrambling output signals from each of the electronic elements to provide calibrated versions of the sampled input signals. Pertinently, each scrambled output signal corresponds to each sampled input signals and the scrambling is in accordance with an index corresponding to the relative timing error. The transceiver circuit stores the index for use with subsequent input signals, thereby calibrating the transceiver.
The accompanying drawings constitute a part of this specification and, together with the specification, illustrate certain exemplary implementations of this disclosure.
Systems and methods in accordance with various embodiments of the present disclosure overcome one or more of the aforementioned and other deficiencies experienced in conventional approaches to calibrate transceivers in communication networks. Embodiments herein provide a method for transceiver calibration using deterministic and statistical methods with a pre-calibration process. Pertinently, the disclosure herein configures components of a transceiver circuit to perform functions that calibrate the transceiver circuit. Typical components configured in the transceiver circuit of the present disclosure include a digital to analog converter (DAC), in one aspect.
The present disclosure, in one example, is applicable in upstream telecommunications for terrestrial, satellite, or cable television. The calibration method and system disclosed herein enables high performance in current-steering for DACs, in one aspect. The performance of a system incorporating the present disclosure may be evaluated using a signal-to-noise-and-distortion ratio (SNDR), which relies on a statistically equi-probable random sampling of a race condition between the clock signal and the input data. In the cable television network, a television tuner includes paths for downstream data, referring to the capture and display of cable/satellite signal, and to upstream data, referring to the communication and transmission of information from customers to the service providers.
In one example, the present disclosure is applied to the DAC component of an upstream cable television path. The upstream path may be implemented in accordance with a Data Over Cable Service Interface Specification standard, also referred to as the DOCSIS standard. The DOCSIS standard implements high quality and high speed DAC to convert fast digital signal to its analog counterpart. Design of high quality and high speed DAC, of the present disclosure, accounts for low performance of DACs from current-source cell mismatch (also referred to as a static error), timing errors (also referred to as dynamic errors), low output impedance of the current sources, process errors, voltage supply errors, temperature variations, clock feed-through errors, among other related errors. In order to mitigate the impact of these factors on the performance of DAC, several constituent calibration techniques are incorporated herein—including pre-calibration, dynamic calibration, and static calibration.
The calibration techniques of the present disclosure can be categorized into background and foreground calibration techniques to distinguish when the correction occurs—either in the beginning or during the operation of DAC, respectively. The present disclosure is applicable to both, static and dynamic errors, and resolves these errors significantly in a background calibration manner.
A DAC circuit typically includes multiple switch components, such as flip-flops or registers, which are also referred to herein as electronic elements. The switch components may be subject to time mismatch issues when switching to provide the analog output signals of the DAC, based on the digital input signals. The mismatch may be a time delay resulting in erroneous analog output. For example, a digital input using binary form <00 . . . 10> may cause a large analog output as a result of a slight delay when the digital input is applied in parallel across multiple switches. In a current-based DAC, this slight delay in digital input between switches may result in a high current output and, thereby, incorrect conversion from the digital signal. Accordingly, small timing delays severely limit the speed of the DAC. The faster the switching, therefore, the higher is the possibility of a mismatch.
The present disclosure is capable of detecting timing errors in the scale of sub-pico-seconds, and is capable of reducing its impact on the performance of high quality, high speed current steering DACs. The present disclosure also targets the static errors and compensates them by using a current mode analog to digital converter (ADC) as optional parts of the DAC system. The ADC is controlled by a successive approximation algorithm, which is capable of compensating the static errors efficiently. In one aspect, the present disclosure utilizes a random or jitter signal, which may be generated as a noise-like signal, also referred to herein as an artificial-jitter, a jitter, or jitter signal. A jitter is typically a deviation from a periodic signal. A random jitter is a random deviation using a random seed value input, while a uniform jitter is a predefined deviation. Using this artificial-jitter, a randomly sampled set of input signals are modified, and a count is performed for a result of a rat race between the clock and the randomly sampled input signals. The rat race is also referred to herein as a race condition, in which two signals expected at a circuit point at a concurrent time, instead, arrive with a time variations. The time variations can cause output variations as a result, in the case of a signal converter, such as the DAC. The count for the rat race between the clock and the randomly sampled input signals provides results that are compared in a predetermined time interval. The information gleaned from the comparison is then applied to calibrate the circuit at issue. The present disclosure is capable of detecting sub-100 femto-second timing errors.
The present disclosure is applied in an optional two-step process, with each step available independently or combined, as required. The two-step process also addresses static mismatch among the cells in the DAC architecture, in one aspect. For example, the two-step process utilizes a statistical algorithm to predict and reduce the dynamic errors, including delay errors, in one aspect.
The subscriber facilities 105 include modems and, optionally, routers, both of which may be wired or wireless type devices. The upstream and downstream signals from cable 115 transmit digital signals carrying data for voice, telephony, television, and other services, over radio frequency (RF) carrier signals to the modern. In a two-way communication network, one or more carrier signals are designated to transmit data in the downstream direction, from the head-end to the modem at a subscriber facility 105, while other carrier signals are designated to transmit data in the upstream direction, from the subscriber facility 105 to upstream components in the communications network 100, e.g., the head-end 110, and subsequently, the base station 130. The modems at each subscriber facility 105 convert the data as required for the upstream or downstream transmission—for e.g., from a digital format to a RF modulated signals in the upstream direction into the communications network 100, and from RF signals to digital format for the downstream direction consuming devices. A cable modem termination system (CMTS) performs the opposite operation for multiple subscribers at the cable operator's head-end.
The downstream and upstream transmissions can occur in, for example, a 6 MHz bandwidth channel. As described above, the downstream portion is designated to a predetermined portion of the available bandwidth, with the upstream portion designated to the remainder. Moreover, subscriber facilities that are condominium-styled facilities are designated to share bandwidth from singular cables, in some instances. The use of converter circuits, including DAC and ADC circuits, are prevalent in these networks and fast switching enables improved performance and speed with respect to signaling through these circuits.
The DAC disclosure of
In a DAC, the signal path through the converter may be randomized in order to remove mismatch errors from the DAC weights using binary signals. As thermometer coded DAC uses equal weights, it may be suitable in the present implementation so long as the timing is resolved by the stored index for calibration. Pertinently, as all bits of the thermometer coded DAC are weighted equally, the randomization does not affect the output; instead, multiple combinations of thermometer code may represent the same binary value and provide the same output. The calibration index stored in the present disclosure enables the use of required weights assigned to the thermometer code at different instances of time to enable a matched output. The scrambler chip enables such an application for the calibrated system herein.
The various embodiments can be implemented in a wide variety of operating environments, which in some cases can include one or more user electronic devices, integrated circuits, chips, and computing devices—each with the proper configuration of hardware, software, and/or firmware as presently disclosed. Such a system can also include a number of the above exemplary systems working together to perform the same function disclosed herein—to dynamically calibrate transceivers using novel integrated circuits and algorithms.
Most embodiments utilize at least one communications network that would be familiar to those skilled in the art for supporting communications using any of a variety of commercially-available protocols, such as TCP/IP, FTP, UPnP, NFS, and CIFS. The communications network can be, for example, a cable network, a local area network, a wide-area network, a virtual private network, the Internet, an intranet, an extranet, a public switched telephone network, an infrared network, a wireless network and any combination thereof.
The environment can include a variety of data stores and other memory and storage media as discussed above—including at least a buffer. These storage components can reside in a variety of locations, such as on a storage medium local to (and/or resident in) one or more of the computers or remote from any or all of the computers across the network. In a particular set of embodiments, the information may reside in a storage-area network (SAN) familiar to those skilled in the art. Similarly, any necessary files for performing the functions attributed to the computers, servers or other network devices may be stored locally and/or remotely, as appropriate. Where a system includes computerized devices, each such device can include hardware elements that may be electrically coupled via a bus, the elements including, for example, at least one central processing unit (CPU), at least one input device (e.g., a mouse, keyboard, controller, touch-sensitive display element or keypad) and at least one output device (e.g., a display device, printer or speaker). Such a system may also include one or more storage devices, such as disk drives, optical storage devices and solid-state storage devices such as random access memory (RAM) or read-only memory (ROM), as well as removable media devices, memory cards, flash cards, etc.
Such devices can also include a computer-readable storage media reader, a communications device (e.g., a modem, a network card (wireless or wired), an infrared communication device) and working memory as described above. The computer-readable storage media reader can be connected with, or configured to receive, a computer-readable storage medium representing remote, local, fixed and/or removable storage devices as well as storage media for temporarily and/or more permanently containing, storing, transmitting and retrieving computer-readable information. The system and various devices also typically will include a number of software applications, modules, services or other elements located within at least one working memory device, including an operating system and application programs such as a client application or Web browser. It should be appreciated that alternate embodiments may have numerous variations from that described above. For example, customized hardware might also be used and/or particular elements might be implemented in hardware, software (including portable software, such as applets) or both. Further, connection to other computing devices such as network input/output devices may be employed.
Storage media and other non-transitory computer readable media for containing code, or portions of code, can include any appropriate media known or used in the art, such as but not limited to volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, including RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices or any other medium which can be used to store the desired information and which can be accessed by a system device. Based on the disclosure and teachings provided herein, a person of ordinary skill in the art will appreciate other ways and/or methods to implement the various embodiments.
The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that various modifications and changes may be made thereunto without departing from the broader spirit and scope of the invention as set forth in the claims.
Claims
1. A method for calibration of a transceiver comprising:
- providing a jitter signal to the transceiver;
- sampling an input signal in accordance with the jitter signal to provide a sampled input signal;
- receiving, at an electronic element in the transceiver, the sampled input signal and a clock signal;
- determining that a race condition exists between the sampled input signal and the clock signal;
- revising a count value in accordance with the determination of the race condition;
- calculating, from the count value, a relative timing error between the sampled input signal and the clock signal; and
- scrambling an output signal from the electronic element to provide scrambled output signal, the scrambling in accordance with an index corresponding to the relative timing error, the index stored for use with subsequent input signals to the transceiver.
2. The method of claim 1, wherein the providing for the jitter signal is by a signal generator that is configured to add randomness to the clock signal using a seed number input from a register.
3. The method of claim 1, wherein the providing for the jitter signal is by a signal generator that is configured to add noise to the clock signal using a linear feedback shift register (LFSR).
4. The method of claim 1, wherein the determination of the race condition is performed by a comparison of receipt times of edges of the sampled input signal and the clock signal, and the comparison occurring when the sampled input signal and the clock signal are active in a predetermined time interval.
5. The method of claim 4, wherein the determination of the race condition further comprises using a sub-pico second difference in the comparison of the receipt times of the edges of the sampled input signal and the clock signal.
6. The method of claim 1, wherein the electronic element is one among flip-flops or registers.
7. The method of claim 1, wherein the sampled input signal and the output signal are thermometer-coded signals.
8. The method of claim 1, wherein the index maps the sampled input signal and the output signal.
9. The method of claim 1, wherein the index comprises code for controlling signal selection to output the scrambled output signal.
10. The method of claim 1, further comprising: pre-calibrating of the clock signal and the input signal to synchronize the clock signal and the input signal.
11. A transceiver circuit, comprising:
- a signal generator for providing a jitter signal;
- a sampler circuit for sampling an input signal in accordance with the jitter signal to provide a sampled input signal;
- an electronic element in the transceiver circuit receiving the sampled input signal and a clock signal;
- a sensor circuit for determining that a race condition exists between the sampled input signal and the clock signal;
- the sensor circuit for revising a count value in accordance with the determination of the race condition;
- the sensor circuit for calculating, from the count value, a relative timing error between the respective sampled input signals and the clock signal; and
- a scrambler circuit for scrambling an output signal from the electronic element to provide a scrambled output signal, the scrambling in accordance with an index corresponding to the relative timing error, the index stored for use with subsequent input signals to the transceiver.
12. The transceiver circuit of claim 11, wherein the signal generator is configured to add randomness to the clock signal using a seed number, from a register, for the providing of the jitter signal.
13. The transceiver circuit of claim 11, wherein the signal generator is configured to add noise to the clock signal using a linear feedback shift register (LFSR), for the providing of the jitter signal.
14. The transceiver circuit of claim 11, wherein the sensor circuit is configured for the determining of the race condition by comparing receipt times of edges of the sampled input signal and the clock signal, the comparing performed when the sampled input signal and the clock signal are active in a predetermined time interval.
15. The transceiver circuit of claim 14, wherein the sensor circuit is configured for the comparing of the receipt times using a sub-pico second difference in the receipt times of the edges of the sampled input signal and the clock signal.
16. The transceiver circuit of claim 14, wherein the electronic element is one among flip-flops or registers.
17. The transceiver circuit of claim 14, wherein the sampled input signal and output signal are thermometer-coded signals.
18. The transceiver circuit of claim 14, wherein the index maps the sampled input signals and the output signals.
19. The transceiver circuit of claim 14, wherein the index comprises code for controlling signal selection to output the scrambled output signal.
20. The transceiver circuit of claim 14, further comprising a pre-calibration circuit for pre-calibration of the clock signal and the input signal to synchronize the clock signal and the input signal.
Type: Application
Filed: Feb 22, 2017
Publication Date: Aug 23, 2018
Inventors: Hamid Nejati (San Jose, CA), Vahid M. Toosi (San Jose, CA), Saeid Mehrmanesh (Los Altos, CA), Marzieh Veyseh (Los Altos, CA)
Application Number: 15/439,131