SYSTEM IN PACKAGE PROCESS FLOW
A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.
This application is a divisional of U.S. patent application Ser. No. 13/290,208, filed Nov. 7, 2011, which is incorporated by reference herein in its entirety.
FIELDThis disclosure relates to semiconductor integrated circuits (ICs) and methods for packaging the ICs.
BACKGROUNDAs the semiconductor industry continues to reduce package dimensions, foundries are looking to increase vertical density in addition to horizontal circuit density. 3D packaging saves space by stacking separate chips in a single package. This packaging, known as System in Package (SiP), uses off-chip signaling (e.g., by way of conductive paths in the package substrate) for communication between chips in the package The chips are not integrated into a single circuit. Rather, the chips within in the package communicate as though they are mounted in separate packages on a normal circuit board. For example, both the upper and lower chips may be wire bonded to the package substrate.
This description of the exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. In the description, relative terms such as “lower,” “upper,” “horizontal,” “vertical,”, “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivative thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation. Terms concerning attachments, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise. The drawings are not drawn to scale.
Package substrate 100 has a plurality of conductive patterns and vias, collectively labeled 104, for distributing signals and power between the ICs above and the solder balls 188 below. On the top surface of package substrate 100, a plurality of solder balls or bumps 112 are provided for connections between the package substrate 100 and a substrate 150 (shown in
In
Next, as shown in
Thus,
Although the configuration of
The package substrate 100 and substrate 150 are sized, so that first and second edge portions 101a, 101b of the package substrate 100 extend beyond at least two edges 151a, 151b (shown in
The first upper die package 180 has pads 183 on the first and second abutting edge portions 182 thereof. The first and second edge portions 182 form an L shaped region along two side edges 181a, 181b of the first upper die package 180. In some embodiments, the first upper die package 180 has solder balls 186 on the pads 183. In other embodiments, the first upper die package has pads 183 without solder balls. A second region 184 of the first upper die package 180 has no pads. The second region 184 is adapted to be used as a mounting interface surface.
At least the first upper die package 180 is to be positioned over the substrate 150, so that first and second edge portions 181a, 181b of the first upper die package 180 extend beyond the at least two edges 151a, 151b of the substrate 150. A thermal interface material 160 is positioned between the substrate 150 and the second region 184 of the first upper die package 180. The thermal interface material 160 (optional) may be a soft polymer, such as a polyimide, or air only.
In the final package configuration of
In
In other embodiments (such as shown in
As shown in
At step 702, a substrate 150 having a plurality of integrated circuit (IC) dies 154 800 is connected to a package substrate 100, so that the package substrate 100 extends beyond at least two edges 151a, 151b of the substrate 150, leaving first and second edge portions 101a, 101b of the package substrate having contacts thereon exposed, where the first and second edge portions 101a, 101b meet at a first corner of the package substrate. In the example of
At step 704, a first underfill material 120 is flowed into the space between the package substrate and the substrate 150. The resulting configuration is as shown in
At step 706, as shown in
At step 708, as shown in
At step 710, as shown in
In the example of
At step 712, the pads 183 on the first and second edge portions 181a, 181b of the first upper die package 180 are connected to the contacts 110 of the first and second edge portions 101a, 101b of the package substrate 100. The pads 183 on the third and fourth edge portions 101c, 101d of the second upper die package 180 are connected to the contacts 110 of the third and fourth edge portions 101c, 101d of the package substrate 100. In the method of
At step 714, the assembly is cleaned, for example by flushing with deionized water, to remove any remaining solder paste and/or flux.
At step 716, as shown in
At step 718, solder bumps 188 are applied to the package 100.
In some embodiments, the package is completed at the end of step 2E
In other embodiments, the package 200 is thinned by a planarization process (step 720), to remove the portion of the molding compound 190 above the back faces of the upper die packages 180, as shown in
Although the method of
Thus, step 710 includes placing a third upper die package 180 over the substrate 150, so that fifth and sixth edge portions 181e, 181f of the third upper die package extend beyond the second and third edges 151b, 151c of the substrate; and placing a fourth upper die package over the substrate, so that the seventh and eighth edge portions 181g, 181h of the fourth upper die package extend beyond the first and fourth edges 151a, 151d of the substrate. In this embodiment, step 712 further includes connecting pads on the fifth and sixth edge portions 181e, 181f of the third upper die package to the contacts 110 of the second and third edge portions 101b, 101c of the package substrate; and connecting pads on the seventh and eighth edge portions 181g, 181h of the fourth upper die package to the contacts 110 of the first and fourth edge portions 101a, 101b of the package substrate 100.
In
In
In
In
The assembly shown in
In
In
In
Following application of solder paste, the upper die packages are placed and connected to the assembly as shown and described with reference to
In
In
In
In
In
In
In some embodiments, a method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having contacts thereon exposed. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.
In some embodiments, an integrated circuit (IC) package comprises a substrate having a plurality of IC dies connected to a package substrate, so that first and second edge portions of the package substrate extend beyond at least two edges of the substrate. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is positioned over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. The first upper die package has pads on the first and second edge portions thereof. The pads are connected to the contacts of the first and second edge portions of the package substrate by solder.
In some embodiments, an integrated circuit (IC) package comprises a substrate having a plurality of IC dies connected to a package substrate, so that four edge portions of the package substrate having contacts thereon extend beyond respective edges of the substrate. Each pair of adjacent edge portions meet at a respective corner of the package substrate. A plurality of upper die packages are positioned so as to partially overlie the substrate, so that first and second edge portions of each upper die package extend beyond a respective pair of adjacent edges of the substrate. The plurality of upper die packages have pads on the first and second edge portions thereof. The pads are connected to respective ones of the contacts of the package substrate by solder. A thermal interface material is provided between the substrate and the plurality of upper die packages.
In some embodiments, an integrated circuit (IC) package comprises a substrate having a plurality of bottom dies connected to the substrate, so that first and second connecting portions of the substrate extend beyond at least two edges of each bottom die, the first and second connecting portions meeting at a first corner of each bottom die. at least a first upper die package is positioned over at least one of the bottom dies, so that first and second edge portions of the first upper die package extend beyond the at least two edges of at least one of the bottom dies. The first upper die package has pads on the first and second edge portions thereof. The pads are connected to the contacts of the first and second connecting portions of the substrate by solder.
Although the subject matter has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly, to include other variants and embodiments, which may be made by those skilled in the art.
Claims
1. A method comprising:
- (a) connecting an integrated circuit (IC) die to a substrate, wherein the substrate comprises a first substrate edge portion, a second substrate edge portion, a third substrate edge portion, and a fourth substrate edge portion, wherein the first substrate edge portion and the second substrate edge portion meet at a first corner of the substrate adjacent to a first corner of the IC die, and wherein the third substrate edge portion and the fourth substrate edge portion meet at a second corner of the substrate adjacent to a second corner of the IC die;
- (b) placing a first upper die package having a first upper die edge portion and a second upper die edge portion over the IC die, so as to cover and extend beyond the first corner of the IC die;
- (c) connecting pads on the first upper die edge portion and the second upper die edge portion to contacts of the first substrate edge portion and the second substrate edge portion;
- (d) placing a second upper die package having a third upper die edge portion and a fourth upper die edge portion over the IC die that is partially overlaid by the first upper die package, so as to cover and extend beyond the second corner of the IC die; and
- (e) connecting pads on the third upper die edge portion and the fourth upper die edge portion to contacts of the third substrate edge portion and the fourth substrate edge portion.
2. The method of claim 1, wherein the second upper die package is located diagonally from the first upper die package, and wherein the first upper die package and the second upper die package are spaced apart so that neither lies over the other.
3. The method of claim 1, the method further comprising:
- depositing a solder paste on the contacts of the first substrate edge portion and the second substrate edge portion before step (c).
4. The method of claim 1, further comprising:
- placing solder on the contacts of the first substrate edge portion and the second substrate edge portion; and
- depositing a solder paste on the solder before step (c).
5. The method of claim 4, wherein the solder is placed on the contacts of the first substrate edge portion and the second substrate edge portion after step (a).
6. The method of claim 1, further comprising placing solder on the contacts of the first substrate edge portion and the second substrate edge portion before step (a).
7. The method of claim 5, further comprising
- applying a molded underfill material around the solder and above the first upper die package.
8. The method of claim 7, wherein an underfill material is deposited between the IC die and the substrate, between steps (a) and (b).
9. The method of claim 8, further comprising depositing a first underfill material between the IC die and the substrate, before applying the molded underfill material around the solder.
10. The method of claim 1, further comprising:
- placing a thermal interface material over the IC die before step (b).
11. A method comprising:
- (a) connecting at an integrated circuit (IC) die to a substrate, so that a first substrate edge portion, a second substrate edge portion, a third substrate edge portion, and a fourth substrate edge portion of the substrate having contacts thereon extend beyond four edges of the IC die;
- (b) placing a first upper die package over the IC die, with the IC die located between the first upper die package and the substrate,
- (c) placing a second upper die package over the IC die, the first upper die package and the second upper die package positioned diagonally from each other in a plane and spaced apart so that neither the first upper die package and the second upper die package lies over the other;
- (d) connecting pads on a first upper die edge portion and a second upper die edge portion of the first upper die package directly to the contacts of the first substrate edge portion and the second substrate edge portion; and
- (e) connecting pads on a third upper die edge portion and a fourth upper die edge portion of the second upper die package to the contacts of the third substrate edge portion and the fourth substrate edge portion.
12. The method of claim 11, wherein step (a) includes connecting the IC die to the substrate using solder, the method further comprising applying a first underfill material around the solder, between steps (a) and (b).
13. The method of claim 12, wherein the step of applying the first underfill material includes depositing the first underfill material between the IC die and the substrate.
14. The method of claim 11, further comprising placing a thermal interface material over the IC die before step (b).
15. A method comprising:
- (a) flip chip mounting an integrated circuit (IC) die over a substrate, wherein the substrate comprises a first substrate edge portion, a second substrate edge portion, a third substrate edge portion, and a fourth substrate edge portion;
- (b) placing a first upper die package over the IC die, so as to cover and extend beyond a first IC die corner of the IC die,
- (c) connecting pads on a first upper die portion and a second upper die edge portion of the first upper die package to contacts of the first substrate edge portion and the second substrate edge portion;
- (d) placing a second upper die package over the substrate that is partially overlaid by the first upper die package, so as to cover and extend beyond a second corner of the IC die; and
- (e) connecting pads on a third upper die edge portion and a fourth upper die edge portion of the second upper die package to contacts on the third substrate edge portion and the fourth substrate edge portion.
16. The method of claim 15, wherein the first upper die package and the second upper die package are positioned diagonally from each other and spaced apart so that neither lies over the other.
17. The method of claim 15, wherein step (a) includes connecting the IC die to the substrate using solder, the method further comprising applying a first underfill material around the solder, between steps (a) and (b), wherein the step of applying the first underfill material includes depositing the first underfill material between the IC die and the substrate.
18. The method of claim 15, wherein the first upper die package and the second upper die package includes two different dies from the group consisting of a general purpose processor, a graphics processor, an audio/video processor, a digital radio receiver, DRAM, SRAM, or flash memory, a communications processor, a global positioning satellite (GPS) receiver, and a power management unit.
19. The method of claim 15, wherein the first upper die package and the second upper die package are wafer level chip scale packages.
20. The method of claim 15, further comprising thinning back surfaces of the first upper die package and the second upper die package after step (e).
Type: Application
Filed: Aug 9, 2018
Publication Date: Dec 6, 2018
Inventors: Tsing-Ding WANG (Tainan City), Chien-Hsiun Lee (Hsin-chu)
Application Number: 16/100,060