Pulse Filtering Circuit
The present disclosure provides a pulse filtering circuit with two input ports and two output ports, including: a first signal path with a first buffer unit, a first comparison unit, and a first shaping unit; and a second signal path with a second buffer unit, a second comparison unit, and a second shaping unit; each of the first comparison unit and the second comparison unit has four ports, which are a first port, a second port, a third port and a fourth port; the first port of each comparison unit serves as an input control port, the second port of each comparison unit serves as an output port, the third port serves as a fixed potential port, and the fourth port serves as a floating potential input port. The new pulse filtering circuit of the present disclosure may eliminate the common-mode noise signal, especially the dV/dt common-mode noise generated by the power supply, and therefore the circuit has a strong anti-dV/dt noise capability and a small transmission delay, and at the same time reduces the chip area and production costs due to its simple circuit structure.
The present disclosure relates to a circuit with a high voltage driving technology, and more particularly to a new pulse filtering circuit of a high voltage floating gate driver circuit with high noise immunity, which belongs to the field of integrated circuits.
BACKGROUNDAs shown in
The high side gate driver circuit 101 is often used to drive a high-side switching device in a half-bridge structure, while a low-side switching device in the half-bridge structure is driven by a low side gate driver circuit 102. A basic topology of the half-bridge structure is shown in
In order to improve utilization efficiency of a power supply, the half-bridge driving circuit 100 adopts a single power supply mode, low/medium voltage circuits in the low side gate driver circuit 102 and the high side gate driver circuit 101 are powered by the low-side fixed power supply VCC, and a high voltage circuit in the high side gate driver circuit 101 is powered by VCC through a bootstrap diode DB and a bootstrap capacitor CB. A power supply voltage VB of the high voltage circuit in the high side gate driver circuit 101 and a reference ground VS are floating voltages. When the output signal HO of the high side gate driver circuit 101 is a high level VB and the output signal LO of the low side gate driver circuit 102 is a low level COM, the high-side power switching device MH is turned on, the low-side power switching device ML is turned off, the VS voltage increases, and the VB voltage also increases with the increase of the VS voltage; on the contrary, when the HO is at the low level and the LO is at the high level, MH is turned off, ML is turned on, and the VS voltage and the VB voltage are dropped. In order to reduce power consumption and improve reliability of the circuit, a mode of controlling the high voltage power switching device by double narrow pulses is often adopted in the high side gate driver circuit 101 to realize a high voltage level shift, that is, the high-side input signal is converted into two narrow pulses which represent a rising edge and a falling edge of the high-side input signal, respectively, thereby greatly reducing the turn-on time of the high voltage power switching device of the high voltage level shifter.
As shown in
A function of the narrow pulse generating circuit 200 is to convert the high-side input signal HIN into two narrow pulses, which represent the rising edge and the falling edge of the high-side input signal HIN, respectively, and are used to drive the high voltage power switching devices M1, M2. The high voltage level shift circuit 201 includes the high voltage switching devices M1 and M2, load resistors RL1 and RL2, and zener diodes Z1 and Z2. The function of the high voltage level shift circuit 201 is to convert pulse signals SET and RESET of the low/medium voltage circuit into signals VDS and VDR of the high voltage circuit, respectively.
As shown in
A conventional method to solve the dV/dt noise is to adopt a RC filtering form. As shown in
Therefore, the related art is still needed to be improved and developed.
SUMMARYIn order to solve the problem that anti-dV/dt capability, anti-VS negative bias capability and channel transmission delay cannot be reconciled in the high side gate driver circuit in the related art, a new pulse filtering circuit is provided in embodiments of the present disclosure. A high side gate driver circuit using this pulse filtering circuit has a high anti-dV/dt noise capability, a high anti-VS negative bias capability, and a very small channel transmission delay; in addition, the circuit structure is compact, saving chip area.
The technical solutions adopted by the present disclosure are as follows.
A pulse filtering circuit with two input ports and two output ports includes:
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- a first signal path with a first buffer unit, a first comparison unit, and a first shaping unit; and
- a second signal path with a second buffer unit, a second comparison unit, and a second shaping unit;
- each of the buffer unit includes one or more digital inverters in series, with the input to the first digital inverter serving as the input to the pulse filtering circuit, and an output of the last digital inverter serving as an output of the buffer unit, optionally such buffer unit can be omitted; and
- each of the first comparison unit and the second comparison unit has four ports, which are a first port, a second port, a third port and a fourth port;
- the first port of each comparison unit serves as an input control port, the second port of each comparison unit serves as an output port, the third port serves as a fixed potential port, and the fourth port serves as a floating potential input port; and
- the output of the first buffer unit connects to the input control port of the first comparison unit and the floating potential input port of the second comparison unit, the output of the second buffer unit connects to the input control port of the second comparison unit and the floating potential input port of the first comparison unit, or alternatively the output of the first buffer unit connects to the input control port of the second comparison unit and the floating potential input port of the first comparison unit, the output of the second buffer unit connects to the input control port of the first comparison unit and the floating potential input port of the second comparison unit; and
- signal from each of the floating potential input port is passed to the corresponding output port when a voltage difference between the corresponding input control port and the floating potential input port exceeds a voltage threshold of the comparison unit, otherwise the corresponding output port provides an output equal to the fixed potential at the third port; and
- the first shaping unit includes one or more digital inverters in series, with an input to the first digital inverter connecting to the output of the first comparison unit, and an output of the last digital inverter serving as a first output of the pulse filtering circuit, and the second shaping unit includes one or more digital inverters in series, with an input to the first digital inverter connecting to the output of the second comparison unit, and an output of the last digital inverter serving as a second output of the pulse filtering circuit; optionally, each such buffer unit can be omitted.
In the pulse filtering circuit, the third port of the first comparison unit and the third port of the second comparison unit are connected with a power supply signal or a ground signal; and the first comparison unit and the second comparison unit each include one or more digital inverters.
In the pulse filtering circuit, the first buffer unit comprises a first digital inverter, and the second buffer unit comprises a second digital inverter.
In the pulse filtering circuit, the first comparison unit comprises a first PMOS transistor and a first NMOS transistor, a gate electrode of the first PMOS transistor and a gate electrode of the first NMOS transistor are connected together to serve as the first port of the first comparison unit, a drain electrode of the first PMOS transistor and a drain electrode of the first NMOS transistor are connected together to serve as the second port of the first comparison unit, a source electrode of the first PMOS transistor serves as the third port of the first comparison unit, and a source electrode of the first NMOS transistor serves as the fourth port of the first comparison unit.
In the pulse filtering circuit, the second comparison unit comprises a second PMOS transistor and a second NMOS transistor, a gate electrode of the second PMOS transistor and a gate electrode of the second NMOS transistor are connected together to serve as the first port of the second comparison unit, a drain electrode of the second PMOS transistor and a drain electrode of the second NMOS transistor are connected together to serve as the second port of the second comparison unit, a source electrode of the second PMOS transistor serves as the third port of the second comparison unit, and a source electrode of the second NMOS transistor serves as the fourth port of the second comparison unit.
In the pulse filtering circuit, the first shaping unit comprises a third digital inverter and a fourth digital inverter, the second shaping unit consists of a fifth digital inverter and a sixth digital inverter; the third port of the first comparison unit and that of the second comparison unit are connected with the power supply signal; and signals at output ends
In the pulse filtering circuit, the first buffer unit comprises a seventh digital inverter and an eighth digital inverter, and the second buffer unit comprises a ninth digital inverter and a tenth digital inverter.
In the pulse filtering circuit, the first comparison unit comprises a third PMOS transistor and a third NMOS transistor, a gate electrode of the third PMOS transistor and a gate electrode of the third NMOS transistor are connected together to serve as the first port of the first comparison unit, a drain electrode of the third PMOS transistor and a drain electrode of the third NMOS transistor are connected together to serve as the second port of the first comparison unit, a source electrode of the third PMOS transistor serves as the third port of the first comparison unit, and a source electrode of the third NMOS transistor serves as the fourth port of the first comparison unit.
In the pulse filtering circuit, the second comparison unit comprises a fourth PMOS transistor and a fourth NMOS transistor, a gate electrode of the fourth PMOS transistor and a gate electrode of the fourth NMOS transistor are connected together to serve as the first port of the second comparison unit, a drain electrode of the fourth PMOS transistor and a drain electrode of the fourth NMOS transistor are connected together to serve as the second port of the second comparison unit, a source electrode of the fourth PMOS transistor serves as the third port of the second comparison unit, and a source electrode of the fourth NMOS transistor serves as the fourth port of the second comparison unit.
In the pulse filtering circuit, the first shaping unit comprises an eleventh digital inverter, and the second shaping unit comprises a twelfth digital inverter; the third port of the first comparison unit and the third port of the second comparison unit are connected with the ground signal; and signals at output ends
Compared with the related art, the technical solutions adopted in embodiments of the present disclosure have the following advantages and remarkable effects:
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- (1) The present disclosure overcomes contradictions among anti-dV/dt noise capability, anti-VS negative bias capability and channel transmission delay of the high side gate driver circuit, thus greatly improving the anti-dV/dt noise capability and anti-VS negative bias capability of the high side gate driver circuit;
- (2) The present disclosure avoids the use of an R (resistor) C (capacitor) filtering circuit structure, thereby reducing the delay of the circuit channel and improving the signal response speed;
- (3) The present disclosure allows a certain process deviation, and the dV/dt noise may not affect the high-side output signal, thereby further improving the anti-dV/dt noise capability and the reliability of the circuit; and
- (4) The circuit of the present disclosure has a simple structure and occupies a small chip area.
The preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
As shown in
As shown in
The second comparison unit 403 comprises a second PMOS transistor 504 and a second NMOS transistor 505. A gate electrode of the second PMOS transistor 504 and a gate electrode of the second NMOS transistor 505 are connected together to serve as the first port of the second comparison unit 403, a drain electrode of the second PMOS transistor 504 and a drain electrode of the second NMOS transistor 505 are connected together to serve as the second port of the second comparison unit 403, a source electrode of the second PMOS transistor 504 serves as the third port of the second comparison unit 403, and a source electrode of the second NMOS transistor 505 serves as the fourth port of the second comparison unit 403.
The first shaping unit 404 comprises a third digital inverter 506 and a fourth digital inverter 508. The second shaping unit 405 comprises a fifth digital inverter 507 and a sixth digital inverter 509. The third port of the first comparison unit 402 and that of the second comparison unit 403 are connected with the power supply signal. When an absolute value of a voltage difference between the first port and the fourth port of the first comparison unit 402 or the first port and the fourth port of the second comparison unit 403 is greater than the voltage threshold of the first comparison unit or the voltage threshold of the second comparison unit, signals at output ends
As shown in
The second comparison unit 403 comprises a fourth PMOS transistor 606 and a fourth NMOS transistor 607, a gate electrode of the fourth PMOS transistor 606 and a gate electrode of the fourth NMOS transistor 607 are connected together to serve as the first port of the second comparison unit 403, a drain electrode of the fourth PMOS transistor 606 and a drain electrode of the fourth NMOS transistor 607 are connected together to serve as the second port of the second comparison unit 403, a source electrode of the fourth NMOS transistor 607 serves as the third port of the second comparison unit 403, and a source electrode of the fourth PMOS transistor 606 serves as the fourth port of the second comparison unit 403.
The first shaping unit 404 comprises an eleventh digital inverter 608, and the second shaping unit 405 comprises a twelfth digital inverter 609; the third port of the first comparison unit 402 and the third port of the second comparison unit 403 are connected with the ground signal. Signals at output ends
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The new pulse filtering circuit of the present disclosure may eliminate the common-mode noise signal, especially the dV/dt common-mode noise generated by the power supply. Therefore, the circuit has a strong anti-dV/dt noise capability. In addition, the new pulse filtering circuit has a small transmission delay, at the same time, due to its simple circuit structure, the chip area and production costs are reduced.
It should be understood that the above detailed descriptions of embodiments of the present disclosure are illustrative and shall not be regarded as a limitation to the protection scope of the present disclosure. The protection scope of the present disclosure should be based on the appended claims.
Claims
1. A pulse filtering circuit with two input ports and two output ports comprising:
- a first signal path with a first buffer unit, a first comparison unit, and a first shaping unit; and
- a second signal path with a second buffer unit, a second comparison unit, and a second shaping unit;
- wherein
- each of the buffer unit comprising one or more digital inverters in series, with the input to the first digital inverter serving as the input to the pulse filtering circuit, and an output of the last digital inverter serving as an output of the buffer unit; and
- each of the first comparison unit and the second comparison unit has four ports, which are a first port, a second port, a third port and a fourth port;
- wherein
- the first port of each comparison unit serves as an input control port, the second port of each comparison unit serves as an output port, the third port serves as a fixed potential port, and the fourth port serves as a floating potential input port; and
- the output of the first buffer unit connects to the input control port of the first comparison unit and the floating potential input port of the second comparison unit, the output of the second buffer unit connects to the input control port of the second comparison unit and the floating potential input port of the first comparison unit, or alternatively the output of the first buffer unit connects to the input control port of the second comparison unit and the floating potential input port of the first comparison unit, the output of the second buffer unit connects to the input control port of the first comparison unit and the floating potential input port of the second comparison unit; and
- signal from each of the floating potential input port is passed to the corresponding output port when a voltage difference between the corresponding input control port and the floating potential input port exceeds a voltage threshold of the comparison unit, otherwise the corresponding output port provides an output equal to the fixed potential at the third port; and
- the first shaping unit comprising one or more digital inverters in series, with an input to the first digital inverter connecting to the output of the first comparison unit, and an output of the last digital inverter serving as a first output of the pulse filtering circuit, and the second shaping unit comprising one or more digital inverters in series, with an input to the first digital inverter connecting to the output of the second comparison unit, and an output of the last digital inverter serving as a second output of the pulse filtering circuit.
2. The pulse filtering circuit according to claim 1, wherein the third port of the first comparison unit and the third port of the second comparison unit are connected to a power supply signal or a ground signal; and the first comparison unit and the second comparison unit each comprise one or more digital inverters.
3. The pulse filtering circuit according to claim 2, wherein the first buffer unit comprises a first digital inverter, and the second buffer unit comprises a second digital inverter.
4. The pulse filtering circuit according to claim 3, wherein the first comparison unit comprises a first PMOS transistor and a first NMOS transistor, a gate electrode of the first PMOS transistor and a gate electrode of the first NMOS transistor are connected together to serve as the first port of the first comparison unit, a drain electrode of the first PMOS transistor and a drain electrode of the first NMOS transistor are connected together to serve as the second port of the first comparison unit, a source electrode of the first PMOS transistor serves as the third port of the first comparison unit, and a source electrode of the first NMOS transistor serves as the fourth port of the first comparison unit.
5. The pulse filtering circuit according to claim 4, wherein the second comparison unit comprises a second PMOS transistor and a second NMOS transistor, a gate electrode of the second PMOS transistor and a gate electrode of the second NMOS transistor are connected together to serve as the first port of the second comparison unit, a drain electrode of the second PMOS transistor and a drain electrode of the second NMOS transistor are connected together to serve as the second port of the second comparison unit, a source electrode of the second PMOS transistor serves as the third port of the second comparison unit, and a source electrode of the second NMOS transistor serves as the fourth port of the second comparison unit.
6. The pulse filtering circuit according to claim 5, wherein the first shaping unit comprises a third digital inverter and a fourth digital inverter, the second shaping unit comprises a fifth digital inverter and a sixth digital inverter; the third port of the first comparison unit and that of the second comparison unit are connected to the power supply signal; and signals at output ends S and R are changed when an absolute value of a voltage difference between the first port and the fourth port of the first comparison unit or the first port and the fourth port of the second comparison unit is greater than the voltage threshold of the first comparison unit or the voltage threshold of the second comparison unit.
7. The pulse filtering circuit according to claim 2, wherein the first buffer unit comprises a seventh digital inverter and an eighth digital inverter, and the second buffer unit comprises a ninth digital inverter and a tenth digital inverter.
8. The pulse filtering circuit according to claim 7, wherein the first comparison unit comprises a third PMOS transistor and a third NMOS transistor, a gate electrode of the third PMOS transistor and a gate electrode of the third NMOS transistor are connected together to serve as the first port of the first comparison unit, a drain electrode of the third PMOS transistor and a drain electrode of the third NMOS transistor are connected together to serve as the second port of the first comparison unit, a source electrode of the third PMOS transistor serves as the third port of the first comparison unit, and a source electrode of the third NMOS transistor serves as the fourth port of the first comparison unit.
9. The pulse filtering circuit according to claim 8, wherein the second comparison unit comprises a fourth PMOS transistor and a fourth NMOS transistor, a gate electrode of the fourth PMOS transistor and a gate electrode of the fourth NMOS transistor are connected together to serve as the first port of the second comparison unit, a drain electrode of the fourth PMOS transistor and a drain electrode of the fourth NMOS transistor are connected together to serve as the second port of the second comparison unit, a source electrode of the fourth PMOS transistor serves as the third port of the second comparison unit, and a source electrode of the fourth NMOS transistor serves as the fourth port of the second comparison unit.
10. The pulse filtering circuit according to claim 9, wherein the first shaping unit comprises an eleventh digital inverter, and the second shaping unit comprises a twelfth digital inverter; the third port of the first comparison unit and the third port of the second comparison unit are connected with the ground signal; and signals at output ends S and R are changed when an absolute value of a voltage difference between the first port and the fourth port of the first comparison unit or the first port and the fourth port of the second comparison unit is greater than the voltage threshold of the first comparison unit or the voltage threshold of the second comparison unit.
11. A pulse filtering circuit with two input ports and two output ports comprising:
- a first signal path with a first buffer unit, a first comparison unit, and a first shaping unit; and
- a second signal path with a second buffer unit, a second comparison unit, and a second shaping unit;
- wherein
- each of the buffer unit comprising one or more digital inverters in series, with the input to the first digital inverter serving as the input to the pulse filtering circuit, and an output of the last digital inverter serving as an output of the buffer unit, optionally such buffer unit can be omitted; and
- each of the first comparison unit and the second comparison unit has four ports, which are a first port, a second port, a third port and a fourth port;
- wherein
- the first port of each comparison unit serves as an input control port, the second port of each comparison unit serves as an output port, the third port serves as a fixed potential port, and the fourth port serves as a floating potential input port; and
- the output of the first buffer unit connects to the input control port of the first comparison unit and the floating potential input port of the second comparison unit, the output of the second buffer unit connects to the input control port of the second comparison unit and the floating potential input port of the first comparison unit, or alternatively the output of the first buffer unit connects to the input control port of the second comparison unit and the floating potential input port of the first comparison unit, the output of the second buffer unit connects to the input control port of the first comparison unit and the floating potential input port of the second comparison unit; and
- signal from each of the floating potential input port is passed to the corresponding output port when a voltage difference between the corresponding input control port and the floating potential input port exceeds a voltage threshold of the comparison unit, otherwise the corresponding output port provides an output equal to the fixed potential at the third port; and
- the first shaping unit comprising one or more digital inverters in series, with an input to the first digital inverter connecting to the output of the first comparison unit, and an output of the last digital inverter serving as a first output of the pulse filtering circuit, and the second shaping unit comprising one or more digital inverters in series, with an input to the first digital inverter connecting to the output of the second comparison unit, and an output of the last digital inverter serving as a second output of the pulse filtering circuit; optionally, each such buffer unit can be omitted.
12. A pulse filtering circuit device, comprising: two signal paths comprising a first path and a second path; the first path comprising a first buffer circuit, a first inverter unit and a first shaping circuit; the second path comprising a second buffer circuit, a second inverter unit and a second shaping circuit; wherein each of the first inverter unit and the second inverter unit has four ports which are a first port, a second port, a third port and a fourth port, wherein the first port serves as an input end of the first inverter unit or the second inverter unit, the second port serves as an output end of the first inverter unit or the second inverter unit, the third port serves as a fixed potential end of the first inverter unit or the second inverter unit, and the fourth port serves as a floating potential end of the first inverter unit or the second inverter unit;
- functions of the first inverter unit or the second inverter unit are that: an output electrical signal of the second port is controlled by a voltage difference between the first port and the fourth port, an electrical signal of the fourth port is transmitted to the second port through one of the first inverter unit and the second inverter unit if an absolute value of the voltage difference between the first port and the fourth port is greater than a voltage threshold VTH of the other of the first inverter unit and the second inverter unit; and the electrical signal of the fourth port is unable to be transmitted to the second port through one of the first inverter unit and the second inverter unit if the absolute value of the voltage difference between the first port and the fourth port is not greater than the voltage threshold VTH of the other of the first inverter unit and the second inverter unit.
13. The pulse filtering circuit device according to claim 12, wherein the respective third ports of the first inverter unit and the second inverter unit are connected to a power supply signal or a ground signal; and the first inverter unit and the second inverter unit are internally formed by one or more inverters.
14. The pulse filtering circuit device according to claim 13, wherein the first buffer circuit comprises a first inverter, and the second buffer circuit comprises a second inverter.
15. The pulse filtering circuit device according to claim 14, wherein the first inverter unit comprises a first PMOS transistor and a first NMOS transistor, a grid electrode of the first PMOS transistor and a grid electrode of the first NMOS transistor are connected together to serve as the first port of the first inverter unit, a drain electrode of the first PMOS transistor and a drain electrode of the first NMOS transistor are connected together to serve as the second port of the first inverter unit, a source electrode of the first PMOS transistor serves as the third port of the first inverter unit, and a source electrode of the first NMOS transistor serves as the fourth port of the first inverter unit.
16. The pulse filtering circuit device according to claim 15, wherein the second inverter unit comprises a second PMOS transistor and a second NMOS transistor, a grid electrode of the second PMOS transistor and a grid electrode of the second NMOS transistor are connected together to serve as the first port of the second inverter unit, a drain electrode of the second PMOS transistor and a drain electrode of the second NMOS transistor are connected together to serve as the second port of the second inverter unit, a source electrode of the second PMOS transistor serves as the third port of the second inverter unit, and a source electrode of the second NMOS transistor serves as the fourth port of the second inverter unit.
17. The pulse filtering circuit device according to claim 16, wherein the first shaping circuit comprises a third inverter and a fourth inverter, the second shaping circuit comprises a fifth inverter and a sixth inverter; the third port of the first inverter unit and that of the second inverter unit are connected to the power supply signal; and signals at output ends S and R are changed when an absolute value of a voltage difference between a first port of a first comparison unit and a first port of a second comparison unit is greater than the voltage threshold of the first inverter unit or the voltage threshold of the second inverter unit.
18. The pulse filtering circuit device according to claim 13, wherein the first buffer circuit comprises a seventh inverter and an eighth inverter, and the second buffer circuit comprises a ninth inverter and a tenth inverter.
19. The pulse filtering circuit device according to claim 18, wherein the first inverter unit consists of a third PMOS transistor and a third NMOS transistor, a grid electrode of the third PMOS transistor and a grid electrode of the third NMOS transistor are connected together to serve as the first port of the first inverter unit, a drain electrode of the third PMOS transistor and a drain electrode of the third NMOS transistor are connected together to serve as the second port of the first inverter unit, a source electrode of the third PMOS transistor serves as the third port of the first inverter unit, and a source electrode of the third NMOS transistor serves as the fourth port of the first inverter unit.
20. The pulse filtering circuit device according to claim 19, wherein the second inverter unit consists of a fourth PMOS transistor and a fourth NMOS transistor, a grid electrode of the fourth PMOS transistor and a grid electrode of the fourth NMOS transistor are connected together to serve as the first port of the second inverter unit, a drain electrode of the fourth PMOS transistor and a drain electrode of the fourth NMOS transistor are connected together to serve as the second port of the second inverter unit, a source electrode of the fourth PMOS transistor serves as the third port of the second inverter unit, and a source electrode of the fourth NMOS transistor serves as the fourth port of the second inverter unit.
Type: Application
Filed: Aug 20, 2018
Publication Date: Apr 4, 2019
Inventors: On Bon Peter Chan (Shatin), Jing Zhu (Jiangsu Province), Yunwu Zhang (Jiangsu Province)
Application Number: 16/105,678