INTEGRATED GATE DRIVER

A gate driver suitable for integration with the backplane of an AMOLED display includes first and second clock signal sources producing first and second clock signals each having alternating active and inactive portions configured such that when one of the clock signals is active the other of the clock signals is inactive, and active portions of the first and second clock signals do not overlap. In a daisy chain of circuits for producing gate signals, each of the circuits except the last has an output coupled to the input of the next circuit in the chain. A source of a start token signal is coupled to an input of a first circuit in the daisy chain. Each of the circuits is configured to produce a gate signal one clock cycle after an active portion of one of the clock signals is received.

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Description
CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefit of U.S. Provisional Application No. 61/969,533, filed Mar. 24, 2014, and U.S. Provisional Application No. 61/975,321, filed Apr. 4, 2014, each of which is hereby incorporated by reference herein in its entirety.

FIELD OF THE INVENTION

The present disclosure relates generally to AMOLED displays. More specifically, this disclosure relates to gate drivers suitable for integration into the back plane of an AMOLED display, which typically uses thin film transistors (TFTs).

BACKGROUND

Traditionally, when building AMOLED displays, it has been the practice to manufacture the display panel backplane and the gate drivers as separate devices. Doing so allows different manufacturing techniques to be applied to each case. If the same techniques could be used to manufacture the gate driver and the display itself, i.e., if the gate driver could be integrated into the back plane of the display, then they could be manufactured simultaneously with fewer components and less assembly required, leading to lower cost displays.

SUMMARY

In accordance with one embodiment, a gate driver suitable for integration with the backplane of an active matrix organic light emitting diode (AMOLED) display comprises clock signal sources producing first and second clock signals each having alternating active and inactive portions configured such that when one of the clock signals is active the other of the clock signals is inactive, and active portions of the first and second clock signals do not overlap; a daisy chain of circuits for producing gate signals, each of the circuits except the last circuit in the chain having an output coupled to the input of an adjacent circuit in the daisy chain; and a source of a start token signal coupled to an input of a first circuit in the daisy chain; wherein each of the circuits is configured to produce a gate signal one clock cycle after an active portion of one of the clock signals is received.

In one implementation, the gate driver is configured for use with an AMOLED display comprising p-type transistors so that an active signal corresponds to a low voltage and an inactive signal corresponds to a high voltage. The gate signals are active low for selecting or addressing p-type thin film transistors, or active high for selecting or addressing n-type thin film transistors.

Adjacent circuits in the daisy chain produce consecutive gate signals with a predetermined time interval between each pair of consecutive gate signals. The active portions of the first and second clock signals preferably have a predetermined time interval between them, to produce the predetermined time interval between each pair of consecutive gate signals.

In accordance with another embodiment, an integrated gate driver for performing emission operations comprises a source of first and second clock signals each, having alternating active and inactive portions configured such that when one is active the other is inactive and active signals do not overlap; a start token signal source and an inverse start token signal source for input into a first circuit block. Alternating odd and even circuit blocks are daisy chained together such that the output of one circuit block is connected to the input of the next circuit block, and each circuit block receives as inputs both first and second clock signals, wherein each circuit block is configured to produce an active output one clock cycle after an active signal is received and an inactive output at all other times. This gate driver may be configured for use with a display comprising p-type transistors so that an active signal corresponds with a high voltage and an inactive signal corresponds with a low voltage. The alternating circuit blocks are configured to select a line of pixels for two clock cycles in order to allow time for the pixels to settle before being programmed.

The foregoing and additional aspects and embodiments of the present disclosure will be apparent to those of ordinary skill in the art in view of the detailed description of various embodiments and/or aspects, which is made with reference to the drawings, a brief description of which is provided next.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other advantages of the disclosure will become apparent upon reading the following detailed description and upon reference to the drawings.

FIG. 1A is a block diagram of a display system using an integrated gate driver.

FIG. 1B is a block diagram of a select signal driver for the array of pixel circuits in the display of FIG. 1A.

FIG. 2A is a circuit diagram of a circuit for use in an odd block of FIG. 1B when configured as an active low select signal driver.

FIG. 2B is a circuit diagram of a circuit for use in an even block of FIG. 1B when configured as an active low select signal driver.

FIG. 2C is a timing diagram illustrating the operation of the circuits of FIGS. 2A and 2B.

FIG. 3A is a circuit diagram of a circuit for use in an odd block of FIG. 1B when configured as an active high select signal driver.

FIG. 3B is a circuit diagram of a circuit for use in an even block of FIG. 1B when configured as an active high select signal driver.

FIG. 3C is a timing diagram illustrating the operation of circuits of FIGS. 3A and 3B.

FIG. 4A is a circuit diagram of a second circuit for use in an odd block of FIG. 1B when configured as an active high select signal driver.

FIG. 4B is a circuit diagram of a second circuit for use in an even block of FIG. 1B when configured as an active high select signal driver.

FIG. 5A is a circuit diagram of a third circuit for use in an odd block of FIG. 1B when configured as an active high select signal driver.

FIG. 5B is a circuit diagram of a third circuit for use in an even block of FIG. 1B when configured as an active high select signal driver.

While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments or implementations have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of an invention as defined by the appended claims.

DETAILED DESCRIPTION

FIG. 1A shows a display 10 for use with an integrated gate driver 12. Display 10 comprises an array (m×n) of pixels. FIG. 1B shows a block diagram of an integrated select signal driver 100 for the array of pixel circuits in the display of FIG. 1A. It should be noted that although select driver 100 is shown, and discussed below, as driving rows (1 to n), it may also be implemented to drive columns (1 to m). Select driver 100 comprises a series of alternating odd blocks 101 and even blocks 102 daisy chained together so that the output of each block, e.g., SEL(1), both drives its associated row of pixels and serves as an input to the following block. Accordingly, rows can be selected and driven in sequence. Other inputs clk1 and clk2 from clock signal sources are used to regulate timing and are discussed in greater detail below. A start token signal ST from a start token signal source is used to initiate the row driving sequence.

Exemplary embodiments of select driver 100 are discussed below. In each case, it is assumed that all transistors are p-type transistors, and are therefore active low devices. Those of skill in the art will understand that complementary circuit designs can be used with active high or n-type transistors. Alternatively, a combination of p-type and n-type devices may be used to implement select signal driver 100.

FIGS. 2A and 2B show circuit diagrams for use in odd blocks 201 and even blocks 202 corresponding to blocks 101 and 102 of FIG. 1B when configured as an active low select signal driver suitable for use as a select driver during read or write operations.

Physically, the circuit elements in odd blocks 201 and even blocks 202 are identical. The difference between odd blocks 201 and even blocks 202 is the inputs. The signals clk1 and clk2 play complementary roles in odd and even circuit blocks. It should be noted that in this implementation only one of clk1 and clk2 may be active at any given time; active clock signals do not overlap, but inactive clock signals may overlap during periods where the signals are transitioning. Other combinations of clk1 and clk2 may be used to achieve similar or extra functionality.

In operation a sequence proceeds through several time periods, a subset of which is shown as 280 to 292 in FIG. 2C. It should be noted that some time periods are longer than others and that the sequence proceeds by alternating long and short periods. For example, a longer period 280-281 is followed by a short period 281-282 which is followed by a longer period 282-283. In actual operation, the number of time periods will be related to the number of rows in the display. Vgh is a voltage that corresponds to a high, therefore inactive, signal while Vgl corresponds to a low, therefore active, signal. Vgh and Vgl are either fixed or adjustable voltages provided by the power supply unit (not shown) of the display system 10.

Referring to FIGS. 2A and 2C, the operation of an odd block proceeds as follows. Block 1 will be described as an example.

At 280, Start Token (ST) and clk2 go low, therefore active, while clk1 goes high, therefore inactive. This causes transistor switches Tc, Te and Tg to close. The low ST signal will expose the bottom plate of capacitor Ca to a low signal, bring a low signal to point A 205 and cause transistor switches Ta and Tf to close. This allows a high signal to reach point B 207 which exposes the bottom plate of Cb to a high signal and causes transistor switches Tb and Td to open. Accordingly, SEL(1) goes out high as it is being fed from Vgh via Tc and high clk1 via Ta.

At 281, clk2 goes high, causing Tc, Te and Tg to open.

At 282, clk1 goes low while ST goes high. ST will stay high for the remainder of the sequence. Capacitor Ca will maintain a low signal at point A 205 and keep Ta and Tf closed. Capacitor Cb will maintain a high signal at point B 207 and keep Tb and Td open. Accordingly, SEL(1) output will be low as it is being fed from low clk1 via Ta.

At 283, clk1 goes high causing SEL(1) to go high.

At 284, clk2 goes low causing Tc, Te and Tg to close. The high ST signal will expose the bottom plate of capacitor Ca to a high signal, bring a high signal to point A 205 and cause transistor switches Ta and Tf to open. This brings a low signal, Vgl, to point B 207 which exposes Cb to a low signal and causes Tb and Td to close. Accordingly, SEL(1) goes out high as it is being fed from Vgh via Tb and Tc.

At 285, clk2 goes high causing Tc, Te and Tg to open.

At 286, clk1 goes low. Capacitor Ca will maintain a high signal at point A 205 and keep Ta and Tf open. Capacitor Cb will maintain a low signal at point B 207 and keep Tb and Td close. Accordingly, SEL(1) will remain high since it is being fed from Vgh via Tb.

At 287, clk1 goes high.

Since ST will not change again until the entire sequence needs to be repeated, block 1 will simply repeat the pattern of 284 to 287 until the ST is changed, regardless of the state of clk1 and clk2. For example, the circuit will proceed through the same states from 288-291 as it did from 284-287 and SEL(1) will remain high.

Referring to FIGS. 2B and 2C, the operation of an even block proceeds as follows. Block 2 will be described as an example. It should be noted that the operation of an even block is complementary to the operation of an odd block in that clk1 and clk2 play opposite roles.

At 282, SEL(1) and clk1 go low, therefore active, while clk2 is high, therefore inactive. This causes transistor switches Tc, Te and Tg to close. The low SEL(1) signal will expose the bottom plate of capacitor Ca to a low signal, bring a low signal to point A 206 and cause transistor switches Ta and Tf to close. This allows a high signal to reach point B 208 which exposes the bottom plate of Cb to a high signal and causes Tb and Td to open. Accordingly, SEL(2) goes out high as it is being fed from Vgh via Tc and high clk2 via Ta.

At 283, clk1 goes high, causing Tc, Te and Tg to open. SEL(1) will also go high and stay high for the remainder of the sequence. Capacitor Ca will maintain a low signal at point A 206 and keep Ta and Tf closed. Capacitor Cb will maintain a high signal at point B 208 and keep Tb and Td open.

At 284, SEL(2) and clk2 go low while SEL(1) remains high. Thus, there is a time interval (284-283) between clk1 going high and clk2 going low, and also between SEL(1) going high and SEL(2) going low.

At 285, clk2 goes high causing SEL(2) to go high.

At 286, clk1 goes low causing Tc, Te and Tg to close. The high SEL(1) signal will now expose the bottom plate of capacitor Ca to a high signal, bring a high signal to point A 206 and cause transistor switches Ta and Tf to open. This brings a low signal, Vgl, to point B 208 which exposes the bottom plate of Cb to a low signal and causes Tb and Td to close. Accordingly, SEL(2) goes out high as it is being fed from Vgh via Tb and Tc.

At 287, clk1 goes high causing Tc, Te and Tg to open. Capacitor Ca will maintain a high signal at point A 206 and keep Ta and Tf open. Capacitor Cb will maintain a low signal at point B 208 and keep Tb and Td closed.

At 288, clk2 goes low. Accordingly, SEL(2) will remain high since it is being fed from Vgh via Tb.

At 289, clk2 goes high.

Since SEL(1) will not change again until the entire sequence needs to be repeated, block 2 will simply repeat the pattern of 286 to 289, regardless of the state of clk1 and clk2, until SEL(1) changes. For example, the circuit will proceed through the same states from 290-293 as it did from 286-289 and SEL(2) will remain high.

All the odd blocks with follow the same pattern described for block 1 and all even block will follow the same pattern described for block 2, only delayed since the input of each block is the output of the previous block. In this way, each row of the display 10 may be selected and driven exclusively.

A pixel circuit in an (m×n) array, such as display system 10, may require multiple select signals to operate. An example of typical SEL signals used in a display system is write (WR), read (RD) and emission (EM). The circuits described above in FIGS. 2A-2C are suitable for WR and RD functions, but not for EM functions. Since emission is active low in a display comprising p-type transistors, a signal to tell a row to stop emitting will be active high.

FIGS. 3A and 3B show circuit diagrams for use in odd blocks 301 and even blocks 302 corresponding to 101 and 102 in FIG. 1B when configured as an active high select signal driver. Note that the circuits of FIGS. 3A and 3B are designed to hold EM signals high for twice as long in order to allow time for the components in the pixels to settle before programming.

Physically, the circuit elements in odd blocks 301 and even blocks 302 are identical. The difference between odd blocks 301 and even blocks 302 is the inputs. Clk1 and clk2 play complementary roles in odd/even blocks. It should be noted that only one of clk1 and clk2 may be active at any given time in this implementation; active clock signals do not overlap. Other combinations of clk1 and clk2 may be used to achieve similar or extra functionality.

In operation a sequence proceeds through several time periods, a subset of which are shown as 380 to 392 in FIG. 3C. It should be noted that some time periods are longer than others and that the sequence proceeds by alternating long and short periods. For example, a longer period 380-381 is followed by a short period 381-382 which is followed by a longer period 382-383. In actual operation, the number of time periods will be related to the number of rows in the display system 10. Vgh is a voltage that corresponds to a high, therefore inactive state, signal while Vgl corresponds to a low, therefore active state, signal.

Referring to FIGS. 3A and 3C, the operation of an odd block proceeds as follows. Block 1 will be described as an example. Note that an underscore, “_” indicates a signal in an inverse state. For example, ST and ST_ will always have inverse states; ST_ will be low when ST is high and vice versa.

At 380, ST_ and clk2 go low, while ST and clk1 go high. This causes transistor switches T3, T6, T7 and T10 to close. The high ST signal will expose the bottom plate of capacitor C4 to a high signal, cause T4 to open and bring a high signal to point A 303 which exposes the bottom plate of C1 to a high signal and causes T11, T5 and T2 to open. The low ST_ signal will expose the bottom plate of capacitor C3 to a low signal and cause transistor switch T8 to close and bring a low signal to point B 305 which exposes the bottom plate of C2 to a low signal and causes T12, T9 and T1 to close. Accordingly, EM(1) will be high and EM_(1) will be low.

At 381, clk2 goes high, causing transistors T3, T6, T7 and T10 to close, effectively shutting out ST and ST_ signals. Capacitor C4 will maintain a high signal and keep T4 open while C3 will maintain a low signal and keeps T8 closed. Capacitor C2 will maintain a low signal at point B 305 and keep transistors T12, T1 and T9 closed while C1 maintains a high signal at point A 303 and keeps T11, T2 and T5 open. Accordingly, EM(1) will remain high while EM_(1) will remain low.

At 382, clk1 goes low but has no effect on the output of block 1, EM(1) and EM_(1). Before 383, ST goes low and ST_ goes high, but has no effect since the transistors controlled by clk2 are closed.

At 383, clk1 goes high.

At 384, clk2 goes low causing transistor switches T3, T6, T7 and T10 to close. The low ST signal will expose the bottom plate of capacitor C4 to a low signal, cause T4 to close and bring a low signal to point A 303 which exposes the bottom plate of C1 to a low signal and causes T2, T5 and T11 to close. The high ST_ signal will expose the bottom plate of capacitor C3 to a high signal, cause T8 to open and bring a high signal to point B 305 which exposes the bottom plate of C2 to a high signal and causes T1, T9 and T12 to open. Consequently, EM(1) will turn low while EM_(1) turns high.

At 385, clk2 goes high, causing T3, T6, T7 and T10 to close. Capacitor C4 will maintain a low signal and keep T4 closed while C3 maintains a high signal and keeps T8 open. Capacitor C2 will maintain a high signal at point B 305 and keep transistor switches T1, T9 and T12 open while C1 maintains a low signal at point A 303 and keeps T2, T5 and T11 closed. Accordingly, EM(1) will remain low while EM_(1) remains high.

At 386, clk1 goes low.

At 387, clk1 goes high but has not effect on the output of block 1, EM(1) and EM_(1).

Since ST and ST_ inputs will not change again until the entire sequence needs to be repeated, block 1 will simply repeat the pattern of 384 to 387, regardless of the state of clk1 and clk2, until the inputs are changed. For example, the circuit will proceed through the same states from 388-391 as it did from 384-387. EM(1) will remain low and EM_(1) will remain high.

Referring to FIGS. 3B and 3C, the operation of an even block proceeds as follows. Block 2 will be described as an example.

At 382, EM_(1) and clk2 go low while EM(1) and clk1 go high. This causes T3, T6, T7 and T10 to close. The high EM(1) signal will expose the bottom plate of capacitor C4 to a high signal, cause T4 to open and bring a high signal to point A 304 which exposes the bottom plate of C1 to a high signal and causes T11, T5 and T2 to open. The low EM_(1) signal will expose the bottom plate of capacitor C3 to a low signal and cause transistor T8 to close and bring a low signal to point B 306 which exposes the bottom plate of C2 to a low signal and causes T12, T9 and T1 to close. Accordingly, EM(2) will go high and EM_(2) will turn low.

At 383, clk1 goes high, causing transistors T3, T6, T7 and T10 to open, effectively isolating the EM(1) and EM_(1) signals into block 2. Capacitor C4 will maintain a high signal and keep T4 open while C3 will maintain a low signal and keep T8 closed. Capacitor C2 will maintain a low signal at point B 306 and keep transistor switches T12, T1 and T9 closed while C1 maintains a high signal at point A 304 and keeps T11, T2 and T5 open. Accordingly, EM(2) will remain high while EM_(2) will remain low.

At 384, clk2 goes low but has not effect on the output, EM(2) and EM(_(2), of block 2.

At 385, clk2 goes high, which also has no effect on the output of block 2.

At 386 clk1 goes low causing transistor switches T3, T6, T7 and T10 to close. The low EM(1) signal will expose the bottom plate of capacitor C4 to a low signal, cause T4 to close and bring a low signal to point A 304 which exposes the bottom plate of C1 to a low signal and causes T2, T5 and T11 to close. The high EM_(1) signal will expose the bottom plate of capacitor C3 to a high signal, cause T8 to open and bring a high signal to point B 306 which exposes the bottom plate of C2 to a high signal and causes T1, T9 and T12 to open. Accordingly, EM(2) will turn low while EM_(2) turns high.

At 387, clk1 goes high, causing T3, T6, T7 and T10 to close. Capacitor C4 will maintain a low signal and keep T4 closed while C3 maintains a high signal and keeps T8 open. Capacitor C2 will maintain a high signal at point B 306 and keep transistors T1, T9 and T12 open while C1 maintains a low signal at point A 304 and keeps T2, T5 and T11 closed. Accordingly, EM(2) will remain low while EM_(2) remains high.

At 388, clk2 goes low and has no effect on the output of block 2.

At 389, clk1 goes high and also has no effect on the output of block 2.

Since EM(1) and EM_(1) inputs will not change again until the entire sequence needs to be repeated, block 2 will simply repeat the pattern of 386 to 389, regardless of the state of clk1 and clk2, until the inputs are changed. For example, the circuit will proceed through the same states from 390-393 as it did from 386-389. EM(2) will remain low and EM_(2) will remain high.

An analogous pattern will occur in subsequent odd blocks. A complementary analogous pattern, with clk1 and clk2 playing opposite roles, will occur in subsequent even blocks.

FIGS. 4A and 4B show circuit diagrams of a second embodiment of odd blocks 401 and even blocks 402 of FIG. 1B when configured as an active high select signal driver. The circuits of FIGS. 4A and 4B are identical to those of FIGS. 3A and 3B except for one connection of capacitor C2. In FIGS. 4A and 4B the terminals of C2 are connected to point B and the EM— output rather than point B and clk1 or clk2. Clk1 and clk2 now drive EM_(1) through T12. The timing diagram of FIG. 3C also applies to the circuits in FIGS. 4 and 4B.

It has been found that the circuits of FIGS. 4A and 4B are better able to handle variations in T12 than those shown in FIGS. 3A and 3B.

FIGS. 5A and 5B show circuit diagrams of a third embodiment of odd blocks 501 and even blocks 502, corresponding to 101 and 102 of FIG. 1B, when configured as an active high select signal driver. The circuits of FIGS. 5A and 5B are identical to those of FIGS. 3A and 3B except that C1 has been removed and T10 has been replaced by a resistance, R, connected to voltage V1, where V1<Vgl. The circuits shown in FIGS. 5A and 5B provide a more stable voltage at point A.

Physically, the circuit elements in odd blocks 501 and even blocks 502 are identical. The difference between odd blocks 501 and even blocks 502 is the inputs. Clk1 and clk2 play complementary roles in odd/even blocks. It should be noted that only one of clk1 and clk2 may be active at any given time in this implementation; active clock signals do not overlap. Other combination of clk1 and clk2 may be used to achieve similar or extra functionality.

In operation, a sequence proceeds through several time periods, a subset of which are shown as 380 to 392 in FIG. 3C. It should be noted that some time periods are longer than others and that the sequence proceeds by alternating long and short periods. For example, a longer period, 380-381, is followed by a short period, 381-382 which is followed by a longer period, 382-383. In actual operation, the number of time periods will be related to the number of rows in display system 10. Vgh is a voltage that corresponds to a high, therefore inactive state, signal while Vgl corresponds to a low, therefore active state, signal and V1<Vgl.

Referring to FIGS. 5A and 3C, the operation of an odd block proceeds as follows. Block 1 will be described as an example. Note that a “_” indicates an inverse state. For example, ST and ST— will always have inverse states; ST— will be low when ST is high and vice versa.

At 380, ST_ goes low, while ST and clk1 go high. Clk2 is also low at this time. This causes transistors T3, T6 and T7 to close. The high ST signal will expose the bottom plate of capacitor C4 to a high signal and cause T4 to open. The low ST_ signal will expose the bottom plate of capacitor C3 to a low signal and cause T8 to close and bring a low signal to point B 505 which exposes the bottom plate of C2 to a low signal and causes T12, T9 and T1 to close. Since T8 and T9 are closed, and by design the on-resistance of T8 and T9 is much less than R, a high signal reaches point A, exposes the bottom plate of C1 to a high signal and causes T11, T5 and T2 to open. Accordingly, EM(1) will be high and EM_(1) will be low.

At 381, clk2 goes high, causing transistors T3, T6 and T7 to open, effectively shutting out ST and ST_ signals. Capacitor C4 will maintain a high signal and keep T4 open while C3 will maintain a low signal and keep T8 closed. Capacitor C2 will maintain a low signal at point B 505 and keep T12, T1 and T9 closed. Since T8 and T9 are closed, and by design the on-resistance of T8 and T9 is much less than R, a high signal reaches point A 503, exposes the bottom plate of C1 to a high signal and causes T11, T5 and T2 to open. Accordingly, EM(1) will remain high while EM_(1) will remain low.

At 382, clk1 goes low. Before 383, ST goes low and ST goes high, but has no effect since the transistors controlled by clk2 are open.

At 383, clk1 goes high.

At 384 clk2 goes low causing T3, T6 and T7 to close. The low ST signal will expose the bottom plate of capacitor C4 to a low signal and cause T4 to close. The high ST_ signal will expose the bottom plate of capacitor C3 to a high signal, cause T8 to open and bring a high signal to point B 505 which exposes the bottom plate of C2 to a high signal and causes T1, T9 and T12 to open. Since T8 and T9 are open, V1 is the only signal source able to reach point A 503. This brings a low signal to point A 503 which causes T2, T5 and T11 to close. Accordingly, EM(1) will turn low while EM_(1) turns high.

At 385, clk2 goes high, causing T3, T6 and T7 to open. Capacitor C4 will maintain a low signal and keep T4 closed while C3 maintains a high signal and keeps T8 open. Capacitor C2 will maintain a high signal at point B 505 and keep T1, T9 and T12 open. Since T8 and T9 are open, V1 is the only signal source able to reach point A 503. This brings a low signal to point A 503 which causes T2, T5 and T11 to close. Accordingly, EM(1) will remain low while EM_(1) remains high.

At 386, clk1 goes low.

At 387, clk1 goes high and has no effect on the outputs of block 1.

Since ST and ST_ inputs will not change again until the entire sequence needs to be repeated, block 1 will simply repeat the pattern of 384 to 387, regardless of the state of clk1 and clk2, until the inputs are changed. For example, the circuit will proceed through the same states from 388-391 as it did from 384-387. EM(1) will remain low and EM_(1) will remain high.

Referring to FIGS. 5B and 3C, the operation of an even block proceeds as follows. Block 2 will be described as an example.

At 382, clk1 goes low, while EM(1) and clk2 are high. EM_(1) is also low at this time. This causes T3, T6 and T7 to close. The high EM(1) signal will expose the bottom plate of capacitor C4 to a high signal and cause T4 to open. The low EM_(1) signal will expose the bottom plate of capacitor C3 to a low signal, cause T8 to close and bring a low signal to point B 506 which exposes the bottom plate of C2 to a low signal and causes T12, T9 and T1 to close. Since T8 and T9 are closed, and by design the on-resistance of T8 and T9 is much less than R, a high signal reaches point A 504, exposes the bottom plate of C1 to a high signal and causes T11, T5 and T2 to open. Accordingly, EM(2) will go high and EM_(2) will turn low.

At 383, clk1 goes high, causing transistors T3, T6 and T7 to open, effectively isolating the EM(1) and EM_(1) signals. Capacitor C4 will maintain a high signal and keep T4 open while C3 will maintain a low signal and keep T8 closed. Capacitor C2 will maintain a low signal at point B 506 and keep transistors T12, T1 and T9 closed. Since T8 and T9 are closed, and by design the on-resistance of T8 and T9 is much less than R, a high signal reaches point A 504, exposes the bottom plate of C1 to a high signal and causes T11, T5 and T2 to open. Accordingly, EM(2) will remain high while EM_(2) remains low.

At 384, clk2 goes low and has no effect on the output of block 2.

At 385, clk2 goes high which also has no effect on the output of block 2.

At 386 clk1 goes low causing T3, T6 and T7 to close. The low EM(1) signal will expose the bottom plate of capacitor C4 to a low signal and cause T4 to close. The high EM_(1) signal will expose capacitor the bottom plate of C3 to a high signal, cause T8 to open and bring a high signal to point B 506 which exposes the bottom plate of C2 to a high signal and causes T1, T9 and T12 to open. Since T8 and T9 are open, V1 is the only signal source able to reach point A 504. This brings a low signal to point A 504 which causes T2, T5 and T11 to close. Accordingly, EM(2) will turn low while EM_(2) turns high.

At 387, clk1 goes high, causing T3, T6 and T7 to open. Capacitor C4 will maintain a low signal and keep T4 closed while C3 maintains a high signal and keeps T8 open. Capacitor C2 will maintain a high signal at point B 506 and keep T1, T9 and T12 open. Since T8 and T9 are open, V1 is the only signal source able to reach point A 504. This brings a low signal to point A 504 which causes T2, T5 and T11 to close. Accordingly, EM(2) will remain low while EM_(2) remains high.

At 388, clk2 goes low and has no effect on the output of block 2.

At 389, clk1 goes high and also has no effect on the output of block 2.

Since EM(1) and EM_(1) inputs will not change again until the entire sequence needs to be repeated, block 2 will simply repeat the pattern of 386 to 389, regardless of the state of clk1 and clk2, until the inputs are changed. For example, the circuit will proceed through the same states from 390-393 as it did from 386-389. EM(2) will remain low and EM_(2) will remain high.

An analogous pattern will occur in subsequent odd blocks. A complementary analogous pattern, with clk1 and clk2 playing opposite roles, will occur in subsequent even blocks.

Other permutations of the circuits shown in FIGS. 5A and 5B include: making resistance R an active element and replacing T5 and T9 with directed connections between their adjacent transistors.

In a display system 10 implementing the integrated gate driver described in FIG. 3, 4 or 5 under normal operating conditions, each row of pixels will be in turn, off and being allowed to settle, off and being programmed and on and emitting. Accordingly, at any given time, one row will be off and settling, one row will be off and being programmed and the remainder will be emitting according to their last programmed state.

Additional functionality can be achieved by varying the inputs. For example, a power-on function, a light-on function and a gate output enable (GOE) function are all possible with any of the circuits described above.

A power-on function can be used whenever display system 10 is first powered up or at any other time that a simultaneous reset of all SEL outputs is desired. In the circuits of FIGS. 2A and 2B, if clk1, clk2 and Vgl are set low while Vgh and ST are set high then the inactive signal will propagate to the entire SEL(1) to SEL(n) of display system 10 and all SEL signals will be deactivated. In the circuits of FIGS. 3A, 3B, 4A, 4B, 5A, and 5B, if clk1, clk2, Vgl and ST— are set low while Vgh and ST are set high the same result will be achieved. V1 can be allowed to float during this operation.

A light-on function can be used to test the functionality of all the pixels by selecting and driving all rows simultaneously. In the circuits of FIGS. 2A and 2B this can be achieved by setting all of the inputs, clk1, clk2, Vgl, Vgh and ST to low. Light-on can be achieved in the circuits of FIGS. 3A, 3B, 4A, 4B, 5A and 5B by setting inputs clk1, clk2, Vgl, Vgh, ST and ST_ to low. V1 can be allowed to float.

A GOE (gate output enable) function allows an active SEL line to be momentarily deactivated even when a token is present. This can be achieved by altering the clk1 signal input for odd blocks or the clk2 signal input for even blocks. For example, consider the circuit of FIG. 2A, an odd block, as it reaches time 284. Normally, clk2 would rise at 284 causing the token to shift into the next block. However, if clk2 is instead held high, a GOE function can be realized. In this situation, if clk1 goes low again, SEL(1) will be reactivated. This can be used to implement in-pixel compensation or to read out pixel characteristics for external compensation.

While particular implementations and applications of the present disclosure have been illustrated and described, it is to be understood that the present disclosure is not limited to the precise construction and compositions disclosed herein and that various modifications, changes, and variations can be apparent from the foregoing descriptions without departing from the spirit and scope of an invention as defined in the appended claims.

Claims

1-15. (canceled)

16. A gate driver suitable for integration with the backplane of an active matrix organic light emitting diode (AMOLED) display, said gate driver comprising

clock signal sources producing first and second clock signals each having alternating active and inactive portions configured such that when one of said clock signals is active the other of said clock signals is inactive, and active portions of said first and second clock signals do not overlap;
a daisy chain of circuits integrated within said backplane for producing gate signals, each of said circuits including a capacitor and a thin film transistor, and each of said circuits except the last circuit in the daisy chain having an output coupled to an input of an adjacent circuit in the daisy chain; and
a source of a start token signal coupled to an input of a first circuit in said daisy chain;
wherein each of said circuits is configured to produce a gate signal one clock cycle after an active portion of one of said clock signals is received.

17. The gate driver of claim 16 which is configured for use with an AMOLED display comprising p-type transistors so that an active signal corresponds to a low voltage and an inactive signal corresponds to a high voltage.

18. The gate driver of claim 16 in which said gate signals are active low for selecting or addressing p-type thin film transistors.

19. The gate driver of claim 16 in which said gate signals are active high for selecting or addressing n-type thin film transistors.

20. The gate driver of claim 16 in which said circuits produce consecutive gate signals with a predetermined time gap between each pair of consecutive gate signals.

21. The gate driver of claim 20 in which said active portions of said first and second clock signals have a predetermined time gap between them, to produce said time gap between each pair of consecutive gate signals.

22. An integrated gate driver for performing emission operations of a display, the gate driver comprising:

a source of first and second clock signals each, having alternating active and inactive portions configured such that when one is active the other is inactive and active signals do not overlap;
a source for a start token signal and an inverse start token signal for input into a first circuit block;
integrated within a backplane of the display alternating odd and even circuit blocks daisy chained together such that the output of one circuit block is connected to the input of the next circuit block and each circuit block receives as inputs both first and second clock signals, wherein each circuit block includes a capacitor and a thin film transistor and is configured to produce an active output one clock cycle after an active signal is received and an inactive output at all other times.

23. The integrated gate driver of claim 22 configured for use with a display comprising p-type transistors so that an active signal corresponds with a high voltage and an inactive signal corresponds with a low voltage.

24. The integrated gate driver of claim 22 wherein the alternating circuit blocks are configured to select a line of pixels for two clock cycles in order to allow time for the pixels to settle before being programmed.

25. A method of producing gate signals from a gate driver integrated with the backplane of an active matrix organic light emitting diode (AMOLED) display, said method comprising producing first and second clock signals each having alternating active and inactive portions configured such that when one of said clock signals is active the other of said clock signals is inactive, and active portions of said first and second clock signals do not overlap;

producing gate signals from a daisy chain of circuits integrated within said backplane, each of said circuits including a capacitor and a thin film transistor, and each of said circuits except the last circuit in the daisy chain having an output coupled to the input of an adjacent circuit in the daisy chain;
supplying a start token signal to an input of a first circuit in said daisy chain; and
producing a gate signal from each of said circuits, each gate signal being produced one clock cycle after said start token signal or an active portion of one of said clock signals is received.

26. The method of claim 25 in which the AMOLED display comprises p-type transistors so that an active signal corresponds to a low voltage and an inactive signal corresponds to a high voltage.

27. The method of claim 25 in which said gate signals are active low for selecting or addressing p-type thin film transistors.

28. The method of claim 25 in which said gate signals are active high for selecting or addressing n-type thin film transistors.

29. The method of claim 25 which produces consecutive gate signals with a predetermined time gap between each pair of consecutive gate signals.

30. The method of claim 29 in which said active portions of said first and second clock signals have a predetermined time gap between them, to produce said time gap between each pair of consecutive gate signals.

Patent History
Publication number: 20190180678
Type: Application
Filed: Dec 4, 2018
Publication Date: Jun 13, 2019
Inventors: Gholamreza Chaji (Waterloo), Yaser Azizi (Waterloo)
Application Number: 16/209,870
Classifications
International Classification: G09G 3/3225 (20060101); G09G 3/3266 (20060101); G11C 19/28 (20060101);