CROSS REFERENCE TO RELATED APPLICATION This application is continuation of International Application No. PCT/CN2017/113352, filed on Nov. 28, 2017, entitled “DISTRIBUTIVE-DRIVING OF LIQUID CRYSTAL DISPLAY (LCD) PANEL,” which claims priority to International Application No. PCT/CN2016/111387, filed on Dec. 21, 2016, entitled “DISTRIBUTIVE-DRIVING OF DISPLAY PANEL,” which claims priority to U.S. Provisional Application No. 62/426,882, filed on Nov. 28, 2016, entitled “DISTRIBUTIVE-DRIVING OF DISPLAY PANEL,” all of which are hereby incorporated by reference in their entireties.
BACKGROUND The disclosure relates generally to display technologies, and more particularly, to driving of display panel.
Display resolution is limited by the physical size of a display panel in each of the width dimension (i.e., in the row/horizontal direction) and the height dimension (i.e., in the column/vertical direction), as well as the minimum pattern size of fabricating the components on the display panel in each dimension. Depending on the ratio of subpixels to pixels, known display systems can have a very large number of source lines (a.k.a. data lines) arranged in the row direction, which can increase the manufacturing complexity and cost. For example, a wide quad high-definition (WQHD) display panel (e.g., resolution is 1440×2560) with the real-RGB subpixel arrangement (the ratio is 3), the number of the source lines may be 4320. Moreover, it became increasingly desirable to narrow the bezel surrounding the display panel, allowing for more screen area. The very large number of gate lines (a.k.a. scan lines) and the corresponding driving circuits for high resolution displays, however, limit the narrow-bezel or bezel-less designs.
Moreover, for liquid crystal displays (LCDs), aperture ratio is one of the important characteristics because it affects the brightness and power consumption of the displays. As the resolution of LCDs increases, the total area occupied by the gate and source lines in each subpixel region has greater impact on the aperture ratio of LCDs.
SUMMARY The disclosure relates generally to display technologies, and more particularly, to driving of display panel.
In one example, a liquid crystal display (LCD) apparatus includes a color filter layer, a liquid crystal (LC) layer, and a pixel circuit layer. The color filter layer includes a plurality of color filters corresponding to an array of pixels arranged in M rows and N columns. The number of the color filters is k times of the number of the pixels. The LC layer is divided into a plurality of LC regions, each of which corresponds to a respective one of the color filters. The pixel circuit layer includes a plurality pixel circuits, each of which is configured to drive a respective one of the LC regions. The pixel circuit layer also includes xM gate lines and (k/x)N source lines, where x is a fraction larger than 1, and each of xM and (k/x)N is a positive integer.
In another example, an LCD apparatus includes a color filter layer, an LC layer, a pixel circuit layer, a gate driving circuit, a source driving circuit, and control logic. The color filter layer includes a plurality of color filters corresponding to an array of pixels arranged in M rows and N columns. The number of the color filters is k times of the number of the pixels. The LC layer is divided into a plurality of LC regions, each of which corresponds to a respective one of the color filters. The pixel circuit layer includes a plurality pixel circuits, each of which is configured to drive a respective one of the LC regions. The pixel circuit layer includes xM gate lines and (k/x)N source lines, where x is a fraction larger than 1, and each of xM and (k/x)N is a positive integer. The gate driving circuit is operatively coupled to the pixel circuit layer via the xM gate lines and configured to scan the plurality of pixel circuits. The source driving circuit is operatively coupled to the pixel circuit layer via the (k/x)N source lines and configured to write display data in a frame to the plurality of pixel circuits. The control logic is operatively coupled to the gate driving circuit and source driving circuit and configured to receive original display data and convert the original display data into converted display data based on the (k/x)N source lines. The control logic is also configured to provide a first set of control signals to the gate driving circuit to control the gate driving circuit to scan the plurality of pixel circuits via the xM gate lines. The control logic is further configured to provide a second set of control signals to the source driving circuit to control the source driving circuit to write the converted display data to the plurality of pixel circuits.
BRIEF DESCRIPTION OF THE DRAWINGS The embodiments will be more readily understood in view of the following description when accompanied by the below figures and wherein like reference numerals represent like elements, wherein:
FIG. 1 is a block diagram illustrating an apparatus including a display and control logic in accordance with an embodiment;
FIGS. 2A and 2B are block diagrams illustrating the display shown in FIG. 1 including drivers in accordance with an embodiment;
FIG. 3 is a depiction of an arrangement of gate lines and source lines for driving a display panel having an array of pixels;
FIG. 4 is a block diagram illustrating one example of the control logic shown in FIG. 1 in accordance with an embodiment;
FIG. 5A is a depiction of an arrangement of gate lines and source lines for driving of subpixels in an example arrangement;
FIG. 5B is a depiction of an arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 5A in accordance with an embodiment;
FIG. 5C is a depiction of another arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 5A in accordance with an embodiment;
FIG. 5D is a depiction of still another arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 5A in accordance with an embodiment;
FIG. 6A is a depiction of an arrangement of gate lines and source lines for driving of subpixels in another example arrangement;
FIG. 6B is a depiction of an arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 6A in accordance with an embodiment;
FIG. 6C is a depiction of another arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 6A in accordance with an embodiment;
FIG. 6D is a depiction of still another arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 6A in accordance with an embodiment;
FIG. 7A is a depiction of an arrangement of gate lines and source lines for driving of subpixels in still another example arrangement;
FIG. 7B is a depiction of an arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 7A in accordance with an embodiment;
FIG. 7C is a depiction of another arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 7A in accordance with an embodiment;
FIG. 7D is a depiction of still another arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 7A in accordance with an embodiment;
FIG. 8A is a depiction of an arrangement of gate lines and source lines for driving of subpixels in yet another example arrangement;
FIG. 8B is a depiction of an arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 8A in accordance with an embodiment;
FIG. 8C is a depiction of another arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 8A in accordance with an embodiment;
FIG. 9A is a depiction of an arrangement of gate lines and source lines for driving of subpixels in yet another example arrangement;
FIG. 9B is a depiction of an arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 9A in accordance with an embodiment;
FIG. 9C is a depiction of another arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 9A in accordance with an embodiment;
FIG. 10 is a block diagram illustrating a demultiplexing module operatively coupled to the control logic and source driver shown in FIG. 2A in accordance with an embodiment;
FIG. 11 is a block diagram illustrating one example of the demultiplexing module shown in FIG. 10 in accordance with an embodiment;
FIG. 12A is a depiction of an arrangement of gate lines and source lines for distributive-driving with source-demultiplexing of subpixels in the example arrangement shown in FIG. 5A in accordance with an embodiment;
FIG. 12B is a depiction of another arrangement of gate lines and source lines for distributive-driving with source-demultiplexing of subpixels in the example arrangement shown in FIG. 5A in accordance with an embodiment;
FIGS. 13A-13D are depictions of an arrangement of gate lines and source lines for distributive-driving with source-demultiplexing of subpixels in the example arrangement shown in FIG. 6A in accordance with an embodiment;
FIG. 14 is a cross-sectional view illustrating one example of an LCD apparatus in accordance with an embodiment;
FIG. 15A is a circuit diagram illustrating one example of a pixel circuit of an LCD apparatus in accordance with an embodiment;
FIG. 15B is a layout diagram illustrating one example of a subpixel of an LCD apparatus in accordance with an embodiment;
FIG. 16A is a depiction of an arrangement of gate lines and source lines for driving subpixels in an example arrangement of an LCD apparatus;
FIG. 16B is a depiction of an arrangement of gate lines and source lines for distributive-driving of subpixels in an example arrangement of an LCD apparatus in accordance with an embodiment;
FIGS. 17A-17B are depictions of example color filter arrangements for distributive-driving of subpixels of an LCD apparatus in accordance with various embodiments;
FIGS. 18A-18C are depictions of arrangements of gate lines, source lines, and pixel circuits for distributive-driving of subpixels in the example arrangement shown in FIG. 16B in accordance with an embodiment;
FIG. 19A is a depiction of a color filter arrangement of an LCD apparatus; and
FIG. 19B is a depiction of an example color filter arrangement for distributive-driving of subpixels of an LCD apparatus in accordance with an embodiment.
DETAILED DESCRIPTION In the following detailed description, numerous specific details are set forth by way of examples in order to provide a thorough understanding of the relevant disclosures. However, it should be apparent to those skilled in the art that the present disclosure may be practiced without such details. In other instances, well known methods, procedures, systems, components, and/or circuitry have been described at a relatively high-level, without detail, in order to avoid unnecessarily obscuring aspects of the present disclosure.
Throughout the specification and claims, terms may have nuanced meanings suggested or implied in context beyond an explicitly stated meaning. Likewise, the phrase “in one embodiment/example” as used herein does not necessarily refer to the same embodiment and the phrase “in another embodiment/example” as used herein does not necessarily refer to a different embodiment. It is intended, for example, that claimed subject matter include combinations of example embodiments in whole or in part.
In general, terminology may be understood at least in part from usage in context. For example, terms, such as “and”, “or”, or “and/or,” as used herein may include a variety of meanings that may depend at least in part upon the context in which such terms are used. Typically, “or” if used to associate a list, such as A, B or C, is intended to mean A, B, and C, here used in the inclusive sense, as well as A, B or C, here used in the exclusive sense. In addition, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.
As will be disclosed in detail below, among other novel features, the distributive-driving of display panel disclosed herein can reduce the number of source lines or gate lines. By distributing the driving load to the source and gate lines according to an optimal ratio, the timing specification of display panels can be optimized. According to some aspects of the present disclosure, the reduction of source lines may be achieved by distributing the driving load to the source and gate lines according to an optimal ratio based on the specific subpixel arrangement of the display panel. On the other hand, the distributive-driving of display panel disclosed herein may not overburden the gate scan (e.g., by doubling the number of gate lines) and thus, would not significantly reduce the scan period of each subpixel.
According to some aspects of the present disclosure, the reduction of gate lines may be achieved by distributing the driving load to the source and gate lines according to an optimal ratio based on the specific subpixel arrangement of the display panel. The reduction of gate lines, as well as the corresponding driving circuits, can help to achieve the narrow-bezel or bezel-less designs. Moreover, the scan period of each subpixel can be increased because of the less gate lines to be scanned in each frame. In some embodiments, source-demultiplexing can be combined with the distributive-driving so that the number of data channels (a.k.a. source channels) provided by control logic, e.g., driver integrated circuit (IC), does not need to increase to the same number of the source lines, thereby avoiding increasing the design and manufacturing complexity and cost. In some embodiments in which the display is an active-matrix organic light-emitting diode (AMOLED) display, the extra wiring caused by the distributive-driving may not reduce the aperture ratio of display because each subpixel is a top emitting OLED.
Moreover, by balancing the number of source lines and gate lines with an optimal ratio (e.g., making the number of source lines and gate lines to be comparable to each other), the situation in which the number of source lines is much larger than the number of gate lines may be avoided. Thus, the single-layer COF package can be used for flexible displays, such as for packaging driver ICs of flexible displays with high resolution, thereby reducing the manufacturing cost compared with the traditional flexible displays using multi-layer COF package.
Additional novel features will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and the accompanying drawings or may be learned by production or operation of the examples. The novel features of the present disclosure may be realized and attained by practice or use of various aspects of the methodologies, instrumentalities, and combinations set forth in the detailed examples discussed below.
FIG. 1 illustrates an apparatus 100 including a display 102 and control logic 104. Apparatus 100 may be any suitable device, for example, a virtual reality (VR) or augmented reality (AR) device (e.g., VR headset, etc.), handheld device (e.g., dumb or smart phone, tablet, etc.), wearable device (e.g., eyeglasses, wrist watch, etc.), automobile control station, gaming console, television set, laptop computer, desktop computer, netbook computer, media center, set-top box, global positioning system (GPS), electronic billboard, electronic sign, printer, or any other suitable device. In this embodiment, display 102 is operatively coupled to control logic 104 and is part of apparatus 100, such as but not limited to, a head-mounted display, handheld device screen, computer monitor, television screen, head-up display (HUD), dashboard, electronic billboard, or electronic sign. Display 102 may be an OLED display, liquid crystal display (LCD), E-ink display, electroluminescent display (ELD), billboard display with LED or incandescent lamps, or any other suitable type of display.
Control logic 104 may be any suitable hardware, software, firmware, or combination thereof, configured to receive display data 106 (e.g., pixel data) and generate control signals 108 for driving the subpixels on display 102. Control signals 108 are used for controlling writing of display data 106 (either in its original form or in a converted form) to the subpixels and directing operations of display 102. For example, subpixel rendering (SPR) algorithms for various subpixel arrangements may be part of control logic 104 or implemented by control logic 104. As described below in detail with respect to FIG. 4, control logic 104 in one embodiment may include a control signal generating module 402 having a timing controller (TCON) 408 and a clock generator 410, a data interface 404, and a data converting module 406 having a storing unit 412 and a data reconstructing unit 414. Control logic 104 may include any other suitable components, such as an encoder, a decoder, one or more processors, controllers, and storage devices. Control logic 104 may be implemented as a standalone IC chip, such as an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). Apparatus 100 may also include any other suitable components such as, but not limited to tracking devices 110 (e.g., inertial sensors, camera, eye tracker, GPS, or any other suitable devices for tracking motion of eyeballs, facial expression, head movement, body movement, and hand and body gesture), input devices 112 (e.g., a mouse, keyboard, remote controller, handwriting device, microphone, scanner, etc.), and speakers (not shown).
In some embodiments, control logic 104 may be manufactured in a chip-on-glass (COG) package, for example, when display 102 is a rigid display. In some embodiments, control logic 104 may be manufactured in a COF package, for example, when display 102 is a flexible display, e.g., a flexible OLED display. As described below in detail, the distribute-driving of display panel can optimize the numbers of source lines and gate lines. As a result, in some embodiments, control logic 104 may be manufactured in a single-layer COF package due to the less number of source lines. It is to be appreciated that control logic 104 may be integrated with drivers, such as gate drivers, source drivers, and light emitting drivers, in a driver IC. The driver IC, including control logic 104 and drivers, may be manufactured in a COF package, such as a single-layer COF package.
In this embodiment, apparatus 100 may be a handheld or a VR/AR device, such as a smart phone, a tablet, or a VR headset. Apparatus 100 may also include a processor 114 and memory 116. Processor 114 may be, for example, a graphics processor (e.g., graphics processing unit (GPU)), an application processor (AP), a general processor (e.g., APU, accelerated processing unit; GPGPU, general-purpose computing on GPU), or any other suitable processor. Memory 116 may be, for example, a discrete frame buffer or a unified memory. Processor 114 is configured to generate display data 106 in display frames and may temporally store display data 106 in memory 116 before sending it to control logic 104. Processor 114 may also generate other data, such as but not limited to, control instructions 118 or test signals, and provide them to control logic 104 directly or through memory 116. Control logic 104 then receives display data 106 from memory 116 or from processor 114 directly.
FIGS. 2A and 2B are block diagrams illustrating display 102 shown in FIG. 1 including drivers in accordance with an embodiment. Display 102 in this embodiment includes a display panel having an active region 200 including a plurality of subpixels 201. The display panel may also include on-panel drivers, e.g., a gate driver 202 and a source driver 204. It is to be appreciated that in some embodiments, gate driver 202 and source driver 204 may not be on-panel drivers, i.e., not parts of the display panel, but instead are operatively coupled to the display panel.
Each subpixel 201 may be any of the units that make up a pixel, i.e., a subdivision of a pixel. For example, a subpixel 201 may be a single-color display element that can be individually addressed. In some embodiments in which display 102 is an OLED display, each subpixel 201 may include an OLED, such as a top emitting OLED, and a pixel circuit for driving the OLED. Each OLED can emit a light in a predetermined brightness and color, such as but not limited to, red, green, blue, yellow, cyan, magenta, or white. Each pixel circuit includes thin film transistors (TFTs) and is configured to drive the corresponding subpixel 201 by controlling the light emitting from the respective OLED according to control signals 108 from control logic 104. The pixel circuit may be in a 2T1C configuration (i.e., including a switching transistor, a driving transistor, and a storage capacitor) or may include a compensation circuit with more transistors and/or capacitors for brightness uniformity, such as in a 7T1C, 5T1C, 5T2C, or 6T1C configuration.
In some embodiments in which display 102 is an LCD, each subpixel 201 may include a color filter, a liquid crystal region, and a pixel circuit for driving the liquid crystal region. Depending on the characteristics (e.g., color, thickness, etc.) of the respective color filter, a subpixel 201 may present a distinct color and brightness, such as but not limited to, red, green, blue, yellow, cyan, magenta, or white. Each pixel circuit includes at least one TFT (e.g., a switching transistor) and a storage capacitor.
In this embodiment, the plurality of subpixels correspond to an array of pixels arranged in M rows and N columns. The number of the subpixels may be k times of the number of the pixels. That is, k subpixels may constitute one pixel, and each pixel may consist of k subpixels. k may be any positive integer larger than 1. In some embodiments, k may be 2, 3, or 4. In some embodiments, each row of pixels may include N pixels arranged in the row/horizontal direction (but are not necessarily in a straight line), which include kN subpixels. Similarly, in some embodiments, each column of pixels may include M pixels arranged in the column/vertical direction (but are not necessarily in a straight line), which include M subpixels. It is to be appreciated that the k subpixels of each pixel (and the kN subpixels in each row of pixels and the M subpixels in each column of pixels) may not be physically aligned. In other words, the centers of the k subpixels of each pixel (and the kN subpixels in each row of pixels and the M subpixels in each column of pixels) may not be in a straight line in the row/horizontal direction and/or in a straight line in the column/vertical direction. It is also to be appreciated that, the colors, sizes, and/or shapes of the k subpixels of each pixel may not be the same as well.
In this embodiment, display 102 (and the display panel thereof) has a resolution of N×M, which corresponds to the array of pixels arranged in the M rows and N columns. That is, display 102 can be characterized by its display resolution, which is the number of distinct pixels in each dimension that can be displayed. For example, for a WQHD display with a resolution of 1440×2560, the corresponding array of pixels is arranged in 2560 rows and 1440 columns. In this embodiment, display data 106 is provided by processor 114 in display frames. For each frame, display data 106 includes M×N pieces of pixel data, and each piece of pixel data corresponds to one pixel of the array of pixels. Each pixel may be considered as a sample of an original image represented by a piece of pixel data having multiple components, such as multiple color components or a luminance and multiple chrominance components. In some embodiments, each piece of pixel data includes a first component representing a first color, a second component representing a second color, and a third component representing a third color. The first, second, and third colors may be three primary colors (i.e., red, green, and blue) so that each pixel can present a full color. That is, display data 106 may be programmed at the pixel-level.
In some embodiments, three subpixels may constitute one pixel, i.e., k is 3. In these embodiments, each of the three components of a piece of pixel data may be used to render one of the three subpixels of the respective pixel. In some embodiments, four subpixels may constitute one pixel, i.e., k is 4. In these embodiments, one of the four subpixels of a pixel (e.g., a white subpixel) may be rendered based on at least one of the three components of the respective piece of pixel data. One example is disclosed in U.S. Pat. No. 9,165,526, having a title of “Subpixel Arrangement of Displays and Methods for Rendering the Same,” which is incorporated herein by reference. In some embodiments, two subpixels may constitute one pixel, i.e., k is 2. In these embodiments, SPR algorithms may be used to render the two subpixels of each pixel based on the specific subpixel arrangement. Examples are disclosed in U.S. Pat. No. 8,786,645, having a title of “Subpixel Arrangement of Displays and Methods for Rendering the Same,” U.S. Pat. No. 9,418,586, having a title of “Subpixel Arrangement of Displays and Methods for Rendering the Same,” U.S. Patent Application Publication No. 2015/0339969, having a title of “Method and Apparatus for Subpixel Rendering,” U.S. Patent Application Publication No. 2016/0240593, having a title of “Subpixel Arrangement of Displays and Methods for Rendering the Same,” and U.S. Patent Application Publication No. 2016/0275846, having a title of “Subpixel Arrangement of Displays and Driving Circuit Thereof,” each of which is incorporated herein by reference. It is to be appreciated that any subpixel arrangements corresponding to any number of k may be applied by the distributive-driving of display panel disclosed herein. The applications of the distributive-driving scheme to exemplary subpixel arrangements are described below in detail.
Gate driver 202 in this embodiment is operatively coupled to active region 200 via a plurality of gate lines (a.k.a. scan lines) and configured to scan the plurality of subpixels 201 based on at least some of control signals 108. For example, gate driver 202 applies a plurality of scan signals, which are generated based on control signals 108 from control logic 104, to the plurality of gate lines for scanning the plurality of subpixels 201 in a gate scanning order. A scan signal is applied to the gate electrode of a switching transistor of each pixel circuit during the scan period to turn on the switching transistor so that the data signal for the corresponding subpixel 201 can be written by source driver 204. It is to be appreciated that although one gate driver 202 is illustrated in FIG. 2A, in some embodiments, multiple gate drivers may work in conjunction with each other to scan the subpixels 201.
In some display systems, such as the example illustrated in FIG. 3, M gate lines (G1, G2, . . . , Gm) are provided for an array of pixels (PX) arranged in M rows and N columns. Subpixels in each of the M rows of pixels are operatively coupled to one gate line and are scanned by a scan signal transmitted via the gate line. In other words, the number of the gate lines is the same as the number of the rows of pixels (M). In some display systems (not shown), subpixels in each of the M rows of pixels are operatively coupled to two gate lines and are scanned by two scan signals transmitted via the two gate lines. That is, the number of the gate lines is twice of the number of the rows of pixels (i.e., dual-gate driving). For example, one half of the subpixels in a row of pixels may be scanned via one gate line, and the other half of the subpixels in the same row of pixels may be scanned via another gate line.
Referring backing to FIG. 2A, in a first embodiment, to achieve the distributive-driving of display panel, the number of the gate lines is xM, wherein x is a faction between 1 and 2. In other words, in average, subpixels in each of the M rows of pixels are operatively coupled to more than one but less than two gate lines and are scanned by scan signals transmitted via the gate lines. In other words, the number of the gate lines is larger than the number of the rows of pixels, but less than twice of the number of the rows of pixels. In this embodiment, x may be represented as p/q, wherein each of p and q is a positive integer, and p is larger than q and is smaller than 2q. In some embodiments, x may be 3/2, 4/3, 5/3, 5/4, 7/4, 6/5, 7/5, 8/5, 9/5, 7/6, 11/6, 8/7, 9/7, 10/7, 11/7, 12/7, 13/7, 9/8, 11/8, 13/8, 15/8, 10/9, 11/9, 13/9, 14/9, 16/9, or 17/9, to name a few. It is to be appreciated that x is not limited to the examples given above and may be any faction between 1 and 2. As will be described below in detail with respect to various examples, the value of x may be determined based on the specific subpixel arrangement to balance the driving load between the gate and source lines (e.g., the numbers of gate and source lines) and/or to simplify the wiring of gate lines and/or source lines on the display panel. It is to be appreciated that in this embodiment, the number of gate/scan channels provided by control logic 104 may be the same as or different from the number of gate lines, e.g., smaller than M due to demultiplexing.
In a second embodiment, to achieve the distributive-driving of display panel, the number of the gate lines is xM, wherein x is a faction between 0 and 1. In other words, in average, subpixels in each of the M rows of pixels are operatively coupled to less than one gate line, and subpixels in more than one row of pixels are scanned by scan signal transmitted via one gate line. In other words, the number of the gate lines is smaller than the number of the rows of pixels. In this embodiment, x may be represented as p/q, wherein each of p and q is a positive integer, and q is larger than p. In some embodiments, p may be equal to 1. For example, subpixels in every q rows of pixels are operatively coupled to one gate line. In some embodiments, p may be larger than 1. For example, subpixels in every q rows of pixels are operatively coupled top gate lines. As will be described below in detail with respect to various examples, the value of x may be determined based on the specific subpixel arrangement to balance the driving load between the gate and source lines (e.g., the numbers of gate and source lines) and/or to simplify the wiring of gate lines and/or source lines on the display panel. Consequently, compared with the example shown in FIG. 3, the number of gate lines (and the corresponding driving circuits, e.g., in gate driver 202) can be reduced by a factor of (1−x) so that the scan period of each subpixel can be increased in each frame. The reduction of gate lines and corresponding driving circuits can also help the narrow-bezel or bezel-less designs of the display panel. It is to be appreciated that in this embodiment, the number of gate/scan channels in control logic 104 may be the same as or different from the number of gate lines, e.g., smaller than M due to demultiplexing.
Source driver 204 in this embodiment is operatively coupled to active region 200 via a plurality of source lines (a.k.a. data lines) and configured to write display data 106 in a frame to the plurality of subpixels 201 based on at least some of control signals 108. For example, source driver 204 may simultaneously apply a plurality of data signals to the plurality of source lines for the subpixels 201. That is, source driver 204 may include one or more shift registers, digital-analog converters (DAC), multiplexers (MUX), and arithmetic circuit for controlling a timing of application of voltage to the source electrode of the switching transistor of each pixel circuit (i.e., during the scan period in each frame) and a magnitude of the applied voltage according to gradations of display data 106. It is to be appreciated that although one source driver 204 is illustrated in FIG. 2A, in some embodiments, multiple source drivers may work in conjunction with each other to apply the data signals to the source lines for the subpixels 201.
Referring to the example illustrated in FIG. 3, the number of subpixels are k times of the number of pixels. In other words, the subpixels may be represented as M×N×k. In this example, the k subpixels constituting one pixel are operatively coupled to the same gate line, and the subpixels may be represented as M×kN. As a result, kN source lines (S1, . . . Sk, S(k+1), . . . S2k, . . . , S(nk−1), . . . , Skn) are provided for the array of pixels. For each pixel, k source lines are provided. Subpixels in each of the N columns of pixels are operatively coupled to k source lines and are written with k data signals transmitted via the k source lines. In other words, the number of the source lines is k times of the number of the columns of pixels (N). It is to be appreciated that in some embodiments, the source lines may be operatively coupled to the columns of subpixels in a “zigzag” manner. As a result, the number of the source lines may be more than k times of the number of the columns of pixels (N). For example, the number of the source lines may be kN+1. In the example of dual-gate driving, the k subpixels constituting one pixel are operatively coupled to two gate lines, and the subpixels may be represented as 2M×(k/2)N. Thus, in average, subpixels in each of the N columns of pixels are operatively coupled to k/2 source lines and are written with data signals transmitted via the k/2 source lines. That is, the number of the gate lines is k/2 times of the number of the columns of pixels (N).
Referring backing to FIG. 2A, in the first embodiment described above, to achieve the distributive-driving of display panel, the number of the source lines is yN, where y is k/x. The subpixels are represented as xM×(k/x)N. Each of xM and (k/x)N is a positive integer. In other words, in average, subpixels in each of the N columns of pixels are operatively coupled to k/x source lines and are written with data signals transmitted via the k/x source lines. Because x is between 1 and 2 in this embodiment, the number of the source lines ((k/x)N) is smaller than the number of the columns of pixels multiplied by the ratio k of the subpixels to the pixels (kN), but is larger than one half of the number of the columns of pixels multiplied by the ratio k ((k/2)N). Consequently, compared with the example shown in FIG. 3, the number of source lines can be reduced by a factor of (1−1/x) so that the manufacturing complexity and cost may be reduced. It is to be appreciated that the number of source/data channels in control logic 104 may be the same as or different from the number of source lines due to demultiplexing.
In the second embodiment described above, to achieve the distributive-driving of display panel, the number of the source lines is yN, where y is k/x. The subpixels are represented as xM×(k/x)N. Each of xM and (k/x)N is a positive integer. In other words, in average, subpixels in each of the N columns of pixels are operatively coupled to k/x source lines and are written with data signals transmitted via the k/x source lines. Because x is between 0 and 1 in this embodiment, the number of the source lines ((k/x)N) is larger than the number of the columns of pixels multiplied by the ratio k of the subpixels to the pixels (kN). As described below in detail, in some embodiments, the number of source/data channels provided by control logic 104 may be different from the number of source lines due to demultiplexing. That is, the number of data channels may maintain the same by the source-demultiplexing even the number of source lines increases due to the distributive-driving.
In general, to achieve the distributive-driving of display panel, the number of the gate lines may be xM, and the number of the source lines may be (k/x)N, wherein x is a faction between 0 and 2, and each of xM and (k/x)N is a positive integer. x may be represented as p/q, wherein each of p and q is a positive integer, and p is smaller than 2q and does not equal to q. The value of x (i.e., p and q) may be determined based on the specific subpixel arrangement to balance the driving load between the gate and source lines (e.g., the numbers of gate and source lines) and/or to simplify the wiring of gate lines and/or source lines on the display panel. It is to be appreciated that in some embodiments, the number of gate lines and/or source lines may be more than xM and (k/x)N, respectively due to the “zigzag” connection of gate lines or source lines. For example, the number of source lines may be (k/x)N+1 or (k/x)N+2 when the source lines are operatively coupled to the columns of subpixels in a “zigzag” manner.
Additionally or optionally, a light emitting driver 206 may be included on the display panel in some embodiments in which display 102 is an OLED display. Light emitting driver 206 may be operatively coupled to active region 200 and configured to cause each subpixel to emit light in each frame. It is to be appreciated that although one light emitting driver 206 is illustrated in FIG. 2A, in some embodiments, multiple light emitting drivers may work in conjunction with each other.
FIG. 4 is a block diagram illustrating one example of control logic 104 shown in FIG. 1 in accordance with an embodiment. In this embodiment, control logic 104 is an IC (but may alternatively include a state machine made of discrete logic and other components), which provides an interface function between processor 114/memory 116 and display 102. Control logic 104 may provide various control signals 108 with suitable voltage, current, timing, and demultiplexing, to cause display 102 to show the desired text or image. Control logic 104 may be an application-specific microcontroller and may include storage units such as RAM, flash memory, EEPROM, and/or ROM, which may store, for example, firmware and display fonts. In this embodiment, control logic 104 includes control signal generating module 402, data interface 404, and data converting module 406. Data interface 404 may be any display data interface, such as but not limited to, display serial interface (DSI), display pixel interface (DPI), and display bus interface (DBI) by the Mobile Industry Processor Interface (MIPI) Alliance, unified display interface (UDI), digital visual interface (DVI), high-definition multimedia interface (HDMI), and DisplayPort (DP). Data interface 404 is configured to receive display data 106 in multiple frames and any other control instructions 118 or test signals. Display data 106 may be received in consecutive frames at any frame rates, such as 30, 60, 72, 120, or 240 frames per second (fps). The received display data 106 is forwarded by data interface 404 to control signal generating module 402 and data converting module 406.
In this embodiment, control signal generating module 402 provides control signals 108 to gate driver 202 and source driver 204 (optionally to light emitting driver 206) to drive the subpixels in active region 200. Control signal generating module 402 may include TCON 408 and clock generator 410. TCON 408 may provide a variety of enable signals to gate driver 202 and source driver 204 (optionally to light emitting driver 206), respectively. Clock generator 410 may provide a variety of clock signals to gate driver 202 and source driver 204 (optionally to light emitting driver 206), respectively.
As described above, display data 106 may be programmed at the pixel-level. In each frame, display data 106 may include M×N pieces of pixel data corresponding to the array of pixels arranged in the M rows and N columns. Because of the distributive-driving of display panel disclosed herein, the number of the source lines is no longer the same as the number of the columns of pixels multiplied by the ratio k (kN), i.e., the number of data channels (kN), but instead becomes (k/x)N. Thus, in some embodiments, display data 106 may be converted into converted display data 416 to accommodate the source line and gate line arrangement due to the specific distributive-driving scheme. In this embodiment, data converting module 406 provides converted display data 416 to source driver 204 based on the source line and gate line arrangement on the display panel. In some embodiments, the timing of each data signal may be re-arranged according to the gate scanning order as well.
In this embodiment, data converting module 406 in this embodiment includes storing unit 412 and data reconstructing unit 414. Storing unit 412 is configured to receive display data 106 (original display data) and store display data 106 in each frame because the conversion of display data 106 may be performed at the frame-level. Storing unit 412 may be data latches or line buffers that temporally store display data 106 forwarded by data interface 404. Data reconstructing unit 414 is operatively coupled to storing unit 412 and configured to reconstruct, in each frame, display data 106 into corresponding converted display data 416 based on the source line and gate line arrangement on the display panel. Data reconstructing unit 414 of data converting module 406 may convert display data 106 into converted display data 416 based on the number of source lines ((k/x)N) according to the distributive-driving scheme. For example, any suitable sampling algorithms may be used by data reconstructing unit 414 to obtain converted display data 416 suitable for the (k/x)N source lines. It is to be appreciated that in some embodiments, data converting module 406 may not be included in control logic 104. Instead, processor 114 may adjust the timing of display data 106 to accommodate the source line and gate line arrangement on the display panel.
FIG. 5A is a depiction of an arrangement of gate lines and source lines for driving of subpixels in an example arrangement. In this example, the display panel includes an array of subpixels in a first color A, a second color B, and a third color C, arranged in rows and columns. A, B, and C denote three different colors, such as but not limited to, red, green, blue, yellow, cyan, magenta, or white. It is to be appreciated that the “array,” “row,” and “column” of subpixels may not correspond to the “array,” “row,” and “column” of pixels described above. Subpixels A, B, and C are alternatively arranged in every three adjacent rows of the array of subpixels. Every two adjacent rows of the array of subpixels are staggered with each other. In one example, a first subpixel in one of the A, B, and C colors and a second subpixel in the same color as the first subpixel may be by 3 units in the row/horizontal direction and 4 units in the column/vertical direction. The first and second subpixels may have a minimum distance among subpixels in the same color. Details of one example of the subpixel arrangements illustrated in this example are provided in U.S. Patent Application Publication No. 2016/0275846, having a title of “Subpixel Arrangement of Displays and Driving Circuit Thereof.” It is to be appreciated that the relative spatial relationship (i.e., 3 units in the row/horizontal direction and 4 units in the column/vertical direction) is not limited to the example described above.
FIG. 5A illustrates a portion of the display panel including 24 subpixels. Depending on the ratio k of subpixels to pixels, the resolution of the display panel may be 4×2 (k=3) or 6×2 (k=2). Regardless, the array of pixels in this example is arranged in two rows and is operatively coupled to two gate lines G1 and G2. As to the source lines, the array of pixels may be arranged in four columns, each of which is operatively coupled to three source lines, or arranged in six columns, each of which is operatively coupled to two source lines. In any event, the array of pixels in this example is operatively coupled to 12 source lines S1 to S12. In other words, the number of the gate lines (2) is the same as the number of the rows of pixels (2), and the number of the source lines (12) is the same as the number of the columns of pixels multiplied by the ratio k (4×3 or 6×2).
FIG. 5B is a depiction of an arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 5A in accordance with an embodiment. In this embodiment, the display panel with the same subpixel arrangement illustrated in FIG. 5A is driven by a distributive-driving scheme to reduce the number of source lines. In this embodiment, the array of pixels is operatively coupled to three gate lines G1-G3, which is one and a half (3/2) times of the number of the rows of pixels (2). The number of the gate lines in this embodiment may be represented as (3/2)M, where x=3/2 (a fraction between 1 and 2) and M is the number of the rows of pixels. For example, every two rows of pixels are driven by gate driver 202 via three gate lines. The scan period of each subpixel is reduced to two thirds (⅔) of the scan period of each subpixel in the example shown in FIG. 5A, which is greater than the scan period of the example using the dual-gate driving (i.e., one half (½) of the scan period of each subpixel in the example shown in FIG. 5A). It is to be appreciated that the gate lines shown in FIGS. 5A and 5B represent the logical connections between subpixels. The actual wiring of the gate lines may be understood by a person of ordinary skill in the art based on the logical connections and may be different in different examples.
As to the source lines, the array of pixels is operatively coupled to eight source lines S1-S8, which is two thirds (⅔) of the number of the columns of pixels multiplied by the ratio k (12). The number of the source lines in this embodiment may be represented as (⅔)kN, where k is the ratio of subpixels to pixels and N is the number of the columns of pixels. In other words, the number of the source lines in the example in FIG. 5A is reduced by one third (⅓) in the example in FIG. 5B by the distributive-driving of display panel disclosed herein. For example, for a WQHD display panel, the number of source lines can be reduced from 2880 to 1920. It is to be appreciated that in FIGS. 5A and 5B, subpixels labeled with the same source line number (e.g., S1, S2, S3, . . . , S8) are connected by the same corresponding source line. Compared with the example in FIG. 5A, the wiring of gate lines and source lines in this embodiment can be simplified as well.
FIG. 5C is a depiction of another arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 5A in accordance with an embodiment. In this embodiment, the display panel with the same subpixel arrangement illustrated in FIG. 5A is driven by a distributive-driving scheme to reduce the number of gate lines. In this embodiment, the array of pixels is operatively coupled to one gate line G1, which is one half (½) of the number of the rows of pixels (2). The number of the gate lines in this embodiment may be represented as (½)M, where x=½ (a fraction between 0 and 1) and M is the number of the rows of pixels. For example, every two rows of pixels are driven by gate driver 202 via one gate line. In other words, the number of the gate lines in the example in FIG. 5A is reduced by one half (½) in the example in FIG. 5C by the distributive-driving of display panel disclosed herein. For example, for a WQHD display panel, the number of gate lines can be reduced from 2560 to 1280. The scan period of each subpixel may increase to twice of the scan period of each subpixel in the example shown in FIG. 5A. It is to be appreciated that the gate lines shown in FIG. 5C represent the logical connections between subpixels. The actual wiring of the gate lines may be understood by a person of ordinary skill in the art based on the logical connections and may be different in different examples.
As to the source lines, the array of pixels is operatively coupled to 24 source lines S1-S24, which is twice of the number of the columns of pixels multiplied by the ratio k (12). The number of the source lines in this embodiment may be represented as 2 kN, where k is the ratio of subpixels to pixels and N is the number of the columns of pixels. It is to be appreciated that in FIG. 5C, subpixels labeled with the same source line number (e.g., S1, S2, S3, . . . , S24) are connected by the same corresponding source line.
FIG. 5D is a depiction of still another arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 5A in accordance with an embodiment. In this embodiment, the display panel with the same subpixel arrangement illustrated in FIG. 5A is driven by a distributive-driving scheme to reduce the number of gate lines. In this embodiment, the array of pixels is operatively coupled to one gate line G1 and one half of gate line G2, which is three fourths (¾) of the number of the rows of pixels (2). The number of the gate lines in this embodiment may be represented as (¾)M, where x=¾ (a fraction between 0 and 1) and M is the number of the rows of pixels. For example, every four rows of pixels are driven by gate driver 202 via three gate lines. In other words, the number of the gate lines in the example in FIG. 5A is reduced by one fourth (¼) in the example in FIG. 5D by the distributive-driving of display panel disclosed herein. For example, for a WQHD display panel, the number of gate lines can be reduced from 2560 to 1920. The scan period of each subpixel may increase to four thirds (4/3) of the scan period of each subpixel in the example shown in FIG. 5A. It is to be appreciated that the gate lines shown in FIG. 5D represent the logical connections between subpixels. The actual wiring of the gate lines may be understood by a person of ordinary skill in the art based on the logical connections and may be different in different examples.
As to the source lines, the array of pixels is operatively coupled to 16 source lines S1-S16, which is four thirds (4/3) of the number of the columns of pixels multiplied by the ratio k (12). The number of the source lines in this embodiment may be represented as (4/3)kN, where k is the ratio of subpixels to pixels and N is the number of the columns of pixels. It is to be appreciated that in FIG. 5D, subpixels labeled with the same source line number (e.g., S1, S2, S3, . . . , S16) are connected by the same corresponding source line.
FIG. 6A is a depiction of an arrangement of gate lines and source lines for driving of subpixels in another example arrangement. In this example, the display panel includes an array of subpixels in a first color A, a second color B, and a third color C, arranged in rows and columns. A, B, and C denote three different colors, such as but not limited to, red, green, blue, yellow, cyan, magenta, or white. It is to be appreciated that the “array,” “row,” and “column” of subpixels may not correspond to the “array,” “row,” and “column” of pixels as described above. In one example, the array of subpixels may be considered as the rotation of the array of subpixels in FIG. 5A by 90 degrees. In another example, the array of subpixels includes a first subpixel repeating group represented by A-B-C and a second subpixel repeating group represented by C-A-B that are alternatively applied to two adjacent rows of the array of subpixels. The two adjacent rows of the array of subpixels are staggered with each other. Details of one example of the subpixel arrangements illustrated in this example are provided in U.S. Patent Application Publication No. 2015/0339969, having a title of “Method and Apparatus for Subpixel Rendering.”
FIG. 6A illustrates a portion of the display panel including 36 subpixels. Depending on the ratio k of subpixels to pixels, the resolution of the display panel may be 4×3 (k=3) or 6×3 (k=2). Regardless, the array of pixels in this example is arranged in three rows and is operatively coupled to three gate lines G1-G3. As to the source lines, the array of pixels may be arranged in four columns, each of which is operatively coupled to three source lines, or arranged in six columns, each of which is operatively coupled to two source lines. In any event, the array of pixels in this example is operatively coupled to 12 source lines S1 to S12. In other words, the number of the gate lines (3) is the same as the number of the rows of pixels (3), and the number of the source lines (12) is the same as the number of the columns of pixels multiplied by the ratio k (4×3 or 6×2).
FIG. 6B is a depiction of an arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 6A in accordance with an embodiment. In this embodiment, the display panel with the same subpixel arrangement illustrated in FIG. 6A is driven by a distributive-driving scheme to reduce the number of source lines. In this embodiment, the array of pixels is operatively coupled to four gate lines G1-G4, which is four thirds (4/3) of the number of the rows of pixels (3). The number of the gate lines in this embodiment may be represented as (4/3)M, where x=4/3 (a fraction between 1 and 2) and M is the number of the rows of pixels. For example, every three rows of pixels are driven by gate driver 202 via four gate lines. The scan period of each subpixel is reduced to three fourth (¾) of the scan period of each subpixel in the example shown in FIG. 6A, which is greater than the scan period of the example using the dual-gate driving (i.e., one half (½) of the scan period of each subpixel in the example shown in FIG. 6A). It is to be appreciated that the gate lines shown in FIGS. 6A and 6B represent the logical connections between subpixels. The actual wiring of the gate lines may be understood by a person of ordinary skill in the art based on the logical connections and may be different in different examples.
As to the source lines, the array of pixels is operatively coupled to nine source lines S1-S9, which is three fourth (¾) of the number of the columns of pixels multiplied by the ratio k (12). The number of the source lines in this embodiment may be represented as (¾)kN, where k is the ratio of subpixels to pixels and N is the number of the columns of pixels. In other words, the number of the source lines in the example in FIG. 6A is reduced by one fourth (¼) in the example in FIG. 6B by the distributive-driving of display panel disclosed herein. For example, for a WQHD display panel, the number of source lines can be reduced from 2880 to 2160. It is to be appreciated that in FIGS. 6A and 6B, subpixels labeled with the same source line number (e.g., S1, S2, S3, . . . , S9) are connected by the same corresponding source line. Compared with the example in FIG. 6A, the wiring of gate lines and source lines in this embodiment can be simplified as well.
As described above, in some embodiments, the source lines may be operatively coupled to the columns of subpixels in a “zigzag” manner as shown, for example, in FIG. 6C. FIG. 6C is similar to FIG. 6B except that the source lines are operatively coupled to the columns of subpixels in a “zigzag” manner. For example, in each odd row (e.g., 1 and 3), the source lines start from S1, while in each even row (e.g., 2 and 4), the source lines start from S0. As a result, the number of source lines in FIG. 6C is one more than the number of source lines in the embodiment of FIG. 6B (i.e., is (3k/4)N+1). Nevertheless, a person of ordinary skill in the art would understand that even with the “zigzag” manner of source line arrangement, the number of source lines on a display panel with distributive-driving is substantially (k/x)N.
FIG. 6D is a depiction of another arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 6A in accordance with an embodiment. In this embodiment, the display panel with the same subpixel arrangement illustrated in FIG. 6A is driven by a distributive-driving scheme to reduce the number of gate lines. In this embodiment, the array of pixels is operatively coupled to two gate lines G1 and G2, which is two thirds (⅔) of the number of the rows of pixels (3). The number of the gate lines in this embodiment may be represented as (⅔)M, where x=⅔ (a fraction between 0 and 1) and M is the number of the rows of pixels. For example, every three rows of pixels are driven by gate driver 202 via two gate lines. In other words, the number of the gate lines in the example in FIG. 6A is reduced by one third (⅓) in the example in FIG. 6D by the distributive-driving of display panel disclosed herein. For example, for a WQHD display panel, the number of gate lines can be reduced from 3840 to 2560. The scan period of each subpixel may increase to one and a half (3/2) times of the scan period of each subpixel in the example shown in FIG. 6A. It is to be appreciated that the gate lines shown in FIG. 6D represent the logical connections between subpixels. The actual wiring of the gate lines may be understood by a person of ordinary skill in the art based on the logical connections and may be different in different examples.
As to the source lines, the array of pixels is operatively coupled to 18 source lines S1-S18, which is one and a half (3/2) times of the number of the columns of pixels multiplied by the ratio k (12). The number of the source lines in this embodiment may be represented as (3/2)kN, where k is the ratio of subpixels to pixels and N is the number of the columns of pixels. It is to be appreciated that in FIG. 6D, subpixels labeled with the same source line number (e.g., S1, S2, S3, . . . , S18) are connected by the same corresponding source line.
FIG. 7A is a depiction of an arrangement of gate lines and source lines for driving of subpixels in still another example arrangement. In this example, the display panel includes an array of subpixels in a first color A, a second color B, and a third color C, arranged in rows and columns. A, B, and C denote three different colors, such as but not limited to, red, green, blue, yellow, cyan, magenta, or white. It is to be appreciated that the “array,” “row,” and “column” of subpixels may not correspond to the “array,” “row,” and “column” of pixels as described above. In this example, the array of subpixels includes a subpixel repeating group represented by A-B-C, which repeats itself in both the row/horizontal direction and the column/vertical direction. One example of such subpixel arrangement is known as the “real-RGB” or “RGB strips” arrangement.
FIG. 7A illustrates a portion of the display panel including 24 subpixels. Depending on the ratio k of subpixels to pixels, the resolution of the display panel may be 4×2 (k=3, e.g., the adjacent A, B, and C subpixels constitute one pixel) or 6×2 (k=2). Regardless, the array of pixels in this example is arranged in two rows and is operatively coupled to two gate lines G1-G2. As to the source lines, the array of pixels may be arranged in four columns, each of which is operatively coupled to three source lines, or arranged in six columns, each of which is operatively coupled to two source lines. In any event, the array of pixels in this example is operatively coupled to 12 source lines S1 to S12. In other words, the number of the gate lines (2) is the same as the number of the rows of pixels (2), and the number of the source lines (12) is the same as the number of the columns of pixels multiplied by the ratio k (4×3 or 6×2).
FIG. 7B is a depiction of an arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 7A in accordance with an embodiment. In this embodiment, the display panel with the same subpixel arrangement illustrated in FIG. 7A is driven by a distributive-driving scheme to reduce the number of source lines. In this embodiment, the array of pixels is operatively coupled to three gate lines G1-G3, which is one and a half (3/2) times of the number of the rows of pixels (2). The number of the gate lines in this embodiment may be represented as (3/2)M, where x=3/2 (a fraction between 1 and 2) and M is the number of the rows of pixels. For example, every two rows of pixels are driven by gate driver 202 via three gate lines. The scan period of each subpixel is reduced to two thirds (⅔) of the scan period of each subpixel in the example shown in FIG. 7A, which is greater than the scan period of the examples using the dual-gate driving (i.e., one half (½) of the scan period of each subpixel in the example shown in FIG. 7A). It is to be appreciated that the gate lines shown in FIGS. 7A and 7B represent the logical connections between subpixels. The actual wiring of the gate lines may be understood by a person of ordinary skill in the art based on the logical connections and may be different in different examples.
As to the source lines, the array of pixels is operatively coupled to eight source lines S1-S8, which is two thirds (⅔) of the number of the columns of pixels multiplied by the ratio k (12). The number of the source lines in this embodiment may be represented as (⅔)kN, where k is the ratio of subpixels to pixels and N is the number of the columns of pixels. In other words, the number of the source lines in the example in FIG. 7A is reduced by one third (⅓) in the example in FIG. 7B by the distributive-driving of display panel disclosed herein. For example, for a WQHD display panel, the number of source lines can be reduced from 2880 to 1920. It is to be appreciated that in FIGS. 7A and 7B, subpixels labeled with the same source line number (e.g., S1, S2, S3, . . . , S8) are connected by the same corresponding source line.
FIG. 7C is a depiction of another arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 7A in accordance with an embodiment. In this embodiment, the display panel with the same subpixel arrangement illustrated in FIG. 7A is driven by a distributive-driving scheme to reduce the number of gate lines. In this embodiment, the array of pixels is operatively coupled to one gate line G1, which is one half (½) of the number of the rows of pixels (2). The number of the gate lines in this embodiment may be represented as (½)M, where x=½ (a fraction between 0 and 1) and M is the number of the rows of pixels. For example, every two rows of pixels are driven by gate driver 202 via one gate line. In other words, the number of the gate lines in the example in FIG. 7A is reduced by one half (½) in the example in FIG. 7C by the distributive-driving of display panel disclosed herein. For example, for a WQHD display panel, the number of gate lines can be reduced from 2560 to 1280. The scan period of each subpixel may increase to twice of the scan period of each subpixel in the example shown in FIG. 7A. It is to be appreciated that the gate lines shown in FIG. 7C represent the logical connections between subpixels. The actual wiring of the gate lines may be understood by a person of ordinary skill in the art based on the logical connections and may be different in different examples.
As to the source lines, the array of pixels is operatively coupled to 24 source lines S1-S24, which is twice of the number of the columns of pixels multiplied by the ratio k (12). The number of the source lines in this embodiment may be represented as 2 kN, where k is the ratio of subpixels to pixels and N is the number of the columns of pixels. It is to be appreciated that in FIG. 7C, subpixels labeled with the same source line number (e.g., S1, S2, S3, . . . , S24) are connected by the same corresponding source line.
FIG. 7D is a depiction of still another arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 7A in accordance with an embodiment. In this embodiment, the display panel with the same subpixel arrangement illustrated in FIG. 7A is driven by a distributive-driving scheme to reduce the number of gate lines. In this embodiment, the array of pixels is operatively coupled to one gate line G1 and one third (⅓) of gate line G2, which is two thirds (⅔) of the number of the rows of pixels (2). For example, in some rows of subpixels (pixels), e.g., the even rows, one half of the subpixels are operatively coupled to one gate line, while the other half of the subpixels are operatively coupled to another gate line. The number of the gate lines in this embodiment may be represented as (⅔)M, where x=⅔ (a fraction between 0 and 1) and M is the number of the rows of pixels. For example, every three rows of pixels are driven by gate driver 202 via two gate lines. In other words, the number of the gate lines in the example in FIG. 7A is reduced by one third (⅓) in the example in FIG. 7D by the distributive-driving of display panel disclosed herein. For example, for a WQHD display panel, the number of gate lines can be reduced from 3840 to 2560. The scan period of each subpixel may increase to one and a half (3/2) times of the scan period of each subpixel in the example shown in FIG. 7A. It is to be appreciated that the gate lines shown in FIG. 7D represent the logical connections between subpixels. The actual wiring of the gate lines may be understood by a person of ordinary skill in the art based on the logical connections and may be different in different examples.
As to the source lines, the array of pixels is operatively coupled to 18 source lines S1-S18, which one and a half (3/2) times of the number of the columns of pixels multiplied by the ratio k (12). The number of the source lines in this embodiment may be represented as (3/2)kN, where k is the ratio of subpixels to pixels and N is the number of the columns of pixels. It is to be appreciated that in FIG. 7D, subpixels labeled with the same source line number (e.g., S1, S2, S3, . . . , S18) are connected by the same corresponding source line.
FIG. 8A is a depiction of an arrangement of gate lines and source lines for driving of subpixels in yet another example arrangement. In this example, the display panel includes an array of subpixels in a first color A, a second color B, and a third color C, arranged in rows and columns. A, B, and C denote three different colors, such as but not limited to, red, green, blue, yellow, cyan, magenta, or white. It is to be appreciated that the “array,” “row,” and “column” of subpixels may not correspond to the “array,” “row,” and “column” of pixels as described above. In this example, the array of subpixels includes a first subpixel repeating group represented by A-B-C-B and a second subpixel repeating group represented by C-B-A-B that are alternatively applied to two adjacent rows of the array of subpixels. The two adjacent rows of the array of subpixels are aligned with each other. The number of subpixels B on the display panel is twice of the number of the subpixels A or C. One example of such subpixel arrangement is known as the “PenTile RGBG” arrangement in which A denotes red (R) subpixels, B denotes green (G) subpixels, and C denotes blue (B) subpixels. In the “PenTile RGBG” arrangement, the sizes of subpixels R, G, and B may be different. For example, the size of subpixels R or subpixels B may be larger than that of subpixels G.
FIG. 8A illustrates a portion of the display panel including 24 subpixels. Depending on the ratio k of subpixels to pixels, the resolution of the display panel may be 4×2 (k=3, e.g., the adjacent A, B, and C subpixels constitute one pixel) or 6×2 (k=2). Regardless, the array of pixels in this example is arranged in two rows and is operatively coupled to two gate lines G1-G2. As to the source lines, the array of pixels may be arranged in four columns, each of which is operatively coupled to three source lines, or arranged in six columns, each of which is operatively coupled to two source lines. In any event, the array of pixels in this example is operatively coupled to 12 source lines S1 to S12. In other words, the number of the gate lines (2) is the same as the number of the rows of pixels (2), and the number of the source lines (12) is the same as the number of the columns of pixels multiplied by the ratio k (4×3 or 6×2).
FIG. 8B is a depiction of an arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 8A in accordance with an embodiment. In this embodiment, the display panel with the same subpixel arrangement illustrated in FIG. 8A is driven by a distributive-driving scheme to reduce the number of source lines. In this embodiment, the array of pixels is operatively coupled to three gate lines G1-G3, which is one and a half (3/2) times of the number of the rows of pixels (2). The number of the gate lines in this embodiment may be represented as (3/2)M, where x=3/2 (a fraction between 1 and 2) and M is the number of the rows of pixels. For example, every two rows of pixels are driven by gate driver 202 via three gate lines. The scan period of each subpixel is reduced to two thirds (⅔) of the scan period of each subpixel in the example shown in FIG. 8A, which is greater than the scan period of the example using the dual-gate driving (i.e., one half (½) of the scan period of each subpixel in the example shown in FIG. 8A). It is to be appreciated that the gate lines shown in FIGS. 8A and 8B represent the logical connections between subpixels. The actual wiring of the gate lines may be understood by a person of ordinary skill in the art based on the logical connections and may be different in different examples.
As to the source lines, the array of pixels is operatively coupled to eight source lines S1-S8, which is two thirds (⅔) of the number of the columns of pixels multiplied by the ratio k (12). The number of the source lines in this embodiment may be represented as (⅔)kN, where k is the ratio of subpixels to pixels and N is the number of the columns of pixels. In other words, the number of the source lines in the example in FIG. 8A is reduced by one third (⅓) in the example in FIG. 8B by the distributive-driving of display panel disclosed herein. For example, for a WQHD display panel, the number of source lines can be reduced from 2880 to 1920. It is to be appreciated that in FIGS. 8A and 8B, subpixels labeled with the same source line number (e.g., S1, S2, S3, . . . , S8) are connected by the same corresponding source line.
FIG. 8C is a depiction of another arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 8A in accordance with an embodiment. In this embodiment, the display panel with the same subpixel arrangement illustrated in FIG. 8A is driven by a distributive-driving scheme to reduce the number of gate lines. In this embodiment, the array of pixels is operatively coupled to one gate line G1, which is one half (½) of the number of the rows of pixels (2). The number of the gate lines in this embodiment may be represented as (½)M, where x=½ (a fraction between 0 and 1) and M is the number of the rows of pixels. For example, every two rows of pixels are driven by gate driver 202 via one gate line. In other words, the number of the gate lines in the example in FIG. 8A is reduced by one half (½) in the example in FIG. 8C by the distributive-driving of display panel disclosed herein. For example, for a WQHD display panel, the number of gate lines can be reduced from 2560 to 1280. The scan period of each subpixel may increase to twice of the scan period of each subpixel in the example shown in FIG. 8A. It is to be appreciated that the gate lines shown in FIG. 8C represent the logical connections between subpixels. The actual wiring of the gate lines may be understood by a person of ordinary skill in the art based on the logical connections and may be different in different examples.
As to the source lines, the array of pixels is operatively coupled to 24 source lines S1-S24, which is twice of the number of the columns of pixels multiplied by the ratio k (12). The number of the source lines in this embodiment may be represented as 2 kN, where k is the ratio of subpixels to pixels and N is the number of the columns of pixels. It is to be appreciated that in FIG. 8C, subpixels labeled with the same source line number (e.g., S1, S2, S3, . . . , S24) are connected by the same corresponding source line.
FIG. 9A is a depiction of an arrangement of gate lines and source lines for driving of subpixels in yet another example arrangement. In this example, the display panel includes an array of subpixels in a first color A, a second color B, and a third color C, arranged in rows and columns. A, B, and C denote three different colors, such as but not limited to, red, green, blue, yellow, cyan, magenta, or white. It is to be appreciated that the “array,” “row,” and “column” of subpixels may not correspond to the “array,” “row,” and “column” of pixels as described above. In this example, the subpixel arrangement is similar to the example in FIG. 8A except that the subpixels B are in separate rows from the subpixels A and C. The subpixel arrangement in FIG. 9A may be considered as a special case of the subpixel arrangement in FIG. 8A because the arrangement of gate lines and source lines for the subpixel arrangement in FIG. 9A is the same as that in FIG. 8A. The size of subpixels B may be smaller than that of the subpixels A or C. One example of such subpixel arrangement is known as the “PenTile diamond” arrangement. It is to be appreciated that the sizes and shapes of subpixels A, B, and C are not limited to the example shown in FIG. 9A.
FIG. 9A illustrates a portion of the display panel including 24 subpixels. Depending on the ratio k of subpixels to pixels, the resolution of the display panel may be 4×2 (k=3, e.g., the adjacent A, B, and C subpixels constitute one pixel) or 6×2 (k=2). Regardless, the array of pixels in this example is arranged in two rows and is operatively coupled to two gate lines G1-G2. As to the source lines, the array of pixels may be arranged in four columns, each of which is operatively coupled to three source lines, or arranged in six columns, each of which is operatively coupled to two source lines. In any event, the array of pixels in this example is operatively coupled to 12 source lines S1 to S12. In other words, the number of the gate lines (2) is the same as the number of the rows of pixels (2), and the number of the source lines (12) is the same as the number of the columns of pixels multiplied by the ratio k (4×3 or 6×2).
FIG. 9B is a depiction of an arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 9A in accordance with an embodiment. In this embodiment, the display panel with the same subpixel arrangement illustrated in FIG. 9A is driven by a distributive-driving scheme to reduce the number of source lines. In this embodiment, the array of pixels is operatively coupled to three gate lines G1-G3, which is one and a half (3/2) times of the number of the rows of pixels (2). The number of the gate lines in this embodiment may be represented as (3/2)M, where x=3/2 (a fraction between 1 and 2) and M is the number of the rows of pixels. For example, every two rows of pixels are driven by gate driver 202 via three gate lines. The scan period of each subpixel is reduced to two thirds (⅔) of the scan period of each subpixel in the example shown in FIG. 9A, which is greater than the scan period of the example using the dual-gate driving (i.e., one half (½) of the scan period of each subpixel in the example shown in FIG. 9A). It is to be appreciated that the gate lines shown in FIGS. 9A and 9B represent the logical connections between subpixels. The actual wiring of the gate lines may be understood by a person of ordinary skill in the art based on the logical connections and may be different in different examples.
As to the source lines, the array of pixels is operatively coupled to eight source lines S1-S8, which is two thirds (⅔) of the number of the columns of pixels multiplied by the ratio k (12). The number of the source lines in this embodiment may be represented as (⅔)kN, where k is the ratio of subpixels to pixels and N is the number of the columns of pixels. In other words, the number of the source lines in the example in FIG. 9A is reduced by one third (⅓) in the example in FIG. 9B by the distributive-driving of display panel disclosed herein. For example, for a WQHD display panel, the number of source lines can be reduced from 2880 to 1920. It is to be appreciated that in FIGS. 9A and 9B, subpixels labeled with the same source line number (e.g., S1, S2, S3, . . . , S8) are connected by the same corresponding source line.
Compared with the example in FIG. 8B, the arrangement of gate lines and source lines for distributive-driving of subpixels in FIG. 9B is not the same, although the original arrangement of gate lines and source lines is the same for both examples in FIGS. 9A and 9B. That is, for the same arrangement of gate lines and source lines of subpixels, different arrangements of gate lines and source lines for distributive-driving of subpixels can be achieved. It is also noted that x equals to 3/2 in both examples of FIGS. 8B and 9B. That is, to achieve the same ratio (x) of distributive-driving of subpixels, different arrangements of gate lines and source lines for distributive-driving of subpixels may be applied as well.
FIG. 9C is a depiction of another arrangement of gate lines and source lines for distributive-driving of subpixels in the example arrangement shown in FIG. 9A in accordance with an embodiment. In this embodiment, the display panel with the same subpixel arrangement illustrated in FIG. 9A is driven by a distributive-driving scheme to reduce the number of gate lines. In this embodiment, the array of pixels is operatively coupled to one gate line G1, which is one half (½) of the number of the rows of pixels (2). The number of the gate lines in this embodiment may be represented as (½)M, where x=½ (a fraction between 0 and 1) and M is the number of the rows of pixels. For example, every two rows of pixels are driven by gate driver 202 via one gate line. In other words, the number of the gate lines in the example in FIG. 9A is reduced by one half (½) in the example in FIG. 9C by the distributive-driving of display panel disclosed herein. For example, for a WQHD display panel, the number of gate lines can be reduced from 2560 to 1280. The scan period of each subpixel may increase to twice of the scan period of each subpixel in the example shown in FIG. 9A. It is to be appreciated that the gate lines shown in FIG. 9C represent the logical connections between subpixels. The actual wiring of the gate lines may be understood by a person of ordinary skill in the art based on the logical connections and may be different in different examples.
As to the source lines, the array of pixels is operatively coupled to 24 source lines S1-S24, which is twice of the number of the columns of pixels multiplied by the ratio k (12). The number of the source lines in this embodiment may be represented as 2 kN, where k is the ratio of subpixels to pixels and N is the number of the columns of pixels. It is to be appreciated that in FIG. 9C, subpixels labeled with the same source line number (e.g., S1, S2, S3, . . . , S24) are connected by the same corresponding source line.
It is to be appreciated that the examples illustrated in FIGS. 5B, 6B, 6C, 7B, 8B, and 9B are for the illustrative purpose only and do not limit the distributive-driving of display panel to only the subpixel arrangements illustrated in these examples. It is also to be appreciated that even for the same subpixel arrangement disclosed in any of the examples illustrated in FIGS. 5B, 6B, 6C, 7B, 8B, and 9B, any other suitable distributive-driving schemes may be applied as well. For example, the value of x is not limited to 3/2 and 4/3 as disclosed in the examples illustrated in FIGS. 5B, 6B, 6C, 7B, 8B, and 9B, and can be any fraction between 1 and 2. That is, every q rows of pixels may be driven by gate driver 202 via p gate lines as long as p is larger than q but smaller than 2q. Also, the value of k is not limited to 2 and 3 as disclosed in the examples illustrated in FIGS. 5B, 6B, 6C, 7B, 8B, and 9B, and can be any other positive integer larger than 1, such as 4.
Similarly, it is to be appreciated that the examples illustrated in FIGS. 5C, 5D, 6D, 7C, 7D, 8C, and 9C are for the illustrative purpose only and do not limit the distributive-driving of display panel to only the subpixel arrangements illustrated in these examples. It is also to be appreciated that even for the same subpixel arrangement disclosed in any of the examples illustrated in FIGS. 5C, 5D, 6D, 7C, 7D, 8C, and 9C, any other suitable distributive-driving schemes may be applied as well. For example, the value of x is not limited to ½, ⅔, and ¾ as disclosed in the examples illustrated in FIGS. 5C, 5D, 6D, 7C, 7D, 8C, and 9C, and can be any fraction between 0 and 1. That is, every q rows of pixels may be driven by gate driver 202 via p gate lines as long as q is larger than p. Also, the value of k is not limited to 2 and 3 as disclosed in the examples illustrated in FIGS. 5C, 5D, 6D, 7C, 7D, 8C, and 9C, and can be any other positive integer larger than 1, such as 4.
FIG. 10 is a block diagram illustrating a demultiplexing module 1002 operatively coupled to control logic 104 and source driver 204 shown in FIG. 2A in accordance with an embodiment. In some embodiments, such as illustrated with respect to FIGS. 5C, 5D, 6D, 7C, 7D, 8C, and 9C, the number of gate lines can be reduced by the distributive-driving to reduce the corresponding driving circuits (e.g., in the gate driver 202) and the scan period of each subpixel. On the other hand, the number of source lines are increased accordingly. To avoid increasing the number of data channels provided by control logic 104, a source-demultiplexing scheme may be applied in conjunction with the distributive-driving scheme. As shown in FIG. 10, control logic 104 may provide display data, either in its original form (e.g., original display data 106) or in its converted form (e.g., converted display data 416) in multiple data channels, for example, kN data channels via kN output pins. In this embodiment, demultiplexing module 1002 may be operatively coupled to the data channels and route the display data to multiple source lines (e.g., (k/x)N source lines) via source driver 204. In the embodiments in which x is between 0 and 1, the number of the data channels (e.g., kN) is smaller than the number of the source lines (e.g., (k/x)N). Thus, demultiplexing module 1002 may cause display data in each data channel to be provided to multiple source lines in different clock periods. It is to be appreciated that although the source-demultiplexing scheme may cause the scan period of each subpixel to be reduced, because the number of gate lines is reduced by the distributive-driving as well, the overcall scan period of each subpixel may remain the same. Consequently, the distributive-driving with source-demultiplexing can optimize the timing specification of display panels and help to achieve the narrow-bezel or bezel-less designs of display panels. In some embodiments, demultiplexing module 1002, control logic 104, source driver 204, and gate driver 202 may be manufactured in a COF package, such as a single-layer COF package.
FIG. 11 is a block diagram illustrating one example of demultiplexing module 1002 shown in FIG. 10 in accordance with an embodiment. In this embodiment, demultiplexing module 1002 includes a selecting unit 1102 and kN demultiplexers 1104. Selecting unit 1102 may be part of display 102, such as on the display panel, or may be part of control logic 104. Selecting unit 1102 may be configured to generate kN sets of selecting signals for kN demultiplexers 1104, respectively. Each demultiplexer 1104 may be part of source driver 204 and operatively coupled to selecting unit 1102 to receive the respective set of selecting signal. Depending on the value of x, each demultiplexer 1104 may be any suitable 1:X demultiplexer, where X=(1/x) and x is a fraction between 0 and 1. Each demultiplexer 1104 may be operatively coupled to one data channel and 1/x source lines. Each demultiplexer 1104 may be configured to receive input display data from one of the kN data channels and provide output display data to one of the 1/x source lines at each clock period based on the respective set of selecting signals from selecting unit 1102.
In this embodiment, DEMUX 1 may be operatively coupled to data channel 1 and receive input display data from data channel 1. DEMUX 1 may be operatively coupled to 1/x source lines S11 to S1(1/x) and provide output display data to one of the source lines S11 to S1(1/x) at each clock period based on the respective set of selecting signals from selecting unit 1102. Similarly, DEMUX kN may be operatively coupled to data channel kN and receive input display data from data channel kN. DEMUX kN may be operatively coupled to 1/x source lines S(kN)1 to S(kN)(1/x) and provide output display data to one of the source lines S(kN)1 to S(kN)(1/x) at each clock period based on the respective set of selecting signals from selecting unit 1102. For example, when x equals to ½, each of DEMUX 1 to DEMUX kN may be a 1:2 demultiplexer that can provide output display data to one of the two source lines at each clock period.
FIG. 12A is a depiction of an arrangement of gate lines and source lines for distributive-driving with source-demultiplexing of subpixels in the example arrangement shown in FIG. 5A in accordance with an embodiment. The arrangement of gate lines and source lines for distributive-driving in FIG. 12A is similar to the example shown in FIG. 5D in which the number of gate lines is decreased by the factor x equal to ¾ compared with the number of rows of pixels, while the number of source lines is increased by the factor 1/x equals to 4/3 compared with the number of columns of pixels. It is to be appreciated that although the connections representing the gate lines shown in FIG. 12A appear to be different from those in FIG. 5D, the logical connections of gate lines between subpixels are the same in FIG. 12A and FIG. 5D.
Different from the example in FIG. 5D, the source-demultiplexing scheme is applied in this embodiment. Thus, two source lines may be operatively coupled to a 1:2 demultiplexer and receive display data from the same data channel in different clock periods. For example, the source lines S1a and S1b may receive display data from data channel 1, and the source lines S8a and S8b may receive display data from data channel 8. As a result, only one half of the number of data channels may be needed compared with the number of source lines on the display panel. In FIGS. 12A, subpixels labeled with the same source line number (e.g., S1a, S1b, . . . , S8a, S8b) are connected by the same corresponding source line.
FIG. 12B is a depiction of another arrangement of gate lines and source lines for distributive-driving with source-demultiplexing of subpixels in the example arrangement shown in FIG. 5A in accordance with an embodiment. The arrangement of gate lines and source lines for distributive-driving in FIG. 12B is similar to the example shown in FIG. 5C in which the number of gate lines is decreased by the factor x equal to ½ compared with the number of rows of pixels, while the number of source lines is increased by the factor 1/x equals to 2 compared with the number of columns of pixels. It is to be appreciated that although the connections representing the gate lines shown in FIG. 12B appear to be different from those in FIG. 5C, the logical connections of gate lines between subpixels are the same in FIG. 12B and FIG. 5C.
Different from the example in FIG. 5C, the source-demultiplexing scheme is applied in this embodiment. Thus, three source lines may be operatively coupled to a 1:3 demultiplexer and receive display data from the same data channel in different clock periods. For example, the source lines S1a, S1b, and S1c may receive display data from data channel 1, and the source lines S8a, S8b, and S8c may receive display data from data channel 8. As a result, only one third of the number of data channels may be needed compared with the number of source lines on the display panel. In FIGS. 12B, subpixels labeled with the same source line number (e.g., S1a, S1b, S1c, . . . , S8a, S8b, S8c) are connected by the same corresponding source line.
FIGS. 13A-13D are depictions of an arrangement of gate lines and source lines for distributive-driving with source-demultiplexing of subpixels in the example arrangement shown in FIG. 6A in accordance with an embodiment. The arrangement of gate lines and source lines for distributive-driving in FIGS. 13A-13D is similar to the example shown in FIG. 6D in which the number of gate lines is decreased by a factor x equal to ⅔ compared with the number of rows of pixels, while the number of source lines is increased by a factor 1/x equals to 3/2 compared with the number of columns of pixels. It is to be appreciated that although the connections representing the gate lines shown in FIGS. 13A-13D appear to be different from those in FIG. 6D, the logical connections of gate lines between subpixels are the same in each pf FIGS. 13A-13D and FIG. 6D. For example, FIGS. 13A-13C and FIG. 6D each represents the same logic connections of gate lines between subpixels although the appearances of those “solid lines” representing the logic connections are not identical in FIGS. 13A-13C and FIG. 6D. As described above, the actual wiring of the gate lines may be understood by a person of ordinary skill in the art based on the logical connections and may be different in different examples. In one example, FIG. 13C may also represent one example of the actual wiring of the gate lines, but any other suitable wiring of gate lines may be applied as well. The same logic connections of gate lines between subpixels may be represented without the “solid lines” used in FIGS. 13A-13C and FIG. 6D. For example in FIG. 13D, the logic connections of gate lines are the same as those in FIGS. 13A-13C and FIG. 6D as the subpixels labeled with the same gate line number (e.g., G1 and G2) are connected by the same corresponding gate line. The same understandings explained above shall be applied to all the examples described in the present disclosure.
Different from the example in FIG. 6D, the source-demultiplexing scheme is applied in this embodiment. Thus, two source lines may be operatively coupled to a 1:2 demultiplexer and receive display data from the same data channel in different clock periods. For example, the source lines S1a and S1b may receive display data from data channel 1, and the source lines S9a and S9b may receive display data from data channel 9. As a result, only one half of the number of data channels may be needed compared with the number of source lines on the display panel. In FIGS. 13A-13D, subpixels labeled with the same source line number (e.g., S1a, S1b, . . . , S9a, S9b) are connected by the same corresponding source line.
It is to be appreciated that FIGS. 12A, 12B, and 13A-13D are for the illustrative purpose only, and the distributive-driving with source-demultiplexing of display panel may be applied to subpixels in any of the example arrangements disclosed in the present disclosure or any other suitable arrangements. It is also to be appreciated that the number of source lines that can receive display data from the same data channel is also not limited to the examples shown in FIGS. 12A, 12B, and 13A-13D and can be any suitable number in different subpixel arrangements.
It is to be appreciated that the “array of pixels” disclosed herein is not limited to all the pixels on the display panel (i.e., the entire display panel) and may be a portion of all the pixels on the display panel. That is, the M rows of pixels in the “array of pixels” may be the same or less than the vertical resolution of display 102, and the N columns of pixels in the “array of pixels” may be the same or less than the horizontal resolution of display 102. For example, for a WQHD display panel with a resolution of 1440×2560 (i.e., the number of rows of pixels and the vertical resolution is 2560) and when x equals to 4/3, because 2560×(4/3) is not an integer, the “array of pixels” in this example may have 2559 rows (i.e., M=2559). Accordingly, the distributive-driving scheme may be applied to 2559 rows of pixels, and the number of gate lines for that particular “array of pixels” may be increased to 3412 (2559×(4/3)). As to the entire display panel, the last row of pixels may be operatively coupled to one gate line without distributive-driving so that the total number of gate lines is 3413 in this example. Similarly, when x equals to ⅔ in the example above, because 2560×(⅔) is not an integer, the “array of pixels” in this example may have 2559 rows (i.e., M=2559). Accordingly, the distributive-driving scheme may be applied to 2559 rows of pixels, and the number of gate lines for that particular “array of pixels” may be decreased to 1706 (2559×(⅔)). As to the entire display panel, the last row of pixels may be operatively coupled to one gate line without distributive-driving so that the total number of gate lines is 1707 in this example.
According to some aspects of the present disclosure, by applying the distributive-driving scheme disclosed herein to LCDs, the aperture ratio can be increased due to the reduction of the total length of metal lines in each subpixel under the same process design rules. Increasing the aperture ratio also increases the brightness of the LCDs and/or reduces the power consumption of the LCDs. In some embodiments, the shape of each subpixel approximates a square, i.e., the ratio between the pitch of the source lines and the pitch of the gate lines gets close to one. Thus, the total length of metal lines in each subpixel (the segments of source lines and gate lines in the subpixel) can be reduced.
According to some aspects of the present disclosure, by applying the distributive-driving scheme disclosed herein to LCDs, the pixel density can be increased due to the increase of the source line pitch/spacing under the same process design rules. In the conventional LCDs, such as the ones with the RGB-strip subpixel arrangement, the source line pitch/spacing is significantly smaller than the gate line pitch/spacing. Thus, the pixel density is limited by the smallest source line pitch/spacing that can be mass produced under certain process design rules. By increasing the source line pitch/spacing (relatively compared with the gate line pitch/spacing) by the distributive-driving scheme disclosed herein, the pixel density of LCDs can be increased.
FIG. 14 is a cross-sectional view illustrating one example of an LCD apparatus 1400 in accordance with an embodiment. LCD apparatus 1400 may be any suitable type of LCDs, such as a twisted nematic (TN) LCD, in-plane switching (IPS) LCD, advanced fringe field switching (AFFS) LCD, vertical alignment (VA) LCD, advanced super view (ASV) LCD, blue phase mode LCD, passive-matrix (PM) LCD, or any other suitable LCDs. LCD apparatus 1400 may include a display panel 1402 and a backlight panel 1404, which are operatively coupled to control logic 104 via driving circuits 1406. Backlight panel 1404 includes light sources 1408 for providing light to display panel 1402, such as but not limited to incandescent light bulbs, LEDs, EL panel, cold cathode fluorescent lamps (CCFLs), and hot cathode fluorescent lamps (HCFLs), to name a few.
Display panel 1402 may be, for example, a TN panel, an IPS panel, an AFFS panel, a VA panel, an ASV panel, or any other suitable display panel. In this example, display panel 1402 includes a color filter layer 1410, a pixel circuit layer 1412, and a liquid crystal (LC) layer 1414 disposed between color filter layer 1410 and pixel circuit layer 1412. As shown in FIG. 14, color filter layer 1410 includes a plurality of color filters A, B, C, and D corresponding to a plurality of subpixels A, B, C, and D, respectively. A, B, C, and D in FIG. 14 denote various combinations of four different colors, such as but not limited to, red, green, blue, yellow, cyan, magenta, or white. Color filter layer 1410 may also include a black matrix disposed between the color filters A, B, C, and D as shown in FIG. 14. The black matrix, as the borders of the subpixels A, B, C, and D, is used for blocking the light coming out from the parts outside the color filters A, B, C, and D. LC layer 1414 is divided into a plurality of LC regions A, B, C, and D, each of which corresponds to a respective one of the color filters A, B, C, and D. In this example, pixel circuit layer 1412 includes a plurality of pixel circuits A, B, C, and D corresponding to the plurality of subpixels A, B, C, and D, respectively. Each of the pixel circuits A, B, C, and D is configured to drive a respective one of the LC regions A, B, C, and D so as to control the light passing through the respective filter A, B, C, or D. Operations of pixel circuits A, B, C, and D in pixel circuit layer 1412 are controlled by driving signals 1416 from driving circuits 1406 (e.g., including gate driving circuit 202 and source driving circuit 204). Display panel 1402 may include any other suitable component, such as one or more glass substrates, polarization layers, or a touch panel as known in the art.
As shown in FIG. 14, each of the plurality of subpixels A, B, C, and D is constituted by at least a color filter, a corresponding pixel circuit, and the LC region between the corresponding color filter and pixel circuit. The color filters A, B, C, and D may be formed of a resin film in which dyes or pigments having the desired color are contained. Depending on the characteristics (e.g., color, thickness, etc.) of the respective color filter, a subpixel may present a distinct color and brightness. As described above, the number of subpixels on display panel 1402 may be k times of the number of the pixels of display panel 1402. Thus, the number of color filters in color filter layer 1410 on display panel 1402 may be k times of the number of the pixels of display panel 1402 as well.
FIG. 15A is a circuit diagram illustrating one example of a pixel circuit 1502 of LCD apparatus 1400 in accordance with an embodiment. Pixel circuit 1502 may include a switching element, e.g., a TFT, and a storage capacitor Cs. The storage capacitor Cs is electrically connected in parallel to an LC region capacitor CLC. The gate of the TFT is electrically connected to a gate line 1506 and the source of the TFT is electrically connected to a source line 1508. The drain of the TFT is electrically connected to one electrode of storage capacitor Cs and one electrode of the LC region capacitor CLC. The other electrodes of storage capacitor Cs and LC region capacitor CLC may be electrically connected, for example, to the ground or to the backplane of the display panel.
FIG. 15B is a layout diagram illustrating one example of a subpixel of LCD apparatus 1400 in accordance with an embodiment. In this example, the subpixel has pixel circuit 1502, a segment of gate line 1506, and a segment of source line 1508 as described in FIG. 15A. In FIG. 15B, the aperture is the light transparent part and is designated for the placement of the LC region. The TFT and storage capacitor Cs in pixel circuit 1502 and the segments of gate line 1506 and source line 1508 in the subpixel are non-light transparent. The ratio between the transparent portion (aperture) of the subpixel and its surrounding electronics (e.g., TFT, capacitor, and metal lines) is called aperture ratio (or fill factor). In some embodiments, the aperture ratio can be increased by reducing the area of the TFT and/or the storage capacitor Cs.
In some embodiments, the aperture ratio can be increased by reducing the area of the metal lines in the subpixel. As shown in FIG. 15B, the non-light transparent area in each subpixel includes a segment of the source line in the subpixel and a segment of the gate line in the subpixel. For the segment of the source line, the area can be calculated by the source line width and the source line length in the subpixel, which equals the pitch of the gate lines (the gate line width plus the gate line spacing). Similarly, for the segment of the gate line, the area can be calculated by the gate line width and the gate line length in the subpixel, which equals the pitch of the source lines (the source line width plus the source line spacing). In some embodiments, the area of the metal lines can be reduced by reducing the source line width and/or the gate line width. In some embodiments, the area of the metal lines can be reduced by reducing the source line length and/or the gate line length, i.e., the gate line pitch and/or the source line pitch.
FIG. 16A is a depiction of an arrangement of gate lines and source lines for driving subpixels in an example arrangement of LCD apparatus 1400. In this example, the LCD display panel includes an array of subpixels in a first color A, a second color B, and a third color C, arranged in rows and columns. A, B, and C denote various combinations of three different colors, such as but not limited to, red, green, blue, yellow, cyan, magenta, or white. It is to be appreciated that the “array,” “row,” and “column” of subpixels may not correspond to the “array,” “row,” and “column” of pixels as described above. In this example, the array of subpixels includes a subpixel repeating group represented by A-B-C, which repeats itself in both the row/horizontal direction and the column/vertical direction. One example of such subpixel arrangement is known as the “real-RGB” or “RGB strips” arrangement as described above with respect to FIG. 7A.
FIG. 16A illustrates a portion of the LCD display panel including 12 subpixels. In this example, the ratio k of subpixels to pixels is three (k=3, e.g., the adjacent A, B, and C subpixels in the same row constitute one pixel), and the resolution of the portion of the display panel is 2×2. The array of pixels in this example includes four pixels P11, P12, P21, and P22, which are arranged in two rows and are operatively coupled to two gate lines G1-G2. As to the source lines, the array of pixels P11, P12, P21, and P22 are arranged in two columns, each of which is operatively coupled to three source lines. That is, the array of pixels in this example are operatively coupled to six source lines S1 to S6. The number of the gate lines (2) is the same as the number of the rows of pixels (2), and the number of the source lines (6) is the same as the number of the columns of pixels multiplied by the ratio k (2×3).
As shown in FIG. 16A, the non-light transparent area of each pixel includes the area of the metal lines, e.g., the segments of the gate line and source line (G1-G2 and S1-S6), and the area of the pixel circuit (represented as the black box at the bottom-left corner of each subpixel). The remaining area of each pixel (aperture) is transparent to the light.
In some embodiments, each pixel P11, P12, P21, or P22 is in a substantially square shape. As each pixel P11, P12, P21, or P22 consists of three adjacent subpixels having the same shape and size arranged in the same row, each subpixel is in a substantially rectangle shape with the ratio between the length (in the column direction) and the width (in the row direction) being about three. That is, the ratio between the gate line pitch and the source line pitch is about three, and the ratio between the source line pitch and the gate line pitch is about ⅓. In one example, for an LCD display panel having a pixel density of 705 pixels per inch (PPI), the area of the pixel circuit (e.g., including a TFT and a storage capacitor) is about 100 μm2, and the size of the subpixel is about 36 μm (length) by about 12 μm (width). The width of each metal line (e.g., each source line or gate line) is about 5 μm. In this example, the ratio between the gate line pitch and the source line pitch is about three, and the ratio between the source line pitch and the gate line pitch is about ⅓. The aperture ratio in this example is about 27%. In another example, by decreasing the width of each metal line from about 5 μm to about 3 μm and keeping all other conditions the same, the aperture ratio can be increased from about 27% to about 46%.
It is to be appreciated that in some embodiments, the width of each metal line cannot be further reduced due to the process design rules. In order to increase the aperture ratio, the distributive-driving scheme disclosed herein can be applied to reduce the total length of the metal lines in each subpixel. FIG. 16B is a depiction of an arrangement of gate lines and source lines for distributive-driving of subpixels in an example arrangement of LCD apparatus 1400 in accordance with an embodiment. The same as the example in FIG. 16A, in this example, a portion of the LCD display panel includes 12 subpixels corresponding to an array of four pixels P11, P12, P21, and P22. The ratio k of subpixels to pixels is three (k=3, e.g., the adjacent A, B, and C subpixels in a delta arrangement constitute one pixel), and the resolution of the display panel is 2×2.
The example in FIG. 16B differs from the example in FIG. 16A, because the array of pixels P11, P12, P21, and P22 are operatively coupled to three gate lines G1-G3, which is one and a half (3/2) times of the number of the rows of pixels (2). The number of the gate lines in this embodiment may be represented as (3/2)M, where x=3/2 (a fraction larger than 1), and M is the number of the rows of pixels. For example, every two rows of pixels are driven by gate driving circuit 202 via three gate lines. As to the source lines, the array of pixels P11, P12, P21, and P22 are operatively coupled to four source lines S1-S4, which is two thirds (⅔) of the number of the columns of pixels multiplied by the ratio k (6). The number of the source lines in this embodiment may be represented as (⅔)kN, where k is the ratio of subpixels to pixels, and N is the number of the columns of pixels. In other words, the number of the source lines in the example in FIG. 16A is reduced by one third (⅓) in the example in FIG. 16B by the distributive-driving scheme disclosed herein. As a result, the ratio between the length (in the column direction) and the width (in the row direction) of each subpixel is about 4/3. That is, the ratio between the gate line pitch and the source line pitch is about 4/3, and the ratio between the source line pitch and the gate line pitch is about ¾.
In one example, for an LCD display panel having a pixel density of 705 PPI, the area of the pixel circuit (e.g., including a TFT and a storage capacitor) is about 100 μm2, and the size of the subpixel is about 24 μm (length) by about 18 μm (width). The width of each metal line (e.g., each source line or gate line) is about 5 μm. In this example, the ratio between the gate line pitch and the source line pitch is about 4/3, and the ratio between the source line pitch and the gate line pitch is about ¾. The aperture ratio in this example is about 34%. Compared with the example described above with respect to FIG. 16A, for the portion of the LCD display panel having the same display resolution (2×2) and the same number of subpixels (12), just by applying the distributive-driving scheme to the subpixel arrangement (while keeping the same pixel circuit size and the width of each metal line), the aperture ratio can be increased from about 27% to about 34% due to the reduced metal line length (e.g., from about 48 μm to about 42 μm in each subpixel).
In general, the distributive-driving scheme disclosed herein can adjust the ratio between the source line pitch and the gate line pitch to make it close to one. In some embodiments, the ratio is larger than ½, such as about ¾ or about 9/8. In some embodiments, the ratio is about one.
FIGS. 17A-17B are depictions of example color filter arrangements (delta arrangements) for distributive-driving of subpixels of LCD apparatus 1400 in accordance with various embodiments. A, B, and C denote three different color filters, such as but not limited to, red, green, blue, yellow, cyan, magenta, or white color filter. The color filter arrangement in FIG. 17A can be used in the example described above in FIG. 16B. In this example, the plurality of color filters are arranged in a repeating pattern, and two adjacent rows of the color filters are staggered with each other in the column direction. In some embodiments, two adjacent rows of the color filters are staggered with each other by one half of the height (length in the column direction) of each of the color filters. In other embodiments, the offset of the adjacent rows of the color filters can be one fourth or any fraction of the height of each color filter.
FIG. 17B illustrates another example of color filter arrangement. A, B, and C denote various combinations of three different color filters, such as but not limited to, red, green, blue, yellow, cyan, magenta, or white color filter. In this example, the plurality of color filters are arranged in a repeating pattern, and two adjacent columns of the color filters are staggered with each other in the row direction. In some embodiments, two adjacent columns of the color filters are staggered with each other by one half of the height (length in the column direction) of each of the color filters. In other embodiments, the offset of the adjacent columns of the color filters can be one fourth or any fraction of the height of each color filter. In some embodiments, the color filter arrangement in FIG. 17B may be viewed as the color filter arrangement in FIG. 17A rotated by 90 degrees.
FIGS. 18A-18C are depictions of arrangements of gate lines, source lines, and pixel circuits for distributive-driving of subpixels in the example arrangement shown in FIG. 16B in accordance with an embodiment. The color filter arrangements in the three examples in FIGS. 18A-18C are the same, such as the example shown in FIG. 17A. Under the same color filter layout, the different pixel circuit placements (with the same area for each pixel circuit regardless of its shape and arrangement) and/or the different gate line placements may affect the visual quality and the metal line layout complexity.
In the example of FIG. 18A, each gate line G1-G3 and source line S1-S4 is a straight line. Each source line S1-S4 is arranged between adjacent columns of color filters, i.e., along the left and right edges of the color filters. Each gate line G1-G3 is arranged across color filters in the row direction. As to the pixel circuits, at least two of the pixel circuits have different relative locations with respect to their respective color filters. For example, some pixel circuits may be arranged at the bottom of the corresponding color filter, while some pixel circuits may be arranged at the top of the corresponding color filters. Each gate line does not cross the pixel circuit regions. In this example, the straight-line shape of each gate line makes the metal line layout less complex, while the unbalanced subpixel placement may affect the color uniformity.
In the example of FIG. 18B, each gate line G1-G3 and source line S1-S4 is a straight line. Each source line S1-S4 is arranged between adjacent columns of color filters, i.e., along the left and right edges of the color filters. Each gate line G1-G3 is arranged across color filters in the row direction. As to the pixel circuits, at least two of the pixel circuits have different relative locations with respect to their respective color filters. For example, each pixel circuit in the odd columns of subpixels may be arranged with the same relative location with respect to the corresponding color filters in the same column, e.g., at the bottom-left corners. Each pixel circuit in the even columns of subpixels may be arranged with the same relative location with respect to the corresponding color filters in the same column, e.g., at the top-left corners. As a result, pixel circuits may be aligned in the row direction even though the adjacent rows of color filters are staggered with each other. Each gate line crosses the pixel circuit regions. In this example, the straight-line shape of each gate line and the aligned pixel circuits in the row direction make the metal line and pixel circuit layouts less complex, while the unbalanced subpixel placement may affect the color uniformity.
In the example of FIG. 18C, each source line S1-S4 is a straight line arranged between adjacent columns of color filters, i.e., along the left and right edges of the color filters. Each gate line G1-G3 is a polyline arranged along the top and bottom edges of the color filters. As to the pixel circuits, each of the pixel circuits has the same relative location with respect to the respective one of the color filters. For example, each pixel circuit may be arranged at the bottom of the corresponding color filter. Each gate line thus does not cross the pixel circuit regions. In this example, the perfect balanced subpixel placement does not affect the color uniformity, while the polyline shape of each gate line makes the metal line layout more complex.
Although in the examples described with respect to FIGS. 16A-16B, the ratio k of subpixels to pixels is three, it is to be appreciated that in other examples, the ratio k can be any integer larger than one, such as two or four. FIG. 19A is a depiction of a color filter arrangement of LCD apparatus 1400. In this example, for “real-RGB” or “RGB strips” arrangement of color filters on LCD display panels, the ratio k of subpixels to pixels may be two. For example, two adjacent subpixels in the same row may form one pixel 1902. FIG. 19B is a depiction of an example color filter arrangement for distributive-driving of subpixels of LCD apparatus 1400 in accordance with an embodiment. In this example, the ratio k of subpixels to pixels may be two as well for the delta arrangement of color filters. Two subpixels may form one pixel 1904.
Also, integrated circuit design systems (e.g., work stations) are known that create wafers with integrated circuits based on executable instructions stored on a computer-readable medium such as but not limited to CDROM, RAM, other forms of ROM, hard drives, distributed memory, etc. The instructions may be represented by any suitable language such as but not limited to hardware descriptor language (HDL), Verilog or other suitable language. As such, the logic, units, and circuits described herein may also be produced as integrated circuits by such systems using the computer-readable medium with instructions stored therein.
For example, an integrated circuit with the aforedescribed logic, units, and circuits may be created using such integrated circuit fabrication systems. The computer-readable medium stores instructions executable by one or more integrated circuit design systems that causes the one or more integrated circuit design systems to design an integrated circuit. In one example, the designed integrated circuit includes a color filter layer, a liquid crystal (LC) layer, and a pixel circuit layer. The color filter layer includes a plurality of color filters corresponding to an array of pixels arranged in M rows and N columns. The number of the color filters is k times of the number of the pixels. The LC layer is divided into a plurality of LC regions, each of which corresponds to a respective one of the color filters. The pixel circuit layer includes a plurality pixel circuits, each of which is configured to drive a respective one of the LC regions. The pixel circuit layer also includes xM gate lines and (k/x)N source lines, where x is a fraction larger than 1, and each of xM and (k/x)N is a positive integer.
In another example, the designed integrated circuit includes a color filter layer, an LC layer, a pixel circuit layer, a gate driving circuit, a source driving circuit, and control logic. The color filter layer includes a plurality of color filters corresponding to an array of pixels arranged in M rows and N columns. The number of the color filters is k times of the number of the pixels. The LC layer is divided into a plurality of LC regions, each of which corresponds to a respective one of the color filters. The pixel circuit layer includes a plurality pixel circuits, each of which is configured to drive a respective one of the LC regions. The pixel circuit layer includes xM gate lines and (k/x)N source lines, where x is a fraction larger than one, and each of xM and (k/x)N is a positive integer. The gate driving circuit is operatively coupled to the pixel circuit layer via the xM gate lines and configured to scan the plurality of pixel circuits. The source driving circuit is operatively coupled to the pixel circuit layer via the (k/x)N source lines and configured to write display data in a frame to the plurality of pixel circuits. The control logic is operatively coupled to the gate driving circuit and source driving circuit and configured to receive original display data and convert the original display data into converted display data based on the (k/x)N source lines. The control logic is also configured to provide a first set of control signals to the gate driving circuit to control the gate driving circuit to scan the plurality of pixel circuits via the xM gate lines. The control logic is further configured to provide a second set of control signals to the source driving circuit to control the source driving circuit to write the converted display data to the plurality of pixel circuits.
The above detailed description of the disclosure and the examples described therein have been presented for the purposes of illustration and description only and not by limitation. It is therefore contemplated that the present disclosure cover any and all modifications, variations or equivalents that fall within the spirit and scope of the basic underlying principles disclosed above and claimed herein.
