# DATA PROCESSING APPARATUS AND METHOD

A data processing apparatus includes a group-wise interleaving unit that performs group-wise interleaving; and a block interleaving unit that performs block interleaving in such a manner that an LDPC code obtained by performing the group-wise interleaving is written in m number of columns as storage regions arranged in the row direction. A type of the block interleaving includes a type A and a type B. A MODCOD which is a combination of the LDPC code and the modulation scheme includes a MODCOD-A which is a MODCOD based on the assumption that the block interleaving of the type A is performed, and a MDOCOD-B which is a MDOCOD based on the assumption that the block interleaving of the type B is performed.

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**Description**

**CROSS-REFERENCE TO RELATED APPLICATION**

This application is a continuation of U.S. application Ser. No. 16/030,350, filed Jul. 9, 2018, which is a continuation of U.S. application Ser. No. 14/840,888 filed Aug. 31, 2015, which claims the benefit of priority of U.S. Provisional Application No. 62/102,941, filed Jan. 13, 2015, and U.S. Provisional Application Ser. No. 62/105,494, filed Jan. 20, 2015, the entire contents of all of which are incorporated herein by reference.

**BACKGROUND**

The present technology relates to a data processing apparatus and a data processing method, and more specifically, it relates to a data processing apparatus and a data processing method capable of allowing a plurality of block interleaving methods to efficiently coexist in data transmission using, for example, an LDPC code.

Some information described in the present specification and drawings is offered from Samsung Electronics Co., Ltd. (hereinafter, referred to as Samsung), LGE Inc., the NERC, and CRC/ETRI (specified in the drawing).

A low density parity check (LDPC) code has high error correcting capability, and has been widely used in transmission schemes of digital broadcasting such as digital video broadcasting (DVB)-S.2, DVB-T.2 or DVB-C.2 in Europe, and advanced television systems committee (ATSC) 3.0 in the United States (for example, see DVB-S2X: ETSI EN 302 307-2 V1.1.1 (2014-10)) in recent years.

According to recent research, similarly to a turbo code, when the LDPC code is used, it has been found that it is possible to obtain performance approximate to the Shannon limit having long code length. Since the LDPC code has the feature that a minimum distance is proportional to a code length, the LDPC code features good block error probability characteristics, and has a merit that a so-called error floor phenomenon which is observed in decoding characteristics on the turbo code does not occur.

**SUMMARY**

For example, in the data transmission using the LDPC code, the LDPC code is changed (is symbolized) to a symbol of quadrature modulation (digital modulation) such as quadrature phase shift keying (QPSK), and the symbol is mapped to a signal point of quadrature modulation and is transmitted. The data transmission using the LDPC code described above has been widely used all over the world.

However, when bit interleaving is performed on the LDPC code, a plurality of block interleaving methods may be adopted, and the plurality of block interleaving methods have to efficiently coexist.

The present technology has been made in view of such circumstances, and it is possible to allow a plurality of block interleaving methods to efficiently coexist in data transmission using an LDPC code.

According to an embodiment of the present technology, there is provided a first data processing apparatus/method. The first data processing apparatus/method is a data processing apparatus/method including a group-wise interleaving unit/group-wise interleaving that performs group-wise interleaving which interleaves an LDPC code having a code length (N) of 16,200 bits or 64,800 bits for every bit group of 360 bits; and a block interleaving unit/block interleaving that performs block interleaving in such a manner that an LDPC code obtained by performing the group-wise interleaving is written in m number of columns as storage regions arranged in the row direction, m bits are obtained by respectively reading the LDPC code from m number of columns bit by bit, and the m bits are interleaved into one symbol corresponding to any one of 2^{m }number of signal points defined by a modulation scheme. A type of the block interleaving includes a type A in which the writing of an LDPC code obtained by performing the group-wise interleaving in the column direction of the columns is iteratively performed on m number of columns, and a type B in which the writing of an LDPC code obtained by performing the group-wise interleaving in the row direction of m number of columns for every bit group is iteratively performed. A MODCOD which is a combination of the LDPC code and the modulation scheme includes a MODCOD-A which is a MODCOD based on the assumption that the block interleaving of the type A is performed, and a MDOCOD-B which is a MDOCOD based on the assumption that the block interleaving of the type B is performed. When the block interleaving of the type A is performed on the LDPC code of the MODCOD-B, the group-wise interleaving unit/group-wise interleaving performs the group-wise interleaving on the LDPC code of the MODCOD-B such that the same block interleaving result as the block interleaving result obtained when the block interleaving of the type B is performed is obtained, or when the block interleaving of the type B is performed on the LDPC code of the MODCOD-A, the group-wise interleaving unit/group-wise interleaving performs the group-wise interleaving on the LDPC code of the MDOCOD-A such that the same block interleaving result as the block interleaving result obtained when the block interleaving of the type A is performed is obtained.

In the first data processing apparatus/method, group-wise interleaving which interleaves an LDPC code having a code length (N) of 16,200 bits or 64,800 bits for every bit group of 360 bits is performed, and block interleaving is performed in such a manner that an LDPC code obtained by performing the group-wise interleaving is written in m number of columns as storage regions arranged in the row direction, m bits are obtained by respectively reading the LDPC code from m number of columns bit by bit, and the m bits are interleaved into one symbol corresponding to any one of 2^{m }number of signal points defined by a modulation scheme. A type of the block interleaving includes a type A in which the writing of an LDPC code obtained by performing the group-wise interleaving in the column direction of the columns is iteratively performed on m number of columns, and a type B in which the writing of an LDPC code obtained by performing the group-wise interleaving in the row direction of m number of columns for every bit group is iteratively performed. A MODCOD which is a combination of the LDPC code and the modulation scheme includes a MODCOD-A which is a MODCOD based on the assumption that the block interleaving of the type A is performed, and a MDOCOD-B which is a MDOCOD based on the assumption that the block interleaving of the type B is performed. When the block interleaving of the type A is performed on the LDPC code of the MODCOD-B, in the group-wise interleaving, the group-wise interleaving is performed on the LDPC code of the MODCOD-B such that the same block interleaving result as the block interleaving result obtained when the block interleaving of the type B is performed is obtained, or when the block interleaving of the type B is performed on the LDPC code of the MODCOD-A, in the group-wise interleaving, the group-wise interleaving is performed on the LDPC code of the MDOCOD-A such that the same block interleaving result as the block interleaving result obtained when the block interleaving of the type A is performed is obtained.

According to another embodiment of the present technology, there is provided a second data processing apparatus/method. The second data processing apparatus/method is a data processing apparatus/method including a block deinterleaving unit/block deinterleaving that performs block deinterleaving which returns m bits of a symbol obtained from data transmitted from a transmission apparatus to an LDPC code obtained by performing group-wise interleaving; and a group-wise deinterleaving unit/group-wise deinterleaving that performs group-wise deinterleaving which returns the arrangement of the LDPC code obtained by performing the group-wise interleaving on the original arrangement. The transmission apparatus includes a group-wise interleaving unit that performs group-wise interleaving which interleaves an LDPC code having a code length (N) of 16,200 bits or 64,800 bits for every bit group of 360 bits, and a block interleaving unit that performs block interleaving in such a manner that an LDPC code obtained by performing the group-wise interleaving is written in m number of columns as storage regions arranged in the row direction, m bits are obtained by respectively reading the LDPC code from m number of columns bit by bit, and the m bits are interleaved into one symbol corresponding to any one of 2^{m }number of signal points defined by a modulation scheme. A type of the block interleaving includes a type A in which the writing of an LDPC code obtained by performing the group-wise interleaving in the column direction of the columns is iteratively performed on m number of columns, and a type B in which the writing of an LDPC code obtained by performing the group-wise interleaving in the row direction of m number of columns for every bit group is iteratively performed. A MODCOD which is a combination of the LDPC code and the modulation scheme includes a MODCOD-A which is a MODCOD based on the assumption that the block interleaving of the type A is performed, and a MDOCOD-B which is a MDOCOD based on the assumption that the block interleaving of the type B is performed. When the block interleaving of the type A is performed on the LDPC code of the MODCOD-B, the group-wise interleaving unit performs the group-wise interleaving on the LDPC code of the MODCOD-B such that the same block interleaving result as the block interleaving result obtained when the block interleaving of the type B is performed is obtained, or when the block interleaving of the type B is performed on the LDPC code of the MODCOD-A, the group-wise interleaving unit performs the group-wise interleaving on the LDPC code of the MDOCOD-A such that the same block interleaving result as the block interleaving result obtained when the block interleaving of the type A is performed is obtained.

In the second data processing apparatus/method, block deinterleaving which returns m bits of a symbol obtained from data transmitted from a transmission apparatus to an LDPC code obtained by performing group-wise interleaving is performed, and group-wise deinterleaving which returns the arrangement of the LDPC code obtained by performing the group-wise interleaving on the original arrangement is performed. The transmission apparatus includes a group-wise interleaving unit that performs group-wise interleaving which interleaves an LDPC code having a code length (N) of 16,200 bits or 64,800 bits for every bit group of 360 bits, and a block interleaving unit that performs block interleaving in such a manner that an LDPC code obtained by performing the group-wise interleaving is written in m number of columns as storage regions arranged in the row direction, m bits are obtained by respectively reading the LDPC code from m number of columns bit by bit, and the m bits are interleaved into one symbol corresponding to any one of 2^{m }number of signal points defined by a modulation scheme. A type of the block interleaving includes a type A in which the writing of an LDPC code obtained by performing the group-wise interleaving in the column direction of the columns is iteratively performed on m number of columns, and a type B in which the writing of an LDPC code obtained by performing the group-wise interleaving in the row direction of m number of columns for every bit group is iteratively performed. A MODCOD which is a combination of the LDPC code and the modulation scheme includes a MODCOD-A which is a MODCOD based on the assumption that the block interleaving of the type A is performed, and a MDOCOD-B which is a MDOCOD based on the assumption that the block interleaving of the type B is performed. When the block interleaving of the type A is performed on the LDPC code of the MODCOD-B, the group-wise interleaving unit performs the group-wise interleaving on the LDPC code of the MODCOD-B such that the same block interleaving result as the block interleaving result obtained when the block interleaving of the type B is performed is obtained, or when the block interleaving of the type B is performed on the LDPC code of the MODCOD-A, the group-wise interleaving unit performs the group-wise interleaving on the LDPC code of the MDOCOD-A such that the same block interleaving result as the block interleaving result obtained when the block interleaving of the type A is performed is obtained.

The data processing apparatuses may be one independent apparatus, or may be internal blocks constituting one apparatus.

According to the present technology, it is possible to allow a plurality of block interleaving methods to efficiently coexist in data transmission using an LDPC code.

The effects described herein are not necessarily limited, and may be any one of the effects described in the present disclosure.

**BRIEF DESCRIPTION OF THE DRAWINGS**

**DETAILED DESCRIPTION OF EMBODIMENTS**

**1. First Embodiment**

Hereinafter, an embodiment of the present technology will be described, but an LDPC code will be described prior to the description.

LDPC Code

The LDPC code is a linear code, and is not necessarily a two-dimensional code. Here, it will be described that the LDPC code is a two-dimensional code.

The LDPC code has a greatest feature in that a parity check matrix which defines the LDPC code is a sparse matrix. Here, the sparse matrix refers to a matrix (matrix in which most of the elements are zero) in which the number of “1”s which are elements in a matrix is extremely small.

In the parity check matrix H of

In the encoding (LDPC encoding) using the LDPC code, for example, a codeword (LDPC code) is generated by generating a generator matrix G based on the parity check matrix H and multiplying two-dimensional information bits by the generator matrix G.

Specifically, an encoding device that performs the LDPC encoding calculates the generator matrix G in which the expression GH^{T}=0 is established between a transposed matrix H_{T }of the parity check matrix H and the generator matrix. Here, when the generator matrix G is a K×N matrix, the encoding device generates an N-bit codeword c (=uG) by multiplying by the generator matrix G by a K-bit string (vector u) of the information bits. The codeword (LDPC code) generated by the encoding device is received by a reception side through a predetermined communication channel.

The LDPC code can be decoded by a message passing algorithm which is called probabilistic decoding suggested by Gallager and uses belief propagation on a so-called Tanner graph which includes a variable node (referred to as a message node) and a check node. Hereinafter, appropriately, the variable node and the check node are simply referred to as a node.

Hereinafter, a real number value (reception LLR) obtained by representing the likelihood that the value of an i-th code bit of the LDPC code (one codeword) received by the reception side will be “0” using a log-likelihood ratio is appropriately referred to as a reception value u_{0i}. A message output from the check node is represented as u_{j}, and a message output from the variable node is represented as v_{i}.

As shown in **11**, after the LDPC code is received, the message (check node message) u_{j }is initialized by setting its value to “0”, a variable k expressed as an integer as a counter of an iteration process is initialized by setting its value to “0”, and the procedure proceeds to step S**12**. In step S**12**, the message (variable node message) v_{i }is obtained by performing a calculation (variable node calculation) represented by Expression (1) based on the reception value u_{0i }obtained by receiving the LDPC code, and the message u_{j }is obtained by performing a calculation (check node calculation) represented by Expression (2) based on the message v_{i}.

Where, d_{v }and d_{c }in Expression (1) and Expression (2) are respectively parameters, which indicate the number of “1”s in the longitudinal direction (column) and the transverse direction (row) of the parity check matrix H and can be arbitrarily selected. For example, in the case of the LDPC code ((3, 6) LDPC code) for the parity check matrix H shown in _{v}=3, and d_{c}=6.

In the variable node calculation of Expression (1) and the check node calculation of Expression (2), since messages input from edges (lines connecting the variable node and the check node) to respectively output messages are not used as calculation targets, a calculation range is from 1 to d_{v}−1 or from 1 to d_{c}−1. A table of a function R(v_{1}, v_{2}) represented by Expression (3) defined by one output for two inputs v_{1 }and v_{2 }is created in advance, and the check node calculation of Expression (2) is performed by continuously (recursively) using the table as shown in Expression (4).

*x=*2 tan *h*^{−1}{tan *h*(*v*_{1}/2)tan *h*(*v*_{2}/2)}=*R*(*v*_{1}*,v*_{2}) (3)

*u*_{j}*=R*(*v*_{1}*,R*(*v*_{2}*,R*(*v*_{3}*, . . . R*(*v*_{d}_{c}_{-2}*,v*_{d}_{c}_{-1})))) (4)

In step S**12**, the variable k is increased by “1”, and the procedure proceeds to step S**13**. In step S**13**, it is determined whether or not the variable k is greater than a predetermined iterative decoding number C. In step S**13**, when it is determined that the variable k is not greater than C, the procedure returns to step S**12**, and the same process is iterated.

In step S**13**, when it is determined that the variable k is greater than C, the procedure proceeds to step S**14**. Thereafter, the message v_{i }as a decoding result that is ultimately output is obtained by performing a calculation represented by Expression (5), and the obtained message is output. The decoding process of the LDPC code is ended.

Here, the calculation of Expression (5) is different from the variable node calculation of Expression (1), and is performed using the messages u_{j }from all edges that are connected to the variable node.

Similarly to

Here, in

That is, when an element in the j-th row and the i-th column is 1, an i-th variable node (“=” node) from the top and a j-th check node (“+” node) from the top are connected through an edge in

In a sum-product algorithm which is a method of decoding the LDPC code, the variable node calculation and the check node calculation are iteratively performed.

In the variable node, the message v_{1 }corresponding to the edge to be calculated is obtained using the variable node calculation of Expression (1) using the reception value u_{0i }and the messages u_{1 }and u_{2 }from the remaining edges connected to the variable node. Messages corresponding to other edges are similarly obtained.

Here, the check node calculation of Expression (2) can be rewritten as Expression (6) by using a relationship of an expression a×b=exp{ln(|a|)+ln(|b|)}×sign(a)×sign(b). In this case, sign(x) is 1 when x≥0, and is −1 when x<0.

In x≥0, when a function φ(x) is defined as the expression ϕ(x)=ln(tan h(x/2)), since the expression ϕ^{−1}(x)=2 tan h^{1}(e^{−x}) is established, Expression (6) can be modified into Expression (7).

In the check node, the check node calculation of Expression (2) is performed according to Expression (7).

That is, as shown in _{j }corresponding to the edge to be calculated is calculated by the check node calculation of Expression (7) using messages v_{1}, v_{2}, v_{3}, v_{4 }and v_{5 }from the remaining edges connected to the check node. Messages corresponding to other edges are similarly calculated.

The function ϕ(x) of Expression (7) can be expressed as the expression ϕ(x)=ln((e^{x}+1)/(e^{x}−1)), and when x>0, ϕ(x)=ϕ^{−1}(x). When the functions ϕ(x) and ϕ^{−1}(x) are implemented on hardware, these functions are implemented using a lookup table (LUT) in some cases, and the same LUT is used for both of these functions.

Configuration Example of Transmission System to which Present Technology is Applied

In **11**, and a reception apparatus **12**.

The transmission apparatus **11** transmits (broadcasts) (sends), for example, television broadcasting programs. That is, the transmission apparatus **11** encodes, for example, target data which is a transmission target such as image data or voice data as the program into the LDPC code, and transmits the encoded code through a communication channel **13** such as a satellite channel, a terrestrial channel or a cable (wired channel).

The reception apparatus **12** receives the LDPC code transmitted from the transmission apparatus **11** through the communication channel **13**, decodes the received code into the target data, and outputs the decoded data.

Here, it is understand that the LDPC code used in the transmission system of

Meanwhile, in the communication channel **13**, a burst error or erasure may occur. For example, when the communication channel **13** is specifically a terrestrial channel, in an orthogonal frequency division multiplexing (OFDM) system, the power of a particular symbol may become zero (erasure) due to the delay of an echo (a path other than a main path) in a multi-path environment in which a desired-to-undesired (D/U) ratio is 0 dB (undesired=echo power is equal to desired=main path power).

Even in flutter (communication path in which the delay is zero and the echo to which the Doppler frequency is applied is added), when the D/U is 0 dB, the power of all OFDM symbols at a particular time may become zero (erasure) by the Doppler frequency.

A burst error may occur due to a state of a wiring from a reception unit (not shown) of the reception apparatus **12** such as an antenna that receives a signal from the transmission apparatus **11** to the reception apparatus **12** or instability of a power supply of the reception apparatus **12**.

Meanwhile, in the decoding of the LDPC code, in the columns of the parity check matrix H and the variable nodes corresponding to the code bits of the LDPC code, since the variable node calculation of Expression (1) for performing the addition of (reception value u_{0i}) of the code bits of the LDPC code is performed as shown in

In the decoding of the LDPC code, since the check node calculation of Expression (7) is performed in the check node by using the messages obtained in the variable nodes connected to the check node, when the number of check nodes in which errors (including erasure) simultaneously occur in (the code bits of the LDPC code corresponding to) the plurality of connected variable nodes is increased, decoding performance is degraded.

That is, for example, when the erasure simultaneously occurs in two or more variable nodes connected to the check node, the check node returns an equal-probability message in which a probability that the value will be zero and a probability that the value will be one are equal to each other to all of the variable nodes. In this case, the check node that returns the equal-probability message does not contribute to one decoding process (one set of the variable node calculation and the check node calculation), and thus, it is necessary to increase the number of times the decoding process is iterated. Accordingly, the decoding performance is degraded, and the power consumption of the reception apparatus **12** that decodes the LDPC code is increased.

Thus, in the transmission system of

Configuration Example of Transmission Apparatus **11**

**11** of

In the transmission apparatus **11**, one or more input streams as target data are supplied to a mode adaptation/multiplexer **111**.

The mode adaptation/multiplexer **111** performs a mode selection and a process such as multiplexing on one or more input streams being supplied thereto when necessary, and supplies data obtained as the result to a padder **112**.

The padder **112** performs necessary zero padding (insertion of Nulls) on the data from the mode adaptation/multiplexer **111**, and supplies data obtained as the result to a BB scrambler **113**.

The BB scrambler **113** performs base-band (BB) scrambling on the data from the padder **112**, and supplies data obtained as the result to a BCH encoder **114**.

The BCH encoder **114** performs BCH encoding the data from the BB scrambler **113**, and supplies data obtained as the processing result as LDPC target data which is an LDPC encoding target to an LDPC encoder **115**.

The LDPC encoder **115** performs, for example, the LDPC encoding in accordance with the parity check matrix in which the parity matrix which is a part corresponding to the parity bits of the LDPC code has a dual diagonal structure on the LDPC target data from the BCH encoder **114**, and outputs the LDPC code using the LDPC target data as the information bits.

That is, the LDPC encoder **115** performs the LDPC encoding that encodes the LDPC target data into the LDPC code (corresponding to the parity check matrix) defined by a predetermined standard such as DVB-S.2, DVB-T.2 or DVB-C.2, or the LDPC code (corresponding to the parity check matrix) to be adopted by ATSC 3.0, and outputs the LDPC code obtained as the result.

Here, the LDPC code defined by the DVB-T.2 standard or the LDPC code to be adopted by ATSC 3.0 is an irregular repeat-accumulate (IRA) code, and the parity matrix in the parity check matrix of the LDPC code has the dual diagonal structure. The parity matrix and the dual diagonal structure will be described below. The IRA code is described in, for example, “Irregular Repeat-Accumulate Codes,” H. Jin, A. Khandekar, and R. J. McEliece, in Proceedings of 2nd International Symposium on Turbo codes and Related Topics, pp. 1-8, September 2000.

The LDPC code output from the LDPC encoder **115** is supplied to a bit interleaver **116**.

The bit interleaver **116** performs bit interleaving to be described below on the LDPC code from the LDPC encoder **115**, and supplies the LDPC code on which the bit interleaving has been performed to a mapper **117**.

The mapper **117** performs quadrature modulation (multi-level modulation) by mapping the LDPC code from the bit interleaver **116** to a signal point representing one symbol of the quadrature modulation for every one or more code bits of the LDPC code (for every symbol).

That is, the mapper **117** performs the quadrature modulation by mapping the LDPC code from the bit interleaver **116** to a signal point determined through a modulation scheme that performs the quadrature modulation of the LDPC code on an IQ plane (IQ constellation) defined using an I axis indicating an I component having the same phase as that of a carrier wave and a Q axis indicating a Q component perpendicular to the carrier wave.

When the number of signal points determined through the modulation scheme of the quadrature modulation performed by the mapper **117** is 2^{m}, in the mapper **117**, the LDPC code from the bit interleaver **116** is mapped to a signal point of 2^{m }number of signal points indicating a symbol for every symbol by using m number of code bits of the LDPC code as a symbol (one symbol).

Here, examples of the modulation scheme of the quadrature modulation performed by the mapper **117** include a modulation scheme defined by DVB-T.2, a modulation scheme to be adopted by ATSC 3.0, or other modulation schemes, that is, binary phase-shift keying (BPSK), quadrature phase-shift keying (QPSK), 8 phase-shift keying (PSK), 16 amplitude and phase-shift keying (APSK), 32 APSK, 16 quadrature amplitude modulation (QAM), 64-QAM, 256-QAM, 1024-QAM, 4096-QAM and 4 pulse-amplitude modulation (PAM). In the mapper **117**, whether to perform quadrature modulation of any modulation scheme is previously set depending on, for example, an operation input of an operator of the transmission apparatus **11**.

The data (mapping result obtained by mapping the symbol to the signal point) obtained by the process in the mapper **117** is supplied to a time interleaver **118**.

The time interleaver **118** performs time interleaving (interleaving in the time direction) on the data from the mapper **117** for every symbol, and supplies data obtained as the result to a single-input single-output/multiple-input single-output (SISO/MISO) encoder **119**.

The SISO/MISO encoder **119** performs space-time encoding on the data from the time interleaver **118**, and supplies the encoded data to a frequency interleaver **120**.

The frequency interleaver **120** performs frequency interleaving (interleaving in the frequency direction) on the data from the SISO/MISO encoder **119** for every symbol, and supplies data to a frame builder and resource allocation unit **131**.

Meanwhile, control data (signaling) for transmission control such as base-band (BB) signaling (BB header) is supplied to a BCH encoder **121**.

Similarly to the BCH encoder **114**, the BCH encoder **121** performs BCH encoding on the supplied control data, and supplies data obtained as the result to an LDPC encoder **122**.

Similarly to the LDPC encoder **115**, the LDPC encoder **122** performs LDPC encoding on the data from the BCH encoder **121** as LDPC target data, and supplies an LDPC code obtained as the result to a mapper **123**.

Similarly to the mapper **117**, the mapper **123** performs quadrature modulation by mapping the LDPC code from the LDPC encoder **122** for every one or more bits of the LDPC code (unit of the symbol) to a signal point indicating one symbol of the quadrature modulation, and supplies data obtained as the result to a frequency interleaver **124**.

Similarly to the frequency interleaver **120**, the frequency interleaver **124** performs frequency interleaving on the data from the mapper **123** for every symbol, and supplies data to the frame builder and resource allocation unit **131**.

The frame builder and resource allocation unit **131** inserts pilot symbols into necessary positions of the data (symbol) from the frequency interleavers **120** and **124**, constructs a frame (for example, a physical layer (PL) frame, a T2 frame, or a C2 frame) including a predetermined number of symbols from the data (symbol) obtained as the result, and supplies the constructed frame to an OFDM generation unit **132**.

The OFDM generation unit **132** generates an OFDM signal corresponding to the frame, based on the frame from the frame builder and resource allocation unit **131**, and transmits the generated signal through the communication channel **13** (

The transmission apparatus **11** can be configured without including some of the blocks shown in **118**, the SISO/MISO encoder **119**, the frequency interleaver **120** and the frequency interleaver **124**.

Configuration Example of Bit Interleaver **116**

**116** of

The bit interleaver **116** has a function of interleaving data, and includes a parity interleaver **23**, a group-wise interleaver **24**, and a block interleaver **25**.

The parity interleaver **23** performs parity interleaving that interleaves parity bits of the LDPC code from the LDPC encoder **115** into positions of other parity bits, and supplies the LDPC code on which the parity interleaving has been performed to the group-wise interleaver **24**.

The group-wise interleaver **24** performs group-wise interleaving on the LDPC code from the parity interleaver **23**, and supplies the LDPC code on which the group-wise interleaving has been performed to the block interleaver **25**.

Here, in the group-wise interleaving, 360 bits of one group obtained by dividing the LDPC code corresponding to one code from a leading code thereof into a unit of 360 bits equal to a unit size P to be described below are grouped as a bit group, and the LDPC code from the parity interleaver **23** is interleaved for every bit group.

It is possible to further enhance an error rate when the group-wise interleaving is performed than when the group-wise interleaving is not performed. As a result, it is possible to ensure favorable communication quality in data transmission.

By performing block interleaving for demultiplexing the LDPC code from the group-wise interleaver **24**, the block interleaver **25** symbolizes the LDPC code corresponding to one code into, for example, an m-bit symbol which is a unit of mapping, and the symbolized symbol is supplied to the mapper **117** (

Here, in the block interleaving, the LDPC code from the group-wise interleaver **24** is written in a column (longitudinal) direction in a storage region in which columns as storage regions storing a predetermined number of bits in the column direction are arranged by the number corresponding to m number of bits of the symbol in a row direction (transverse direction), and is read in the row direction. Thus, the LDPC code corresponding to one code is symbolized into, for example, the m-bit symbol.

Parity Check Matrix of LDPC Code

**115** of

The parity check matrix H has a low-density generator matrix (LDGM) structure, and can be expressed as the expression H=[H_{A}|H_{T}] (a matrix in which an element of an information matrix H_{A }is used as a left element, and an element of a parity matrix H_{T }is used as a right element) by the information matrix H_{A }which is a part corresponding to the information bits of the code bits of the LDPC code and the parity matrix H_{T }corresponding to the parity bits.

Here, the number of bits of the information bits of the code bits of the LDPC code (one codeword) of the one code and the number of bits of the parity bits are respectively referred to as an information length K and a parity length M, and the number of bits of the code bits of the LDPC code of one code (one codeword) is referred to as a code length N (=K+M).

The information length K and the parity length M of the LDPC code having a certain code length N are determined depending on a code rate. The parity check matrix H is a matrix in which row×column is M×N (matrix of M row×N column). The information matrix H_{A }is an M×K matrix, and the parity matrix H_{T }is an M×M matrix.

_{T }of the parity check matrix H used for the LDPC encoding in the LDPC encoder **115** of

The parity matrix H_{T }of the parity check matrix H used for the LDPC encoding in the LDPC encoder **115** is the same as the parity matrix H_{T }of the parity check matrix H of the LDPC code defined by the standard such as DVB-T.2.

As shown in _{T }of the parity check matrix H of the LDPC code defined by the standard such as DVB-T.2 is a matrix having a dual diagonal structure (lower bidiagonal matrix) in which the elements of 1s are arranged in a so-called dual diagonal form. The row weight of the parity matrix H_{T }is 1 for the first row, and is 2 for all of the remaining rows. The column weight is 1 for the last column, and is 2 for all of the remaining columns.

As mentioned above, the LDPC code of the parity check matrix H of which the parity matrix H_{T }has the dual diagonal structure can be generated using the parity check matrix H.

That is, the LDPC code (one codeword) is expressed as a row vector c, and a column vector which is the transpose of the row vector is expressed as c^{T}. A part of the information bits of the row vector c which is the LDPC code is expressed as a row vector A, and a part of the parity bits is expressed as a row vector T.

In this case, the row vector c can be expressed as the express c=[A|T] (row vector in which an element of the row vector A is used as a left element and an element of the row vector T is used as a right element) by the row vector A as the information bits and the row vector T as the parity bits.

The parity check matrix H and the row vector c=[A|T] as the LDPC code are necessary to satisfy the expression Hc^{T}=0, and when the parity matrix H_{T }of the parity check matrix H=[H_{A}|H_{T}] has the dual diagonal structure shown in ^{T}=0 can be successively (sequentially) calculated by sequentially changing the elements of the respective rows to zero from the first element of the column vector Hc^{T }in the expression Hc^{T}=0.

The column weight of a KX column from the first column of the parity check matrix H of the LDPC code defined by the standard such as DVB-T.2 is X, the column weight of the K3 column is 3, the column weight of the M−1 column is 2, and the column weight of the last column is 1.

Here, KX+K3+M−1+1 is equal to the code length N.

In the standard such as DVB-T.2, the LDPC codes having the code lengths N of 64,800 bits and 16,200 bits are defined.

Eleven code rates (nominal rates) of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10 are defined for the LDPC code having the code length N of 64,800 bits, and ten code rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9 are defined for the LDPC code having the code length N of 16,200 bits.

Here, the code length N of 64,800 bits is referred to as 64 k bits, and the code length N of 16,200 bits is referred to as 16 k bits.

In the case of the LDPC code, code bits of the parity check matrix H corresponding to columns having a larger column weight tend to have lower error rates.

In the parity check matrix H defined by the standard such as DVB-T.2 shown in

Parity Interleaving

The parity interleaving performed by the parity interleaver **23** of

As shown in

However, the LDPC code output from the LDPC encoder **115** of _{T }of the parity check matrix H has the dual diagonal structure as shown in

_{T }having the dual diagonal structure as shown in _{T}.

_{T }having the dual diagonal structure, and _{T }of

In the parity matrix H_{T }having the dual diagonal structure, the elements of “1”s are adjacent to each other in the respective rows (except for the first column). For this reason, in the Tanner graph of the parity matrix H_{T}, two adjacent variable nodes corresponding to columns of two adjacent elements in which the values of the parity matrix H_{T }are 1s are connected to the same check node.

Accordingly, when the parity bits corresponding to the two adjacent variable nodes are simultaneously in error due to the burst error or the erasure, since the check node connected to the two variable nodes (variable nodes requesting messages using the parity bits) corresponding to the two parity bits in error returns the equal-probability message in which the probability that the value will be zero and the probability that the value will be one are equal to the variable nodes connected to the check node, the decoding performance is degraded. When a burst length (the number of bits of the parity bits that are continuously in error) is increased, the number of check nodes that return the equal-probability message is increased, and thus, the decoding performance is further degraded.

Thus, in order to prevent the degradation of the decoding performance, the parity interleaver **23** (**115** into positions of other parity bits.

_{T }of the parity check matrix H corresponding to the LDPC code on which the parity interleaving has been performed by the parity interleaver **23** of

Here, the information matrix H_{A }of the parity check matrix H corresponding to the LDPC code output from the LDPC encoder **115** has a cyclic structure similarly to the information matrix of the parity check matrix H corresponding to the LDPC code defined by the standard such as DVB-T.2.

The cyclic structure refers to a structure in which a certain column coincides with a column obtained by performing cyclic shifting on another column, and includes, for example, a structure in which the positions of 1s of the respective rows of the P column for each of the P columns are positions obtained by performing cyclic-shifting in the column direction by a predetermined value such as a value proportional to a value q obtained by dividing the first column of the P column by the parity length M. Hereinafter, the P column in the cyclic structure is appropriately referred to as a unit size.

As described in

Further, the parity length M is a value other than a prime number represented by the expression M=q×P=q×360 by using the value q different depending on the code rate. Accordingly, similarly to the unit size P, the value q is another one of the divisors except for 1 and M of the divisors of the parity length M, and is obtained by dividing the parity length M by the unit size P (the product of P and q which are divisors of the parity length M is the parity length M).

As described above, when the information length is K, an integer which is 0 or greater and less than P is x, an integer which is 0 or greater and less than q is y, the parity interleaver **23** interleaves the (K+qx+y+1)-th code bit of the code bits of the N-bit LDPC code into the position of the (K+Py+x+1)-th code bit.

Since both of the (K+qx+y+1)-th code bit and the (K+Py+x+1)-th code bit are code bits subsequent to a (K+1)-th code bit, these bits are parity bits. Accordingly, the positions of the parity bits of the LDPC code are moved through the parity interleaving.

According to the parity interleaving, since (the parity bits corresponding to) the variable nodes connected to the same check node are separated by the unit size P, that is, 360 bits, when the burst length is less than 360 bits, it is possible to avoid the situation that the plurality of variable nodes connected to the same check node are simultaneously in error, and as a result, it is possible to improve tolerance to the burst error.

The LDPC code on which the parity interleaving that interleaves the (K+qx+y+1)-th code bit into the position of the (K+Py+x+1)-th code bit has been performed coincides with the LDPC code (hereinafter, referred to as a permutation parity check matrix) of the parity check matrix obtained by performing column permutation that permutes the (K+qx+y+1)-th column of the original parity check matrix H into the (K+Py+x+1)-th column.

As shown in

Here, the pseudo-cyclic structure refers to a structure in which parts except for a part have the cyclic structure.

The permutation parity check matrix obtained by performing the column permutation corresponding to the parity interleaving on the parity check matrix of the LDPC code defined by the standard such as DVB-T.2 is a so-called pseudo-cyclic structure not the (complete) cyclic structure in which the number of the elements of 1s is short by one (the element of 1 becomes the element of 0) in a part of 360 rows×360 columns (shift matrix to be described below) which is an upper-right corner part of the permutation parity check matrix.

Similarly to the permutation parity check matrix for the parity check matrix of the LDPC code defined by the standard such as DVB-T.2, the permutation parity check matrix for the parity check matrix of the LDPC code output from the LDPC encoder **115** has, for example, the pseudo-cyclic structure.

The permutation parity check matrix of

**115**, the bit interleaver **116** and the mapper **117** of

The LDPC encoder **115** waits for the LDPC target data to be supplied from the BCH encoder **114**, encodes the LDPC target data into the LDPC code in step S**101**, and supplies the LDPC code to the bit interleaver **116**. The process proceeds to step S**102**.

In step S**102**, the bit interleaver **116** performs the bit interleaving on the LDPC code from the LDPC encoder **115**, and supplies a symbol obtained by performing the bit interleaving to the mapper **117**. The process proceeds to step S**103**.

That is, in step S**102**, the parity interleaver **23** of the bit interleaver **116** (**115**, and supplies the LDPC code on which the parity interleaving has been performed to the group-wise interleaver **24**.

The group-wise interleaver **24** performs the group-wise interleaving on the LDPC code from the parity interleaver **23**, and supplies the LDPC code to the block interleaver **25**.

The block interleaver **25** performs the block interleaving on the LDPC code on which the group-wise interleaving has been performed by the group-wise interleaver **24**, and supplies an m-bit symbol obtained as the result to the mapper **117**.

In step S**103**, the mapper **117** performs the quadrature modulation by mapping the symbol from the block interleaver **25** to any one of 2^{m }number of signal points determined through the modulation scheme of the quadrature modulation performed by the mapper **117**, and supplies data obtained as the result to the time interleaver **118**.

As stated above, it is possible to improve the error rate when the plurality of code bits of the LDPC code is transmitted as one symbol by performing the parity interleaving and the group-wise interleaving.

Here, for the sake of convenience in the description, although it has been described in **23** which is the block that performs the parity interleaving and the group-wise interleaver **24** which is the block that performs the group-wise interleaving are individually provided, the parity interleaver **23** and the group-wise interleaver **24** may be integrally configured.

That is, both of the parity interleaver and the group-wise interleaving can be performed by writing and reading the code bits in and from the memory, and can be expressed by a matrix for converting an address (write address) where the code bits are written into an address (read address) where the code bits are read.

Accordingly, if a matrix obtained by multiplying a matrix representing the parity interleaving and a matrix representing the group-wise interleaving is obtained, the code bits are converted by using these matrices. Therefore, it is possible to obtain the result on which the parity interleaving is performed and the group-wise interleaving is performed on the LDPC code on which the parity interleaving has been performed.

It is possible to integrally configure the block interleaver **25** in addition to the parity interleaver **23** and the group-wise interleaver **24**.

That is, the block interleaving performed in the block interleaver **25** can also be expressed by a matrix for converting a write address where the LDPC code is stored into a read address.

Accordingly, if a matrix obtained by multiplying the matrix representing the parity interleaving, the matrix representing the group-wise interleaving and the matrix representing the block interleaving is obtained, it is possible to collectively perform the parity interleaving, the group-wise interleaving and the block interleaving by using these matrices.

Configuration Example of LDPC Encoder **115**

**115** of

The LDPC encoder **122** of

As described in

Eleven code rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9 and 9/10 are defined for the LDPC code having the code length N of 64,800 bits, and tens code rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6 and 8/9 are defined for the LDPC code having the code length N of 16,200 bits (

For example, the LDPC encoder **115** can perform encoding (error-correction encoding) using the LDPC codes of the respective code rates which have the code lengths N of 64,800 bits and 16,200 bits according to the parity check matrix H provided for each the code lengths N and each code rate.

The LDPC encoder **115** includes an encoding unit **601**, and a storage unit **602**.

The encoding unit **601** includes a code rate setting module **611**, an initial value table reading module **612**, a parity check matrix generating module **613**, an information bit reading module **614**, an encoding parity calculating module **615**, and a control module **616**. The encoding unit performs the LDPC encoding on the LDPC target data supplied to the LDPC encoder **115**, and supplies the LDPC code obtained as the result to the bit interleaver **116** (

That is, the code rate setting module **611** sets the code length N and the code rate of the LDPC code depending on, for example, an operation input of the operator.

The initial value table reading module **612** reads a parity check matrix initial value table to be described below, which corresponds to the code length N and the code rate set by the code rate setting module **611**, from the storage unit **602**.

The parity check matrix generating module **613** generates the parity check matrix H by arranging the elements of 1s of the information matrix H_{A }corresponding to the information length K (=code length N−parity length M) according to the code rate and the code length N set by the code rate setting module **611** for every 360 columns (unit size P) in the column direction based on the parity check matrix initial value table read by the initial value table reading module **612**, and stores the generated parity check matrix in the storage unit **602**.

The information bit reading module **614** reads (extracts) the information bits having the information length K from the LDPC target data supplied to the LDPC encoder **115**.

The encoding parity calculating module **615** reads the parity check matrix H generated by the parity check matrix generating module **613** from the storage unit **602**, and generates the codeword (LDPC code) by calculating the parity bits with respect to the information bits read by the information bit reading module **614** based on the predetermined expression by using the parity check matrix H.

The control module **616** controls the respective blocks constituting the encoding unit **601**.

For example, a plurality of parity check matrix initial value tables corresponding to the plurality of code rates shown in **602**. The storage unit **602** temporarily stores necessary data in the process of the encoding unit **601**.

**115** of

In step S**201**, the code rate setting module **611** determines (sets) the code length N and the code rate r for performing the LDPC encoding.

In step S**202**, the initial value table reading module **612** reads a predetermined parity check matrix initial value table corresponding to the code length N and the code rate r determined by the code rate setting module **611** from the storage unit **602**.

In step S**203**, the parity check matrix generating module **613** obtains (generates) the parity check matrix H of the LDPC code having the code length N and the code rate r determined by the code rate setting module **611** by using the parity check matrix initial value table read from the storage unit **602** by the initial value table reading module **612**, and stores the obtained parity check matrix in the storage unit **602**.

In step S**204**, the information bit reading module **614** reads the information bits having the information length K (=N×r) corresponding to the code length N and the code rate r determined by the code rate setting module **611** from the LDPC target data supplied to the LDPC encoder **115**, reads the parity check matrix H obtained by the parity check matrix generating module **613** from the storage unit **602**, and supplies the read information bits and the parity check matrix to the encoding parity calculating module **615**.

In step S**205**, the encoding parity calculating module **615** calculates the parity bits of the codeword c satisfying Expression (8) by using the parity check matrix H and the information bits from the information bit reading module **614**.

*Hc*^{T}=0 (8)

In Expression (8), c represents a row vector as the codeword (LDPC code), and c^{T }represents the transpose of the row vector c.

Here, as stated above, a part of the information bits of the row vector c as the LDPC code (one codeword) is represented as a row vector A, and when a part of the parity bits is represented by a row vector T, the row vector c can be expressed by the expression c=[A|T] by using the row vector A as the information bits and the row vector T as the parity bits.

When the parity matrix H_{T }of the parity check matrix H=[H_{A}|H_{T}] has the dual diagonal structure shown in ^{T}=0, and the row vector T as the parity bits constituting the row vector c=[A|T] satisfying the expression Hc^{T}=0 can be sequentially obtained by sequentially converting the elements of the respective rows into zero from the elements of the first row of the column vector Hc^{T }in the expression Hc^{T}=0.

The encoding parity calculating module **615** obtains the parity bits T for the information bits A from the information bit reading module **614**, and outputs the codeword c=[A|T] expressed by the information bits A and the parity bits T as the result of the LDPC encoding of the information bits A.

Thereafter, in step S**206**, the control module **616** determines whether or not the LDPC encoding has ended. In step S**206**, when it is determined that the LDPC encoding has not ended, that is, when, for example, the LDPC target data to be subject to the LDPC encoding is still present, the process returns to step S**201** (or step S**204**), and thereinafter, the processes of step S**201** (or step S**204**) to step S**206** are repeated.

In step S**206**, when it is determined that the LDPC encoding has ended, that is, when, for example, the LDPC target data to be subject to the LDPC encoding is not present, the LDPC encoder **115** ends the process.

As mentioned above, the parity check matrix initial value table corresponding to the code rates r and the code lengths N is provided, and the LDPC encoder **115** performs the LDPC encoding with a predetermined code length N and a predetermined cord rate r by using the parity check matrix H generated from the parity check matrix initial value table corresponding to the predetermined code length N and the predetermined code rate r.

Example of Parity Check Matrix Initial Value Table

The parity check matrix initial value table is a table in which the positions of the elements of 1s of the information matrix H_{A }(

That is, in the parity check matrix initial value table, at least the positions of the elements of 1s of the information matrix H_{A }are represented for every 360 columns (unit size P).

As the parity check matrix H, there are a parity check matrix which is defined by DVB-T.2 and in which (all of) the parity matrices H_{T }have the dual diagonal structure, and a parity check matrix which is suggested by CRC/ETRI and in which a part of the parity matrix H_{T }has the dual diagonal structure and the remaining part has a diagonal matrix (unit matrix).

Hereinafter, an expression method of a parity check matrix initial value table representing the parity check matrix which is defined by DVB-T.2 and in which the parity matrix H_{T }has the dual diagonal structure is referred to as a DVB method, and an expression method of a parity check matrix initial value table representing the parity check matrix suggested by CRC/ETRI is referred to as a ETRI method.

That is,

The parity check matrix generating module **613** (

That is,

The parity check matrix initial value table of the DVB method is a table in which the positions of all of the elements of 1s of the information matrix H_{A }corresponding to the information length K in accordance with the code rate r and the code length N of the LDPC code are represented for every 360 columns (unit size P), and row numbers of the elements of is of the (1+360×(i−1))-th column of the parity check matrix H (row numbers in which a row number of the first row of the parity check matrix H is zero) are arranged in the i-th row by the number of a column weight of the (1+360×(i−1))-th column.

Here, since the parity check matrix H_{T }(_{A }(

A row number k+1 of the parity check matrix initial value table of the DVB method is different depending on the information length K.

The relationship of Expression (9) is established between the information length K and the row number k+1 of the parity check matrix initial value table.

*K*=(*k+*1)×360 (9)

Here, 360 of Expression (9) is the unit size P described in

In the parity check matrix initial value table of

Accordingly, the column weight of the parity check matrix H obtained from the parity check matrix initial value table of

The first row of the parity check matrix initial value table of

The second row of the parity check matrix initial value table of

As stated above, in the parity check matrix initial value table, the positions of the elements of 1s of the information matrix H_{A }of the parity check matrix H are represented for every 360 columns.

Columns other than the (1+360×(i−1))-th column of the parity check matrix H, that is, the respective columns from the (2+360×(i−1))-th column to the (360×i)-th column are arranged by periodically cyclic-shifting the elements of 1s of the (1+360×(i−1))-th column determined by the parity check matrix initial value table in the lower direction (lower direction of the columns) according to the parity length M.

That is, for example, the (2+360×(i−1))-th column is obtained by cyclic-shifting the (1+360×(i−1))-th column in the lower direction by M/360(=q), and the next (3+360×(i−1))-th column is obtained by cyclic-shifting ((2+360×(i−1))-th column obtained by cyclic-shifting the (1+360×(i−1))-th column in the lower direction by 2×M/360(=2×q) in the lower direction by M/360(=q).

When the value of the j-th column (the j-th column from the left) of the i-th row (i-th row from the top) of the parity check matrix initial value table is represented as h_{i,j}, and a row number of a j-th element of 1 of the w-th column of the parity check matrix H is represented as H_{w-j}, the row number H_{w-j }of the element of 1 of the w-th column which is a column other than the (1+360×(i−1))-th column of the parity check matrix H can be obtained using Expression (10).

*H*_{w-j}=mod {*h*_{i,j}+mod((*w−*1),*P*)×*q,M*) (10)

Where, mod(x, y) means a remainder obtained by dividing x by y.

In the first embodiment, P is the aforementioned unit size, and is 360 as in the standard of, for example, DVB-S.2, DVB-T.2 and DVB-C.2. Furthermore, q is a value of M/360 obtained by dividing the parity length M by the unit size P (=360).

The parity check matrix generating module **613** (

Moreover, the parity check matrix generating module **613** (_{w-j }of the element of 1 of the w-th column which is the column other than the (1+360×(i−1))-th column of the parity check matrix H according to Expression (10), and the parity check matrix H having the element of 1 of the row number as obtained above is generated.

The parity check matrix of the ETRI method includes an A matrix, a B matrix, a C matrix, a D matrix, and a Z matrix.

The A matrix is a matrix on an upper left side of the parity check matrix which is expressed as information length K of LDPC code=code length N×code rate r and a predetermined value g and has g rows and k columns.

The B matrix is a matrix which has g rows and g columns and has a dual diagonal structure which is adjacent to a right side of the A matrix.

The C matrix is a matrix which has N-K−g rows and K+g columns and is adjacent to a lower side of the A matrix and the B matrix.

The D matrix is a unit matrix which has N-K−g rows and N-K−g columns and is adjacent to a right side of the C matrix.

The Z matrix is a zero matrix (0 matrix) which has g rows and N-K−g columns and is adjacent to a right side of the B matrix.

In the parity check matrix of the ETRI method including the A matrix to the D matrix and the Z matrix described above, a part of the A matrix and the C matrix constitutes the information matrix, and the remaining part of the B matrix and the C matrix, the D matrix and the Z matrix constitute the parity matrix.

Since the B matrix is the matrix having the dual diagonal structure and the D matrix is the unit matrix, a part (a part of the B matrix) of the parity matrix of the parity check matrix of the ETRI method has the dual diagonal structure, and the remaining part thereof (a part of the D matrix) is the diagonal matrix (unit matrix).

Similarly to the information matrix of the parity check matrix of the DVB method, the A matrix and the C matrix have the cyclic structure for every 360 columns (unit size P), and in the parity check matrix initial value table of the ETRI method, the positions of the elements of 1s of the A matrix and the C matrix are represented for every 360 columns.

Here, as described above, since a part of the A matrix and the C matrix constitutes the information matrix, in the parity check matrix initial value table of the ETRI method in which the positions of the elements of 1s of the A matrix and the C matrix are represented for every 360 columns, at least the positions of the elements of 1s of the information matrix can be represented for every 360 columns.

That is,

The parity check matrix initial value table of the ETRI method is a table in which the positions of the elements of 1s of the A matrix and the C matrix are represented for each unit size P, and the row numbers of the elements of 1s of the (1+P×(i−1))-th column of the parity check matrix (the row numbers in which the row numbers of the first row of the parity check matrix are 0s) are arranged in the i-th column by the column weight of the columns of the (1+P×(i−1))-th column.

Here, for the sake of convenience in the description, the unit size P is, for example, 5. As parameters of the parity check matrix of the ETRI method, there are g=M_{1}, M_{2}, Q_{1}, and Q_{2}.

g=M_{1 }is a parameter for determining the size of the B matrix, and is a value of a multiple of the unit size P. When the performance of the LDPC code is changed by adjusting g=M_{1 }and the parity check matrix is determined, a predetermined value is adjusted. Here, it is assumed that g=M_{1}, and the unit size P=5 multiplied by 3=15.

M_{2 }is a value M-M_{1 }which is the parity length M minus M_{1}.

Here, since the information length K is N×r=50×1/2=25 and the parity length M is N−K=50−25=25, M_{2 }is M−M_{1}=25−15=10.

Q_{1 }is obtained according to the expression Q_{1}=M_{1}/P, and represents the number of shifts (the number of rows) in the cyclic shifting in the A matrix.

That is, the columns other than the (1+P×(i−1))-th column of the A matrix of the parity check matrix of the ETRI method, that is, the respective columns from the (2+P×(i−1))-th column to the (P×i)-th column are arranged by periodically cyclic-shifting the elements of 1s of the (1+360×(i−1))-th columns determined by the parity check matrix initial value table in the lower direction (lower direction of the columns), and Q_{1 }represents the number of shifts in the cyclic shifting in the A matrix.

Q_{2 }is obtained according to the expression Q_{2}=M_{2}/P, and represents the number of shifts (the number of rows) in the cyclic shifting in the C matrix.

That is, the columns other than the (1+P×(i−1))-th column of the C matrix of the parity check matrix of the ETRI method, that is, the respective columns from the (2+P×(i−1))-th column to the (P×i)-th column are arranged by periodically cyclic-shifting the elements of 1s of the (1+360×(i−1))-th column determined by the parity check matrix initial value table in the lower direction (lower direction of the columns), and Q_{2 }represents the number of shifts in the cyclic shifting in the C matrix.

Here, Q_{1 }is M_{1}/P=15/5=3, and Q_{2 }is M_{2}/P=10/5=2.

In the parity check matrix initial value table of

That is, the first row of the parity check matrix initial value table of

In this case, since the A matrix is a matrix in 15 rows and 25 columns (g rows and K columns) and the C matrix is the matrix in 10 rows and 40 columns (N−K−g rows and K+g columns), the rows having row numbers of 0 to 14 of the parity check matrix are the rows of the A matrix, and the rows having row numbers of 15 to 24 of the parity check matrix are rows of the C matrix.

Accordingly, among the rows having the row numbers of 2, 6 and 18 (hereinafter, described as the rows #2, #6, and #18), the rows #2 and #6 are the rows of the A matrix, and the row #18 is the row of the C matrix.

The second row of the parity check matrix initial value table of

Here, the rows #2 and #10 of the rows #2, #10, and #19 in the 6(=1+5×(2−1))-th column of the parity check matrix are the rows of the A matrix, and the row #19 is the row of the C matrix.

The third row of the parity check matrix initial value table of

Here, the row #22 in the 11(=1+5×(3−1))-th row of the parity check matrix is the row of the C matrix.

Similarly, 19 of the fourth row of the parity check matrix initial value table of

As stated above, in the parity check matrix initial value table, the positions of the elements of 1s of the A matrix and the C matrix of the parity check matrix are represented for each unit size P=5.

The columns other than the (1+5×(i−1))-th column of the A matrix and the C matrix of the parity check matrix, that is, the respective columns from the (2+5×(i−1))-th column to the (5×i)-th column are arranged by periodically cyclic-shifting the elements of 1s of the (1+5×(i−1))-th columns determined by the parity check matrix initial value table in the lower direction (lower direction of the columns) according to the parameters Q_{1 }and Q_{2}.

That is, for example, the (2+5×(i−1))-th column of the A matrix is obtained by cyclic-shifting the (1+5×(i−1))-th column in the lower direction by Q_{1}(=3), and the next (3+5×(i−1))-th column is obtained by cyclic-shifting the (2+5×(i−1))-th column obtained by cyclic shifting the (1+5×(i−1))-th column in the lower direction by 2×Q_{1}(=2×3) in the lower direction by Q_{1}.

For example, the (2+5×(i−1))-th column of the C matrix is obtained by cyclic-shifting the (1+5×(i−1))-th column in the lower direction by Q_{2}(=2), and the next (3+5×(i−1))-th column is obtained by cyclic-shifting the (2+5×(i−1))-th column obtained by cyclic-shifting the (1+5×(i−1))-th column in the lower direction by 2×Q_{2}(=2×2) in the lower direction by Q_{2}.

In the A matrix of

Moreover, the respective columns from the 2(=2+5×(1−1))-nd column to the 5(=5+5×(1−1))-th column are obtained by cyclic-shifting the immediately previous columns in the lower direction by Q_{1}=3.

In the A matrix of

The respective columns from the 7(=2+5×(2−1))-th column to the 10(=5+5×(2−1))-th column are obtained by cyclic-shifting the immediately previous columns in the lower direction by Q_{1}=3.

The parity check matrix generating module **613** (**613** regards the B matrix as the parity matrix, and performs the parity interleaving such that the adjacent elements of 1s of the B matrix having the dual diagonal structure are separated from each other by the unit size P=5 in the row direction.

In the C matrix of

The respective columns from the 2(=2+5×(1−1))-nd column to the 5(=5+5×(1−1))-th column of the C matrix are obtained by cyclic-shifting the immediately previous columns in the lower direction by Q_{2}=2.

In the C matrix of

The respective columns from the 7(=2+5×(2−1))-th column to the 10(=5+5×(2−1))-th column, the respective columns from the 12(=2+5×(3−1))-th column to the 15(=5+5×(3−1))-th column, the respective columns from the 17(=2+5×(4−1))-th column to the 20(=5+5×(4−1))-th column, and the respective columns from the 22(=2+5×(5−1))-nd column to the 25(=5+5×(5−1))-th column are obtained by cyclic shifting the immediately previous columns in the lower direction by Q_{2}=2.

The parity check matrix generating module **613** (

Further, the parity check matrix generating module **613** arranges the Z matrix so as to be adjacent to the right side of the B matrix, arranges the D matrix to be adjacent to the right side of the C matrix, and generates the parity check matrix shown in

After the parity check matrix of **613** regards the D matrix as the parity matrix, and performs the parity interleaving on only the D matrix such that the elements of 1s of the odd-number rows and the next even-number rows of the D matrix of the unit matrix are separated from each other by the unit size P=5.

(The encoding parity calculating module **615** (**115** performs the LDPC encoding (generates the LDPC code) by using, for example, the parity check matrix of

Here, the LDPC code generated using the parity check matrix of **23** (

In the LDPC encoder **115**, it is possible to perform the LDPC encoding (generate the LDPC code) by using the parity check matrix of

When the LDPC encoding is performed using the parity check matrix of **23** (

As will be described below, the transformation check matrix is a matrix represented by combining a unit matrix of P×P, a quasi-unit matrix in which one or more 1s of 1s of the unit matrix are 0s, a shift matrix obtained by cyclic-shifting the unit matrix or the quasi-unit matrix, a sum matrix which is the sum of two or more matrices of the unit matrix, the quasi-unit matrix and the shift matrix, and a 0 matrix of P×P.

By using the transformation check matrix in the decoding of the LDPC code, it is possible to adopt an architecture in which the check node calculation and the variable node calculation are simultaneously performed P times in the decoding of the LDPC code, as will be described below.

New LDPC Code

The standard of the terrestrial digital television broadcasting called ATSC 3.0 is currently being developed.

Now, a renewed LDPC code (hereinafter, referred to as a new LDPC code) capable of being used in data transmission other than ATSC 3.0 will be described.

For example, as the new LDPC code, it is possible to adopt the LDPC code of the ETRI method or the LDPC code of the DVB method which has the unit size P of 360 which is the same as that of DVB-T.2, and corresponds to the parity check matrix having the cyclic structure.

The LDPC encoder **115** (

In this case, the parity check matrix initial value table of the new LDPC code is stored in the storage unit **602** of the LDPC encoder **115** (

Among the new LDPC codes, particularly, the Sony codes are LDPC codes having good performance.

Here, the LDPC codes having good performance are LDPC codes obtained from an appropriate parity check matrix H.

For example, the appropriate parity check matrix H is a parity check matrix which has a smaller BER (bit error rate) (and FER (frame error rate)) and satisfies a predetermined condition when the LDPC code obtained from the parity check matrix H is transmitted with a low E_{s}/N_{0 }or E_{b}/N_{o }(the ratio of the signal power to the noise power per one bit).

It is possible to obtain the appropriate parity check matrix H by performing, for example, a simulation that measures a BER when the LDPC codes obtained from various parity check matrices satisfying a predetermined condition are transmitted with a low E_{s}/N_{o}.

As the predetermined conditions to be satisfied by the appropriate parity check matrix H, there are a condition in which an analysis result obtained by a code performance analysis method called density evolution is favorable and a condition in which a loop of the elements of 1s called cycle-4 is not present.

In the information matrix H_{A}, when the elements of 1s are concentrated as in cycle-4, it is considered that the decoding performance of the LDPC code is degraded, and thus, a condition in which cycle-4 is not present is necessary as the predetermined condition to be satisfied by the appropriate parity check matrix H.

It is possible to appropriately determine the predetermined condition to be satisfied by the appropriate parity check matrix H in order to improve the decoding performance of the LDPC code or easily perform (simplify) the decoding process of the LDPC code.

The density evolution is a code analysis method of calculating an expectation value of an error probability of an ensemble of LDPC codes which is specified by a degree sequence to be described below and has a code length N of ∞.

For example, when the variance of noise is steadily increased from zero on an AWGN channel, an expectation value of an error possibility of a certain ensemble is initially zero, but when the variance of noise is equal to or greater than a certain threshold, the expectation value thereof does not become zero.

According to the density evolution, it is possible to determine if the performance of the ensemble is good or bad (appropriateness of the parity check matrix) by comparing the expectation value with a threshold (hereinafter, referred to as a performance threshold) of the variance of noise in which the expectation value of the error probability does not become zero.

With regard to a specific LDPC code, when an ensemble to which the LDPC code belongs is determined and the density evolution is performed, it is possible to roughly predict performance of the LDPC code.

Accordingly, if the ensemble having good performance is found, it is possible to find the LDPC code having good performance from the LDPC codes belonging to the ensemble.

Here, the aforementioned degree sequence means what percentage of the variable nodes or the check nodes having the respective weight values are present in the LDPC code having the code length N.

For example, a regular (3, 6) LDPC code having a code rate of 1/2 belongs to an ensemble specified by the degree sequence in which the weights (column weights) of all variable nodes are 3 and the weights (row weights) of all check nodes are 6.

In the Tanner graph of

Three edges equal to the column weight are connected to the respective variable nodes, and thus, edges connected to the N number of variable nodes are present by a 3N number in total.

Six edges equal to the row weight are connected to the respective check nodes, and thus, edges connected to N/2 number of check nodes are present by a 3N number in total.

Furthermore, in the Tanner graph of

The interleaver randomly rearranges 3N number of edges connected to N number of variable nodes, and connects the rearranged edges to any one of 3N number of edges connected to N/2 number of check nodes.

As a rearrangement pattern in which 3N number of edges connected to N number of variable nodes are rearranged in the interleaver, there are (3N)!(=(3N)×(3N−1)× . . . ×1) number of methods. Accordingly, an ensemble specified by the degree sequence in which the weights of all variable nodes are 3 and the weights of all check nodes are 6 is a set of (3N)! number of LDPC codes.

In the simulation for obtaining the LDPC code (appropriate parity check matrix) having good performance, a multi-edge type ensemble is used in the density evolution.

In the multi-edge type, the interleaver through which the edges connected to the variable nodes and the edges connected to the check nodes pass is divided into multiple edges, and thus, the ensemble is more precisely specified.

In the Tanner graph of

In the Tanner graph of

In the Tanner graph of

The density evolution and the implementation thereof are described in, for example, “On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit”, S. Y. Chung, G. D. Forney, T. J. Richardson, R. Urbanke, IEEE Communications Leggers, VOL. 5, NO. 2, February 2001.

In the simulation for obtaining (the parity check matrix initial value table of) the Sony codes, an ensemble of which a performance threshold which is E_{b}/N_{0 }(ratio of signal power to noise power per one bit) at which a BER starts to be decreased (become smaller) is equal to or less than a predetermined value is found through the multi-edge type density evolution, and the LDPC code capable of reducing the BER when one or more quadrature modulation schemes such as QPSK are used is selected as the LDPC code having good performance from the LDPC codes belonging to the found ensemble.

The parity check matrix initial value table of the Sony codes is obtained through the simulation described above.

Therefore, according to the Sony codes obtained from the parity check matrix initial value table, it is possible to ensure favorable communication quality in data transmission.

All minimum cycle lengths of the parity check matrix H of the Sony codes of (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15) exceed the cycle-4, and thus, the cycle-4 (a loop of the elements of 1s which has a loop length of 4) is not present. Here, the minimum cycle length (girth) means the minimum value of the length of the loop (loop length) constructed by the elements of 1s of the parity check matrix H.

A performance threshold of the Sony code of (16 k, 8/15) is 0.805765, a performance threshold of the Sony code of (16 k, 10/15) is 2.471011, and a performance threshold of the Sony code of (16 k, 12/15) is 4.269922.

In the parity check matrix H of the Sony codes of (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15), column weights from the first column to the KX1-th column are X1, a column weight of the KX2-th column is X2, a column weight of the KY1-th column is Y1, a column weight of the KY2-th column is Y2, a column weight of the (M−1)-th column is 2, and a column weight of the last column is 1.

Here, KX1+KX2+KY1+KY2+M−1+1 is equal to the code length N=16,200 bits of the Sony codes of (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15).

The column numbers KX1, KX2, KY1, KY2, and M and the column weights X1, X2, Y1, and Y2 of the parity check matrix H of the Sony codes of (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15) are shown in

Similarly to the parity check matrix described in

According to the simulation performed by the present applicant, favorable BER/FER are obtained for the Sony codes of (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15), and thus, it is possible to ensure favorable communication quality in data transmission using the Sony codes of (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15).

All minimum cycle lengths of the parity check matrix H of the Sony codes of (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15) exceed the cycle-4, and thus, the cycle-4 is not present.

A performance threshold of the Sony code of (64 k, 7/15) is −0.093751, a performance threshold of the Sony code of (64 k, 9/15) is 1.658523, a performance threshold of the Sony code of (64 k, 11/15) is 3.351930, and a performance threshold of the Sony code of (64 k, 13/15) is 5.301749.

In the parity check matrix H of the Sony codes of (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15), column weights from the first column to the KX1-th column are X1, a column weight of the KX2-th column is X2, a column weight of the KY1-th column is Y1, a column weight of the KY2-th column is Y2, a column weight of the (M−1)-th column is 2, and a column weight of the last column is 1.

KX1+KX2+KY1+KY2+M−1+1 is equal to the code length N=64,800 bits of the Sony codes of (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15).

The column numbers KX1, KX2, KY1, KY2, and M and the column weights X1, X2, Y1, and Y2 of the parity check matrix H of the Sony codes of (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15) are shown in

Similarly to the parity check matrix described in

According to the simulation performed by the present applicant, favorable BER/FER are obtained for the Sony codes of (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15), and thus, it is possible to ensure favorable communication quality in data transmission using the Sony codes of (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15).

In the parity check matrix H of the Samsung codes of (64 k, 6/15), (64 k, 8/15), and (64 k, 12/15), column weights from the first column to the KX1-th column are X1, a column weight of the KX2-th column is X2, a column weight of the KY1-th column is Y1, a column weight of the KY2-th is Y2, a column weight of the (M−1)-th column is 2, and a column weight of the last column is 1.

Here, KX1+KX2+KY1+KY2+M−1+1 is equal to the code length N=64,800 bits of the Samsung codes of (64 k, 6/15), (64 k, 8/15), and (64 k, 12/15).

The column numbers KX1, KX2, KY1, KY2, and M and the column weights X1, X2, Y1, and Y2 of the parity check matrix H of the Samsung codes of (64 k, 6/15), (64 k, 8/15), and (64 k, 12/15) are shown in

In the parity check matrix H of the LGE codes of (16 k, 6/15), (16 k, 7/15), (16 k, 9/15), (16 k, 11/15), and (16 k, 13/15), column weights from the first column to the KX1-th column are X1, a column weight of the KX2-th column is X2, a column weight of the KY1-th column is Y1, a column weight of the KY2-th column is Y2, a column weight of the (M−1)-th column is 2, and a column weight of the last column is 1.

Here, KX1+KX2+KY1+KY2+M−1+1 is equal to the code length N=16,200 bits of the LGE codes of (16 k, 6/15), (16 k, 7/15), (16 k, 9/15), (16 k, 11/15), and (16 k, 13/15).

The column numbers KX1, KX2, KY1, KY2, and M and the column weights X1, X2, Y1, and Y2 of the parity check matrix H of the LGE codes of (16 k, 6/15), (16 k, 7/15), (16 k, 9/15), (16 k, 11/15), and (16 k, 13/15) are shown in

In the parity check matrix H of the LGE code of (64 k, 10/15), a column weight from the first column to the KX1-th column is X1, a column weight of the KX2-th column is X2, a column weight of the KY1-th column is Y1, a column weight of the KY2-th is Y2, a column weight of the (M−1)-th column is 2, and a column weight of the last column is 1.

Here, KX1+KX2+KY1+KY2+M−1+1 is equal to the code length N=64,800 bits of the LGE code of (64 k, 10/15).

The column numbers KX1, KX2, KY1, KY2, and M and the column weights X1, X2, Y1, and Y2 of the parity check matrix H of the LGE code of (64 k, 10/15) are shown in

In the parity check matrix H of the NERC code of (64 k, 9/15), column weights from the first column to the KX1-th column are X1, a column weight of the KX2-th column is X2, a column weight of the KY1-th column is Y1, a column weight of the KY2-th column is Y2, a column weight of the (M−1)-th column is 2, and a column weight of the last column is 1.

Here, KX1+KX2+KY1+KY2+M−1+1 is equal to the code length N=64,800 bits of the NERC code of (64 k, 9/15).

The column numbers KX1, KX2, KY1, KY2, and M and the column weights X1, X2, Y1, and Y2 of the parity check matrix H of the NERC code of (64 k, 9/15) are shown in

In the parity check matrix H of the ETRI code of (16 k, 5/15), a parameter g=M_{1 }is 720.

Since the ETRI code of (16 k, 5/15) has a code length N of 16,200 and a code rate r of 5/15, an information length K=N×r is 16,200×5/15=5,400, and a parity length M=N−K is 16,200-5,400=10,800.

A parameter M_{2}=M−M_{1}=N−K−g is 10,800−720=10,080.

Accordingly, a parameter Q_{1}=M_{1}/P is 720/360=2, and a parameter Q_{2}=M_{2}/P is 10,080/360=28.

Parameters g=M_{1}, M_{2}, Q_{1 }and Q_{2 }for the parity check matrix H of the ETRI codes of (64 k, 5/15), (64 k, 6/15), and (64 k, 7/15) are shown in

Constellation

For example, in the transmission system of

That is, in the transmission system of

In the transmission system of

As the constellation, there are a uniform constellation (UC) in which signal points are uniformly arranged, and a non-uniform constellation (NUC) in which signal points are not uniformly arranged.

As the NUC, for example, there is a constellation called a 1-dimensional M^{2}-QAM non-uniform constellation (1D NUC) and a constellation called a 2-dimensional QQAM non-uniform constellation (2D NUC).

In general, the 1D NUC can improve a BER further than the UC, and the 2D NUC can improve a BER further than the 1D NUC.

The constellation of the QPSK modulation scheme is the UC. As the constellation of the 16-QAM, 64-QAM or 256-QAM modulation scheme, it is possible to adopt, for example, the 2D NUC, and as the constellation of the 1024-QAM or 4096-QAM modulation scheme, it is possible to adopt, for example, the 1D NUC.

Hereinafter, the NUC constellation used in the MODCOD in which the modulation scheme is a modulation scheme of mapping a m-bit symbol to any one of 2^{m }number of signal points and the code rate of the LDPC code is r is described as a NUC_2^{m}_r.

For example, “NUC_16_6/15” refers to the NUC constellation used in the MODCOD in which the modulation scheme is a 16-QAM modulation scheme (in addition, a modulation scheme of mapping a symbol to any one of 16 signal points) and the code rate r of the LDPC code is 6/15.

In the transmission system of

In the transmission system of

Moreover, in the transmission system of

Accordingly, as described above, when the LDPC code is classified into nine types of LDPC codes having r=5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12, 15, 13/15 according to the code rate r, one type of constellation is provided for QPSK, nine types of 2D NUC constellations are provided for 16-QAM, 64-QAM and 256-QAM, and nine types of 1D NUC constellations are provided for 1024-QAM and 4096-QAM.

In _{1}} and Im{x_{1}} are respectively a real part and an imaginary part of a signal point x_{1}, as a coordinate of the signal point x_{1}.

In

In _{q}” represents the coordinate of a signal point z_{q}. The index q of the signal point z_{q }represents a discrete time of a symbol (a time interval between a given symbol and the next symbol).

In _{q }is represented in the form of a complex number, and i represents an imaginary unit (√(−1)).

In ^{m}_r represents the coordinate of the signal point of the 2D NUC used when the modulation scheme is 2^{m}-QAM and the code rate of the LDPC code is r.

Similarly to _{q }is represented in the form of a complex number, and i represents an imaginary unit.

In

In the 2D NUC, a signal point in a second quadrant of the constellation is disposed in a position where the signal point in the first quadrant is symmetrically moved with respect to the Q axis, and a signal point in a third quadrant of the constellation is disposed in a position where the signal point in the first quadrant is symmetrically moved with respect to an origin. A signal point in a fourth quadrant of the constellation is disposed in a position where the signal point in the first quadrant is symmetrically moved with respect to the I axis.

Here, when the modulation scheme is 2^{m}-QAM, m bits are used as one symbol, and the one symbol is mapped to a signal corresponding to the symbol.

The m-bit symbol is represented as, for example, an integer value of 0 to 2^{m}−1. However, when b=2^{m}/4, symbols y(0), y(1), . . . , and y(2^{m}−1) that are expressed as integer values of 0 to 2^{m}−1 can be classified into four symbols including symbols y(0) to y(b−1), y(b) to y(2b−1), y(2b) to y(3b−1), and y(3b) to y(4b−1).

In

The coordinate of a signal point corresponding to a symbol y(k+b) in a range of symbols y(b) to y(2b−1) is represented as −conj(w # k), the coordinate of a signal point corresponding to a symbol y(k+2b) in a range of symbols y(2b) to y(3b−1) is represented as conj(w # k), and the coordinate of a signal point corresponding to a symbol y(k+3b) in a range of symbols y(3b) to y(4b−1) is represented as −w # k.

Here, conj(w # k) represents complex conjugates of w # k.

For example, when the modulation scheme is 16-QAM, symbols y(0), y(1), . . . , and y(15) of m=4 bits are classified into four symbols including symbols y(0) to y(3), y(4) to y(7), y(8) to y(11) and y(12) to y(15) since b=2^{4}/4=4.

Furthermore, for example, since the symbol y(12) of the symbols y(0) to y(15) is a symbol y(k+3b)=y(0+3×4) in a range of symbols y(3b) to y(4b−1) and k=0, the coordinate of a signal point of the symbol y(12) is −w # k=−w0.

When the code rate r of the LDPC code is, for example, 9/15, since w0 (NUC_16_9/15) when the modulation scheme is 16-QAM and the code rate r is 9/15 is 0.4967+1.1932i according to

In

u # k represents a real part Re(z_{q}) and an imaginary part Im(z_{q}) of a complex number as the coordinate of the signal point z_{q }of the 1D NUC.

_{q}) and the imaginary part Im(z_{q}) of the complex number representing the coordinate of the signal point z_{q }of the 1D NUC corresponding to the symbol y.

It is assumed that a 10-bit symbol y of 1024-QAM is represents as y_{0, q}, y_{1, q}, y_{2, q}, y_{3, q}, y_{4, q}, y_{5, q}, y_{6, q}, y_{7, q}, y_{8, q}, y_{9, q }from the leading bit (most significant bit).

_{0, q}, y_{2, q}, y_{4, q}, y_{6, q}, y_{8, q }of the symbol y and u # k representing the real part Re(z_{q}) of (the coordinate of) the signal point z_{q }corresponding to the symbol y.

_{1, q}, y_{3, q}, y_{5, q}, y_{7, q}, y_{9, q }of the symbol y and u # k representing the imaginary part Im(z_{q}) of (the coordinate of) the signal point z_{q }corresponding to the symbol y.

When the 10-bit symbol y=(y_{0, q}, y_{1, q}, y_{2, q}, y_{3, q}, y_{4, q}, y_{5, q}, y_{6, q}, y_{7, q}, y_{8, q}, y_{9, q}) of 1024-QAM is, for example, (0, 0, 1, 0, 0, 1, 1, 1, 0, 0), five odd-numbered bits (y_{0, q}, y_{2, q}, y_{4, q}, y_{6, q}, y_{8, q}) are (0, 1, 0, 1, 0), and five even-numbered bits (y_{1, q}, y_{3, q}, y_{5, q}, y_{7, q}, y_{9, q}) are (0, 0, 1, 1, 0).

In _{q}) of the signal point z_{q }corresponding to the symbol y=(0, 0, 1, 0, 0, 1, 1, 1, 0, 0) corresponds to u3.

Moreover, in _{q}) of the signal point z_{q }corresponding to the symbol y=(0, 0, 1, 0, 0, 1, 1, 1, 0, 0) is u11.

Meanwhile, when it is assumed that the code rate r of the LDPC code is, for example, 7/15, u3 of the 1D NUC(NUC_1 k_7/15) used when the modulation scheme is 1024-QAM and the code rate r of the LDPC code is 7/15 is 1.1963, and u11 is 6.9391 according to

Accordingly, the real part Re(z_{q}) of the signal point z_{q }corresponding to the symbol y=(0, 0, 1, 0, 0, 1, 1, 1, 0, 0) is u3=1.1963, and Im(z_{q}) is u11=6.9391. As a result, the coordinate of a signal point z_{q }corresponding to the symbol y=(0, 0, 1, 0, 0, 1, 1, 1, 0, 0) is represented as 1.1963+6.9391i.

In

u # k represents a real part Re(z_{q}) and an imaginary part Im(z_{q}) of a complex number as the coordinate of the signal point z_{q }of the 1D NUC.

_{q}) and the imaginary part Im(z_{q}) of the complex number representing the coordinate of the signal point z_{q }of the 1D NUC corresponding to the symbol y.

Since a method of obtaining the coordinate of the signal point of the 1D NUC of 4096-QAM using

Similarly to _{1}} and Im{x_{1}} represent a real part and an imaginary part of a signal point x_{1 }as the coordinate of the signal point x_{1}. In

In ^{m}_r represents the coordinate of the signal point of the 2D NUC used when the modulation scheme is 2^{m}_QAM and the code rate of the LDPC code is r, similarly to

The signal points of the 1D NUC are arranged in a straight line parallel to the I axis or a straight line parallel to the Q axis in a lattice shape. An interval between the signal points is not uniform. When (data mapped to) the signal points is transmitted, an average power of the signal point on the constellation is normalized. When it is assumed that a root-mean-square value of an absolute value of (coordinates of) all signal points on the constellation is represented as P_{ave}, the normalization is performed by multiplying the reciprocal 1/(√P_{ave}) of the respective signal points z_{q }on the constellation by the square root √P_{ave }of the root-mean-square value P_{ave}.

According to the constellations described in

Block Interleaver **25**

**25** of

The block interleaver **25** includes a storage region called a part 1, and a storage region called a part 2.

Both of the parts 1 and 2 are configured in such a manner that columns as storage regions that store one bit in a row (transverse) direction and store a predetermined number of bits in a column (longitudinal) direction are arranged by a number C equal to m which is the number of bits of a symbol in the row direction.

When it is assumed that the number of bits (hereinafter, referred to as a part column length) stored in the column direction by the columns of the part 1 is represented as R1 and the part column length of the columns of the part 2 is represented as R2, (R1+R2)×C is equal to the code length N (64,800 bits or 16,200 bits in the first embodiment) of the LDPC code to be subject to the block interleaving.

The part column length R1 is equal to a multiple of 360 bits which is the unit size P, and the part column length R2 is equal to the remainder when the sum (hereinafter, referred to as a column length) R1+R2 of the part column length R1 of the part 1 and the part column length R2 of the part 2 is divided by 360 bits which is the unit size P.

Here, the column length R1+R2 is equal to the value obtained by dividing the code length N of the LDPC code to be subject to the block interleaving by the number of bits m of the symbol.

When 16-QAM is adopted as the modulation scheme, since the number of bits m of the symbol is 4 bits, the column length R1+R2 of the LDPC code having a code length N of 16,200 bits is 4,050(=16,200/4) bits.

Furthermore, since the remainder when the column length R1+R2=4,050 is divided by 360 bits which is the unit size P is 90, the part column length R2 of the part 2 is 90 bits.

The part column length R1 of the part 1 is R1+R2-R2=4,050−90=3,960 bits.

**25** of

The block interleaver **25** performs the block interleaving by writing and reading the LDPC code in and from the parts 1 and 2.

That is, in the block interleaving, as shown in

When the writing of the code bits in the bottommost region of the rightmost column (C-th column) of the columns of the part 1 is ended, the writing of the remaining code bits in the columns of the part 2 from the top to the bottom (in the column direction) is performed in the columns from the left to the right.

Subsequently, when the writing of the code bits in the bottommost region of the rightmost column (C-th column) of the columns of the part 2 is ended, the code bits are read from the first columns of all of C number of columns of the part 1 in the row direction for every C=m bits as shown in

The reading of the code bits from all of C number of columns of the part 1 is sequentially performed in the lower rows, and when the reading from the R1 row which is the last row is ended, the code bits are read from the first rows of all of C number of columns of the part 2 in the row direction for every C=m bits.

The reading of the code bits from all of C number of columns of the part 2 is sequentially performed in the lower rows, and the reading is performed up to the R2 row which is the last row.

As stated above, the code bits read for every m bits from the parts 1 and 2 are supplied as the symbol to the mapper **117** (

Group-Wise Interleaving

**24** of

In the group-wise interleaving, the LDPC code of one codeword is interleaved for every bit group according to a predetermined pattern (hereinafter, referred to as a GW pattern) by using 360 bits corresponding to one group obtained by dividing the LDPC code of one codeword from the leading code for every 360 bits equal to the unit size P into the bit groups.

Hereinafter, a (i+1)-th bit group from a leading bit group when the LDPC code of one codeword is divided into the bit groups is referred to as a bit group i.

When the unit size P is 360 bits, the LDPC code having the code length N of, for example, 1,800 bits is divided into 5 (=1,800/360) bit groups of bit groups 0, 1, 2, 3 and 4. For example, the LDPC code having the code length N of 16,200 bits is divided into 45 (=16,200/360) bit groups of bit groups 0, 1, . . . , and 44, and the LDPC code having the code length N of 64,800 bits is divided into 180 (=64,800/360) bit groups of bit groups 0, 1, . . . , and 179.

In the following description, it is assumed that the GW pattern is represented as the arrangement of numbers representing the bit groups. For example, the GW pattern of 4, 2, 0, 3, 1 for the LDPC code having the code length N of 1,800 bits represents that the arrangement of bit groups 0, 1, 2, 3 and 4 is interleaved (rearranged) into the arrangement of bit groups 4, 2, 0, 3 and 1.

The GW pattern can be set for at least the code length N of the LDPC code.

Example of GW Pattern for LDPC Code of 64 k Bits

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

It is possible to apply the first to thirty-third examples of the GW pattern for the LDPC code having the code length N of 64 k bits described above to any combination of LDPC codes having a code length N of 64 k bits and an arbitrary code rate r and an arbitrary modulation scheme (constellation).

It is possible to further improve an error rate of each of the combinations by setting the GW pattern to be applied for each of the combinations of the code lengths N of the LDPC code and the code rates r of the LDPC code and the modulation schemes (constellations) in the group-wise interleaving.

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

Example of GW Pattern for LDPC Code of 16 k Bits

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

According to the GW pattern of

It is possible to apply the first to sixteenth examples of the GW pattern for the LDPC code having the code length N of 16 k bits to any combination of LDPC codes having a code length N of 16 k bits and an arbitrary code rate r and an arbitrary modulation scheme (constellation).

As mentioned above, it is possible to further improve an error rate of each of the combinations by setting the GW pattern to be applied for each of the combinations of the code lengths N of the LDPC code and the code rates r of the LDPC code and the modulation schemes (constellations) in the group-wise interleaving.

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

It is possible to achieve a favorable error rate by applying the GW pattern of

Simulation Result

**13** (

In

According to

In addition to the QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM constellations having the arrangements of signal points shown in

In addition to the QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM constellations having the arrangements of signal points shown in

Configuration Example of Reception Apparatus **12**

**12** of

An OFDM operation unit **151** receives an OFDM signal from the transmission apparatus **11** (**151** is supplied to a frame management unit **152**.

The frame management unit **152** performs processing (frame analysis) on a frame constituted by data supplied from the OFDM operation unit **151**, and respectively supplies a signal of target data obtained as the result and a signal of control data to frequency deinterleavers **161** and **153**.

The frequency deinterleaver **153** performs frequency deinterleaving on the data from the frame management unit **152** for every symbol, and supplies data obtained as the result to a demapper **154**.

The demapper **154** performs quadrature demodulation by demapping (signal point arrangement decoding) data (data on the constellation) from the frequency deinterleaver **153** based on the arrangement (constellation) of signal points determined through the quadrature modulation performed by the transmission apparatus **11**, and supplies data ((likelihood of) LDPC code) obtained as the result to an LDPC decoder **155**.

The LDPC decoder **155** performs LDPC decoding on the LDPC code from the demapper **154**, and supplies LDPC target data (here, a BCH code) obtained as the result to a BCH decoder **156**.

The BCH decoder **156** performs BCH decoding on the LDPC target data from the LDPC decoder **155**, and outputs control data (signaling) obtained as the result.

Meanwhile, the frequency deinterleaver **161** performs frequency deinterleaving on the data from the frame management unit **152** for every symbol, and supplies data obtained as the result to a SISO/MISO decoder **162**.

The SISO/MISO decoder **162** performs space-time decoding on the data from the frequency deinterleaver **161**, and supplies data obtained as the result to a time deinterleaver **163**.

The time deinterleaver **163** performs time deinterleaving on the data from the SISO/MISO decoder **162** for every symbol, and supplies data obtained as the result to a demapper **164**.

The demapper **164** performs quadrature demodulation by demapping (signal point arrangement decoding) the data (data on the constellation) from the time deinterleaver **163** based on the arrangement (constellation) of signal points determined through the quadrature modulation performed by the transmission apparatus **11**, and supplies data obtained as the result to a bit deinterleaver **165**.

The bit deinterleaver **165** performs bit deinterleaving on the data from the demapper **164**, and supplies (likelihood of) an LDPC code which is data on which the bit interleaving has been performed to an LDPC decoder **166**.

The LDPC decoder **166** performs LDPC decoding on the LDPC code from the bit deinterleaver **165**, and supplies LDPC target data (here, a BCH code) obtained as the result to a BCH decoder **167**.

The BCH decoder **167** performs BCH decoding on the LDPC target data from the LDPC decoder **155**, and supplies data obtained as the result to a BB descrambler **168**.

The BB descrambler **168** performs BB descrambling on the data from the BCH decoder **167**, and supplies data obtained as the result to a null deletion unit **169**.

The null deletion unit **169** deletes the Nulls inserted by the padder **112** of **168**, and supplies data obtained as the result to a demultiplexer **170**.

The demultiplexer **170** splits one or more streams (target data) multiplexed to the data from the null deletion unit **169**, performs necessary processing on the split data items, and outputs the processed data items as an output stream.

The reception apparatus **12** may be configured without including some of the blocks shown in **11** (**118**, the SISO/MISO encoder **119**, the frequency interleaver **120** and the frequency interleaver **124**, the reception apparatus **12** may be configured without including the time deinterleaver **163**, the SISO/MISO decoder **162**, the frequency deinterleaver **161** and the frequency deinterleaver **153** which are the blocks respectively corresponding to the time interleaver **118**, the SISO/MISO encoder **119**, the frequency interleaver **120** and the frequency interleaver **124** of the transmission apparatus **11**.

Configuration Example of Bit Deinterleaver **165**

**165** of

The bit deinterleaver **165** includes a block deinterleaver **54**, and a group-wise deinterleaver **55**, and performs (bit) deinterleaving of symbol bits of a symbol which is the data from the demapper **164** (

That is, the block deinterleaver **54** performs block deinterleaving (reverse processing of the block interleaving) corresponding to the block interleaving performed by the block interleaver **25** of **164** as a target, that is, block deinterleaving that returns the positions of (likelihood of) the code bits of the LDPC code rearranged by the block interleaving to the original positions, and supplies an LDPC code obtained as the result to the group-wise deinterleaver **55**.

The group-wise deinterleaver **55** performs group-wise deinterleaving (reverse processing of the group-wise interleaving) corresponding to the group-wise interleaving performed by the group-wise interleaver **24** of **54** as a target, that is, group-wise deinterleaving which returns the arrangement to the original arrangement by rearranging the code bits of the LDPC code whose arrangement is changed for every bit group by, for example, the group-wise interleaving described in

Here, when the parity interleaving, the group-wise interleaving and the block interleaving are performed on the LDPC code supplied to the bit deinterleaver **165** from the demapper **164**, it is possible to perform all of parity deinterleaving (reverse processing of the parity interleaving, that is, parity deinterleaving that returns the arrangement of the code bits of the LDPC code whose arrangement is changed by the parity interleaving to the original arrangement) corresponding to the parity interleaving, block deinterleaving corresponding to the block interleaving, and group-wise deinterleaving corresponding to the group-wise interleaving in the bit deinterleaver **165**.

In the bit deinterleaver **165** of **54** that performs the block deinterleaving corresponding to the block interleaving, and the group-wise deinterleaver **55** that performs the group-wise deinterleaving corresponding to the group-wise interleaving are provided. However, the block that performs the parity deinterleaving corresponding to the parity interleaving is not provided, and thus, the parity deinterleaving is not performed.

Accordingly, the LDPC code on which the block deinterleaving and the group-wise deinterleaving have been performed and the parity deinterleaving has not been performed is supplied to the LDPC decoder **166** from (the group-wise deinterleaver **55** of) the bit deinterleaver **165**.

The LDPC decoder **166** performs the LDPC decoding on the LDPC code from the bit deinterleaver **165** by using a transformation check matrix (or the transformation check matrix (**115** of

**164**, the bit deinterleaver **165** and the LDPC decoder **166** of

In step S**111**, the demapper **164** performs quadrature demodulation by demapping the data (data on the constellation mapped to the signal point) from the time deinterleaver **163**, and supplies data obtained as the result to the bit deinterleaver **165**. The process then proceeds to step S**112**.

In step S**112**, the bit deinterleaver **165** performs the deinterleaving (bit deinterleaving) on the data from the demapper **164**, and the process proceeds to step S**113**.

That is, in step S**112**, in the bit deinterleaver **165**, the block deinterleaver **54** performs the block deinterleaving on the data (symbol) from the demapper **164** as a target, and supplies the code bits of the LDPC code obtained as the result to the group-wise deinterleaver **55**.

The group-wise deinterleaver **55** performs the group-wise interleaving on the LDPC code from the block deinterleaver **54** as a target, and supplies (the likelihood of) the LDPC code obtained as the result to the LDPC decoder **166**.

In step S**113**, the LDPC decoder **166** performs the LDPC decoding on the LDPC code from the group-wise deinterleaver **55** by using the parity check matrix H used in the LDPC encoding performed by the LDPC encoder **115** of **167**.

Similarly to the case of **54** that performs the block deinterleaving and the group-wise deinterleaver **55** that performs the group-wise deinterleaving are individually provided, but the block deinterleaver **54** and the group-wise deinterleaver **55** may be integrally configured.

LDPC Decoding The LDPC decoding performed in the LDPC decoder **166** of

As described above, in the LDPC decoder **166** of **55** on which the block deinterleaving and the group-wise deinterleaving have been performed and the parity deinterleaving has not been performed by using the transformation check matrix (or the transformation check matrix (**115** of

Here, it has been previously suggested to use the LDPC decoding capable of allowing an operation frequency to fall within a sufficiently realizable range while suppressing a circuit scale by performing the LDPC decoding using the transformation check matrix (for example, see U.S. Pat. No. 4,224,777).

The LDPC decoding using the transformation check matrix that has been previously suggested will be described with reference to

In

In the parity check matrix H of

Row permutation: (6*s+t+*1)-th row→(5*t+s+*1)-th row (11)

Column permutation: (6*x+y+*61)-th column→(5*y+x+*61)-th column (12)

Here, in Expressions (11) and (12), s, t, x and y are respectively integers in a range of 0≤s<5, 0≤t<6, 0≤x<5, and 0≤t<6.

According to the row permutation of Expression (11), the 1^{st}, 7^{th}, 13^{th}, 19^{th }and 25^{th }rows which have a remainder of 1 by being divided by 6 are respectively permuted to the 1^{st}, 2^{nd}, 3^{rd}, 4^{th }and 5^{th }rows, and the 2^{nd}, 8^{th}, 14^{th}, 20^{th }and 26^{th }rows which have a remainder of 2 by being divided by 6 are respectively permuted to the 6^{th}, 7^{th}, 8^{th}, 9^{th }and 10^{th }rows.

According to the column permutation of Expression (12), the permutation is performed on the 61^{st }column and the subsequent columns (parity matrix) such that the 61^{st}, 67^{th}, 73^{rd}, 79^{th }and 85^{th }columns which have a remainder of 1 by being divided by 6 are respectively permuted to the 61^{st}, 62^{nd}, 63^{rd}, 64^{th }and 65^{th }columns, and 62^{nd}, 68^{th}, 74^{th}, 80^{th }and 86^{th }columns which have a remainder **2** by being divided by 6 are respectively permuted to the 66^{th}, 67^{th}, 68^{th}, 69^{th }and 70^{th }columns.

In this manner, the matrix obtained by performing the row and column permutations on the parity check matrix H of

Here, the arrangement of the code bits of the LDPC code are not influenced even when the row permutation of the parity check matrix H is performed.

The column permutation of Expression (12) corresponds to the parity interleaving when the information length K is 60, the unit size P is 5 and the divisor q(=M/P) of the parity length M (here, 30) is 6 in the parity interleaving that interleaves the (K+qx+y+1)-th code bit into the position of the (K+Py+x+1)-th code bit.

Accordingly, the parity check matrix H′ of

When the LDPC code of the original parity check matrix H of ^{T }becomes the 0 vector in view of properties of the parity check matrix, H′c′^{T }also becomes the 0 vector.

As stated above, the transformation parity check matrix H′ of

Accordingly, the column permutation of Expression (12) is performed on the LDPC code c of the original parity check matrix H, and decoding (LDPC decoding) is performed on the LDPC code c′ after the column permutation by using the transformation check matrix H′ of

In

The transformation check matrix H′ of

It is possible to use an architecture in which the check node calculation and the variable node calculation are simultaneously performed p times in the decoding of the LDPC code of the parity check matrix represented as P×P constitutive matrices.

That is,

The decoding device of **300** including six FIFOs **300**_{1 }to **300**_{6}, a selector **301** that selects the FIFOs **300**_{1 }to **300**_{6}, a check node calculating unit **302**, two cyclic shift circuits **303** and **308**, an edge data storing memory **304** including 18 FIFOs **304**_{1 }to **304**_{18}, a selector **305** that selects the FIFOs **304**_{1 }to **304**_{18}, a reception data memory **306** that stores reception data, a variable node calculating unit **307**, a decoded word calculating unit **309**, a reception data rearrangement unit **310**, and a decoded data rearrangement unit **311**.

A method of storing data in the edge data storing memories **300** and **304** will be initially described.

The edge data storing memory **300** includes the FIFOs **300**_{1 }to **300**_{6 }of which there are 6 which is a value obtained by dividing 30 which is the number of rows of the transformation check matrix H′ of **300**_{y }(y=1, 2, . . . , and 6) includes storage regions of multiple stages, and messages corresponding to five edges of which the number thereof corresponds to the number of the rows and the number of columns (unit size P) can be simultaneously read from and written in the storage region of each stage. The number of the stages of the storage regions of the FIFO **300**_{y }is 9 which is the maximum number of the number of 1s (Hamming weight) of the transformation check matrix of

Data (message v_{1 }from the variable nodes) corresponding to the positions of 1s from the first row to the fifth row of the transformation check matrix H′ of **300**_{1 }while the data and the respective rows fill in the transverse direction (0 is ignored). That is, when an element in the j-th row and the i-th column is represented as (j, i), data corresponding to the positions of 1s of the 5×5 unit matrix from (1, 1) to (5, 5) of the transformation check matrix H′ is stored in the storage region of the first stage of the FIFO **300**_{1}. Data corresponding to the positions of 1s of the shift matrix (matrix obtained by cyclic-shifting the 5×5 unit matrix to the right by 3) from (1, 21) to (5, 25) of the transformation check matrix H′ is stored in the storage region of the second stage. Similarly, data are stored in the storage regions of the third and eighth stages so as to be associated with the transformation check matrix H′. Data corresponding to the positions of 1s of the shift matrix (matrix obtained by cyclic-shifting a matrix obtained by replacing 1s of the first row of the 5×5 unit matrix with 0s to the right by 1) from (1, 86) to (5, 90) of the transformation check matrix H′ is stored in the storage region of the ninth stage.

Data corresponding to the positions of 1s from the sixth row to the tenth row of the transformation check matrix H′ of **300**_{2}. That is, data corresponding to the positions of 1s of the first shift matrix constituting the sum matrix (sum matrix which is the sum of the first shift matrix obtained by cyclic-shifting the 5×5 unit matrix to the right by 1 and the second shift matrix obtained by cyclic-shifting the 5×5 unit matrix to the right by 2) from (6, 1) to (10, 5) of the transformation check matrix H′ is stored in the storage region of the first stage of the FIFO **300**_{2}. Further, data corresponding to the positions of 1s of the second shift matrix constituting the sum matrix from (6, 1) to (10, 5) of the transformation check matrix H′ is stored in the storage region of the second stage.

That is, in the case of the constitutive matrices having two or more weights, when the constitutive matrices are represented as the sum of multiple matrices of a P×P unit matrix having a weight of 1, a quasi-unit matrix in which one or more 1s of the elements of 1s of the unit matrix become 0s, and a shift matrix obtained by cyclic-shifting the unit matrix or the quasi-unit matrix, data (messages corresponding to the edges belonging to the unit matrix, the quasi-unit matrix or the shift matrix) corresponding to the positions of 1s of the unit matrix having the weight of 1, the quasi-unit matrix or the shift matrix is stored in the same address (the same FIFO of the FIFOs **300**_{1 }to **300**_{6}).

Hereinafter, data are stored in the storage regions of the third to ninth stages so as to be associated with the transformation check matrix H′.

Similarly, data are stored in the FIFOs **300**_{3 }to **300**_{6 }so as to be associated with the transformation check matrix H′.

The edge data storing memory **304** includes FIFOs **304**_{1 }to **304**_{18 }of which there are 18 which is a value obtained by dividing 90 which is the number of rows of the transformation check matrix H′ by 5 which is the number of columns (unit size P) of the constitutive matrices. The FIFO **304**_{x }(x=1, 2, . . . , and 18) includes storage regions of multiple stages, and messages corresponding to five edges of which the number thereof corresponds to the number of rows and the number of columns (unit size P) can be simultaneously read from and written in the storage regions of the multiple stages.

Data (messages u_{j }from the check nodes) corresponding to the positions of 1s from the first column to the fifth column of the transformation check matrix H′ of **304**_{1 }while the data and the respective columns fill in the longitudinal direction (0 is ignored). That is, data corresponding to the positions of 1s of the 5×5 unit matrix from (1, 1) to (5, 5) of the transformation check matrix H′ is stored in the storage region of the first stage of the FIFO **304**_{1}. Data corresponding to the positions of 1s of the first shift matrix constituting the sum matrix (sum matrix of the first shift matrix obtained by cyclic-shifting the 5×5 unit matrix to the right by 1 and the second shift matrix obtained by cyclic-shifting the 5×5 unit matrix to the right by 2) from (6, 1) to (10, 5) of the transformation check matrix H′ is stored in the storage region of the second stage. Furthermore, data corresponding to the positions of 1s of the second shift matrix constituting the sum matrix from (6, 1) to (10, 5) of the transformation check matrix H′ is stored in the storage region of the third stage.

That is, in the case of the constitutive matrices having two or more weights, when the constitutive matrices are represented as the sum of multiple matrices of a P×P unit matrix having a weight of 1, a quasi-unit matrix in which one or more 1s of the elements of 1s of the unit matrix become 0s, and a shift matrix obtained by cyclic-shifting the unit matrix or the quasi-unit matrix, data (messages corresponding to the edges belonging to the unit matrix, the quasi-unit matrix or the shift matrix) corresponding to the positions of 1s of the unit matrix having the weight of 1, the quasi-unit matrix or the shift matrix is stored in the same address (the same FIFO of the FIFOs **304**_{1 }to **304**_{18}).

Hereinafter, data are stored in the storage regions of the fourth and fifth stages so as to be associated with the transformation check matrix H′. The number of the stages of the storage regions of the FIFO **304**_{1 }is 5 which is the maximum number of the number of 1s (Hamming weight) from the first column to the fifth column of the transformation check matrix H′ in the row direction.

Similarly, data are stored in the FIFOs **304**_{2 }to **304**_{3 }so as to be associated with the transformation check matrix H′, and the respective lengths thereof (the number of stages) are 5. Similarly, data are stored in the FIFOs **304**_{4 }to **304**_{12 }so as to be associated with the transformation check matrix H′, and the respective lengths thereof are 3. Similarly, data are stored in the FIFOs **304**_{13 }to **304**_{18 }so as to be associated with the transformation check matrix H′, and the respective lengths thereof are 2.

Next, the operation of the decoding device of

The edge data storing memory **300** includes the 6 FIFOs **300**_{1 }to **300**_{6}, and the FIFO for storing data is selected from the FIFOs **300**_{1 }to **300**_{6 }based on information (matrix data) D**312** indicating a row of the transformation check matrix H′ of **311** supplied from the cyclic shift circuit **308** at the previous stage belong, and the five messages D**311** are sequentially stored in the selected FIFO all at once. When data is read, the edge data storing memory **300** sequentially reads the five messages D**300**_{1 }from the FIFO **300**_{1}, and supplies the read messages to the selector **301** at the next stage. After the reading of the messages from the FIFO **300**_{1 }is finished, the edge data storing memory **300** sequentially reads the messages from the FIFO **300**_{2 }to **300**_{6}, and supplies the read messages to the selector **301**.

The selector **301** selects the five messages from the FIFO of the FIFOs **300**_{1 }to **300**_{6 }from which the data is currently being read in response to a selector signal D**301**, and supplies the selected messages as messages D**302** to the check node calculating unit **302**.

The check node calculating unit **302** includes five check node calculators **302**_{1 }to **302**_{5}, performs the check node calculation according to Expression (7) by using the messages D**302** (D**302**_{1 }to D**302**_{5}) (messages v_{1 }of Expression (7)) supplied through the selector **301**, and supplies five messages D**303** (D**303**_{1 }to D**303**_{5}) (messages u_{j }of Expression (7)) obtained as the result of the check node calculation to the cyclic shift circuit **303**.

The cyclic shift circuit **303** performs cyclic-shifting of the five messages D**303**_{1 }to D**303**_{5 }obtained in the check node calculating unit **302** based on information (matrix data) D**305** indicating the corresponding edge based on how many times the cyclic-shifting is performed on the unit matrix (or the qausi-unit matrix) as the original matrix in the transformation check matrix H′, and supplies the result as a message D**304** to the edge data storing memory **304**.

The edge data storing memory **304** includes the 18 FIFO **304**_{1 }to **304**_{18}, and the FIFO for storing data is selected from the FIFOs **304**_{1 }to **304**_{18 }based on information D**305** indicating the row of the transformation check matrix H′ to which the 5 messages D**304** supplied from the cyclic shift circuit **303** at the previous stage belong, and the five messages D**304** are sequentially stored in the selected FIFO all at once. When data is read, the edge data storing memory **304** sequentially reads the five messages D**306**_{1 }from the FIFO **304**_{1}, and supplies the read messages to the selector **305** at the next stage. After the reading of the data from the FIFO **304**_{1 }is finished, the edge data storing memory **304** sequentially reads the messages from the FIFO **304**_{2 }to **304**_{18}, and supplies the read messages to the selector **305**.

The selector **305** selects the five messages from the FIFO of the FIFOs **304**_{1 }to **304**_{18 }from which the data is currently being read in response to a selector signal D**307**, and supplies the selected messages as messages D**308** to the variable node calculating unit **307** and the decoded word calculating unit **309**.

Meanwhile, the reception data rearrangement unit **310** rearranges an LDPC code D**313** corresponding to the parity check matrix H of **13** by the column permutation of Expression (12), and supplies the rearranged LDPC code as reception data D**314** to the reception data memory **306**. The reception data memory **306** calculates reception LLRs (log-likelihood ratios) from the reception data D**314** supplied from the reception data rearrangement unit **310**, and supplies the reception LLRs as reception values D**309** to the variable node calculating unit **307** and the decoded word calculating unit **309** by 5 LLRs all at once.

The variable node calculating unit **307** includes the five variable node calculators **307**_{1 }to **307**_{5}, performs the variable node calculation according to Expression (1) by using the messages D**308** (D**308**_{1 }to D**308**_{5}) (messages u_{j }of Expression (1)) supplied through the selector **305** and the five reception values D**309** (reception values u_{0i }of Expression (1)) supplied from the reception data memory **306**, and supplies messages D**310** (D**310**_{1 }to D**310**_{5}) (messages v_{1 }of Expression (1)) to the cyclic shift circuit **308**.

The cyclic shift circuit **308** performs the cyclic-shifting the messages D**310**_{1 }to D**310**_{5 }calculated in the variable node calculating unit **307** based on information indicating the corresponding edge based on how many times the cyclic-shifting is performed on the unit matrix (or the qausi-unit matrix) as the original matrix in the transformation check matrix H′, and supplies the result as a message D**311** to the edge data storing memory **300**.

It is possible to perform one decoding process (variable node calculation and check node calculation) on the LDPC code by performing the aforementioned operation once. After the LDPC code is decoded by a predetermined number of times, the decoding device of **309** and the decoded data rearrangement unit **311**.

That is, the decoded word calculating unit **309** includes five decoded word calculators **309**_{1 }to **309**_{5}, calculates the decoded result (decoded word) based on Expression (5) by using the five messages D**308** (D**308**_{1 }to D**308**_{5}) (messages u_{j }of Expression (5)) output from the selector **305** and the five reception values D**309** (reception values u_{0i }of Expression (5)) supplied from the reception data memory **306**, as the final stage of the multiple decoding processes, and supplies decoded data D**315** obtained as the result to the decoded data rearrangement unit **311**.

The decoded data rearrangement unit **311** rearranges the decoded data D**315** supplied from the decoded word calculating unit **309** by performing reverse permutation of the column permutation of Expression (12) on the decoded data, and outputs the rearranged data as a final decoded result D**316**.

As described above, by performing one or both of the row permutation and the column permutation on the parity check matrix (original parity check matrix) and transforming the parity check matrix to the parity check matrix (transformation check matrix) capable of being represented as the combination of the P×P unit matrix, the qausi-unit matrix in which one or more is of the elements of 1s of the unit matrix become 0s, the shift matrix obtained by cyclic-shifting the unit matrix or the qausi-unit matrix, the sum matrix which is the sum of multiple matrices of the unit matrix, the qausi-unit matrix and the shift matrix, and the P×P **0** matrix, that is, the combination of the constitutive matrices, it is possible to adopt the architecture in which the check node calculation and the variable node calculation are simultaneously performed P times which is less than the number of rows and the number of columns in the decoding of the LDPC code. When the architecture in which the node calculations (the check node calculation and the variable node calculation) are simultaneously performed P times which is less than the number of rows and the number of column of the parity check matrix is adopted, it is possible to allow the operation frequency to fall within the realizable range and to repeatedly perform the decoding multiple times unlike in the case where the node calculations are simultaneously performed by the number equal to the number of rows and the number of columns of the parity check matrix.

Similarly to the decoding device of **166** constituting the reception apparatus **12** of

That is, for the sake of convenience in the description, when the parity check matrix of the LDPC code output from the LDPC encoder **115** constituting the transmission apparatus **11** of **23** of the transmission apparatus **11**, the parity interleaving that interleaves the (K+qx+y+1)-th code bit to the position of the (K+Py+x+1)-th code bit is performed while the information length K is 60, the unit size P is 5 and the divisor q (=M/P) of the parity length M is 6.

As mentioned above, since the parity interleaving corresponds to the column permutation of Expression (12), it is not necessary to perform the column permutation of Expression (12) in the LDPC decoder **166**.

For this reason, in the reception apparatus **12** of **166** from the group-wise deinterleaver **55**, and the same processing as that of the decoding device of **166** except for the fact that the column permutation of Expression (12) is not performed.

That is, **166** of

In **166** has the same configuration as that of the decoding device of **310** of

As stated above, since the LDPC decoder **166** can be configured without including the reception data rearrangement unit **310**, it is possible to reduce the scale further than that of the decoding device of

For the sake of convenience in the description, in

That is, in the transmission apparatus **11** of **115** outputs, for example, the LDPC code in which the code length N is 64,800 or 16,200, the information length K is N−Pq(=N−M), the unit size P is 360 and the divisor q is M/P. However, it is possible to apply the LDPC decoder **166** of

Moreover, after the LDPC code is decoded in the LDPC decoder **166**, when the part of the parity bits of the decoded result is not necessary and only the information bits of the decoded result are output, it is possible to configure the LDPC decoder **166** without providing the decoded data rearrangement unit **311**.

Configuration Example of Block Deinterleaver **54**

**54** of

The block deinterleaver **54** has the same configuration as that of the block interleaver **25** described in

Accordingly, the block deinterleaver **54** includes the storage region called the part 1, and the storage region called the part 2, and both of the parts 1 and 2 are configured in such a manner that columns as the storage regions that store one bit in the row direction and store the predetermined number of bits in the column direction are arranged in the row direction by the number C equal to the number of bits m of the symbol.

The block deinterleaver **54** performs block interleaving by writing and reading the LDPC code in and from the parts 1 and 2.

In the block deinterleaving, the writing of the LDPC code (which is the symbol) is performed in the reading order of the LDPC code by the block interleaver **25** of

In addition, in the block deinterleaving, the reading of the LDPC code is performed in the writing order of the LDPC code by the block interleaver **25** of

That is, in the block interleaving performed in the block interleaver **25** of **54** of

Another Configuration Example of Bit Deinterleaver **165**

**165** of

In the drawing, the parts corresponding to the parts of

That is, the bit deinterleaver **165** of **1011** is newly provided.

In **165** includes a block deinterleaver **54**, a group-wise deinterleaver **55**, and a parity deinterleaver **1011**, and performs bit interleaving on the code bits of the LDPC code from the demapper **164**.

That is, the block deinterleaver **54** performs the block deinterleaving (reverse processing of the block interleaving) corresponding to the block interleaving performed by the block interleaver **25** of the transmission apparatus **11**, that is, the block deinterleaving that returns the positions of the code bits switched by the block interleaving to the original positions on the LDPC code from the demapper **164** as a target, and supplies the LDPC code obtained as the result to the group-wise deinterleaver **55**.

The group-wise deinterleaver **55** performs the group-wise deinterleaving corresponding to the group-wise interleaving as rearrangement processing performed by the group-wise interleaver **24** of the transmission apparatus **11** on the LDPC code from the block deinterleaver **54** as a target.

The LDPC code obtained as the result of the group-wise deinterleaving is supplied to the parity deinterleaver **1011** from the group-wise deinterleaver **55**.

The parity deinterleaver **1011** performs parity deinterleaving (reverse processing of the parity interleaving) corresponding to the parity interleaving performed by the parity interleaver **23** of the transmission apparatus **11**, that is, parity deinterleaving that returns the code bits of the LDPC code whose arrangement is changed by the parity interleaving to the original rearrangement on the code bits on which the group-wise deinterleaving in the group-wise deinterleaver **55** has been performed as a target.

The LDPC code obtained as the result of the parity deinterleaving is supplied to the LDPC decoder **166** from the parity deinterleaver **1011**.

Accordingly, in the bit deinterleaver **165** of **166**.

The LDPC decoder **166** performs the LDPC decoding on the LDPC code from the bit deinterleaver **165** by using the parity check matrix H used in the LDPC encoding performed by the LDPC encoder **115** of the transmission apparatus **11**. That is, the LDPC decoder **166** performs the LDPC decoding on the LDPC code from the bit deinterleaver **165** by using the parity check matrix H (of the DVB method) used in the LDPC encoding performed by the LDPC encoder **115** of the transmission apparatus **11**, using the transformation check matrix obtained by at least performing the column permutation corresponding to the parity interleaving on the parity check matrix H (in the ETRI method, parity check matrix (

Here, in **166** from (the parity deinterleaver **1011** of) the bit deinterleaver **165**, when the LDPC decoding on the LDPC code is performed using the parity check matrix H (of the DVB method) used in the LDPC encoding performed by the LDPC encoder **115** of the transmission apparatus **11** (in the ETRI method, the parity check matrix (**166** may be configured using a decoding device that performs the LDPC decoding using, for example, a full serial decoding scheme in which the calculation of the messages (check node messages and the variable node messages) is sequentially performed on the nodes bit by bit or a decoding device that performs the LDPC decoding using a full parallel decoding scheme in which the calculation of the messages is simultaneously performed on all of the nodes (in parallel).

When the LDPC decoding on the LDPC code is performed using the transformation check matrix obtained by at least performing the column permutation corresponding to the parity interleaving (in the ETRI method, the transformation check matrix (**115** of the transmission apparatus **11** in the LDPC decoder **166**, the LDPC decoder **166** may be configured as a decoding device of an architecture in which the check node calculation and the variable node calculation are simultaneously performed P (or divisors of P other than 1) times. Here, the decoding device may be a decoding device (**310** that switches the code bits of the LDPC code by performing the same column permutation as the column permutation (parity interleaving) for obtaining the transformation check matrix on the LDPC code.

For the sake in convenience in the description, in **54** that performs the block deinterleaving, the group-wise deinterleaver **55** that performs the group-wise deinterleaving, and the parity deinterleaver **1011** that performs the parity deinterleaving are individually configured. However, similarly to the parity interleaver **23**, the group-wise interleaver **24** and the block interleaver **25** of the transmission apparatus **11**, two or more of the block deinterleaver **54**, the group-wise deinterleaver **55** and the parity deinterleaver **1011** may be integrally configured.

**2. Second Embodiment**

However, in ATSC 3.0, two types of methods including a type A and a type B are adopted as the block interleaving method performed in (the block interleaver of) the bit interleaver **116** of

Here, the block interleaving of the type A is a method in which the writing of the LDPC code on which the group-wise interleaving has been performed in the column direction of columns as m number of storage regions that are arranged in the row direction is iteratively performed on m number of columns. The block interleaving of the type B is a method in which the writing of the LDPC code on which the group-wise interleaving has been performed for every bit group in the row direction of m number of columns is iteratively performed.

As stated above, since the two types of methods including the type A and the type B are adopted as the block interleaving method, in the transmission apparatus **11**, when the block interleaving is performed by (the block interleaver) of the bit interleaver **116**, the LDPC code is written in and read from the storage regions depending on the type A or the type B.

However, in the block interleaving of the type A and the block interleaving of the type B, since the writing method and a part of the reading method performed on the storage regions are different, it is necessary to provide two types of address generating circuits for generating a write address of the LDPC code and a read address of the LDPC code in (the block interleaver of) the bit interleaver **116**.

Similarly, in the reception apparatus **12**, even when the block deinterleaving is performed by (the block deinterleaver of) the bit deinterleaver **165**, the reading method and a part of the writing method performed on the storage regions are different depending on the type. For this reason, it is necessary to provide two types of address generating circuits for generating a read address of the LDPC code and a write address of the LDPC code in (the block deinterleaver of) the bit deinterleaver **165**.

As mentioned above, since it is necessary to provide two types of address generating circuits by adopting two types of method including the type A and the type B as the block interleaving method, it has been requested that the two types of methods including the type A and the type B efficiently coexist by realizing the block interleaving of the type A and the block interleaving of the type B by using a common address generating circuit.

Thus, as the second embodiment, a method of allowing a plurality of block interleaving methods (type A and type B) to efficiently coexist in the data transmission using the LDPC code will be described.

Configuration Example of Bit Interleaver **116**

**116** of

In the drawing, the parts corresponding to those in

That is, the bit interleaver **116** of **1021** and a block interleaver **1022** are provided instead of the group-wise interleaver **24** and the block interleaver **25** of

In **116** includes the parity interleaver **23**, the group-wise interleaver **1021**, and the block interleaver **1022**, and performs bit interleaving on the code bits of the LDPC code from the LDPC encoder **115**.

The group-wise interleaver **1021** performs group-wise interleaving on the LDPC code from the parity interleaver **23**, and supplies the LDPC code on which the group-wise interleaving has been performed to the block interleaver **1022**.

Here, when it is assumed that the block interleaving of the type B is performed, the group-wise interleaver **1021** rewrites the GW pattern for the block interleaving of the type B into the GW pattern for the block interleaving of the type A such that when the block interleaving of the type A is performed, the same block interleaving result as that when the block interleaving of the type B is performed is obtained.

Further, when it is assumed that the block interleaving of the type A is performed, the group-wise interleaver **1021** rewrites the GW pattern for the block interleaving of the type A into the GW pattern for the block interleaving of the type B such that when the block interleaving of the type B is performed, the same block interleaving result as that when the block interleaving of the type A is performed is obtained.

For example, the block interleaver **1022** symbolizes the LDPC code corresponding to one code to a m-bit symbol which is a unit of mapping by performing the block interleaving for demultiplexing the LDPC code from the group-wise interleaver **1021**, and supplies the symbol to the mapper **117** (

The block interleaver **1022** corresponds to the block interleaving of the type A or the type B, and can perform the block interleaving of the type A or the type B.

Block Interleaver **1022** Corresponding to Block Interleaving of Type A

Here, the block interleaving of the type A will be described. **1022** (

The block interleaver **1022** corresponding to the block interleaving of the type A includes a storage region called a part 1, and a storage region called to a part 2.

Both of the parts 1 and 2 are configured in such a manner that columns as storage regions which store one bit in the row (transverse) direction and store a predetermined number of bits in the column (longitudinal) direction are arranged in the row direction by the number C equal to the number of bits m of the symbol.

When a part column length of the part 1 which is the number of bits stored in the column direction by columns of the part 1 is represented as R1 and a part column length of columns of the part 2 is represented as R2, (R1+R2)×C is equal to the code length N (64,800 bits or 16,200 bits in the second embodiment) of the LDPC code to be subject to the interleaving.

Moreover, the part column length R1 is equal to a multiple of 360 bits which is the unit size P, and the part column length R2 is equal to a remainder obtained by dividing a column length R1+R2 which is the sum of the part column length R1 of the part 1 and the part column length R2 of the part 2 by 360 bits which is the unit size P.

Here, the column length R1+R2 is equal to a value obtained by dividing the code length N of the LDPC code to be subjected to the block interleaving by m which is the number of bits of the symbol.

For example, when the modulation scheme of 16-QAM is performed on the LDPC code having a length code N of 16,200 bits, since the number of bits m of the symbol is 4 bits, the column length R1+R2 is 4,050 (=16,200/4) bits.

Further, since the remainder obtained by dividing the column length R1+R2=4,050 by 360 bits which is the unit size P is 90, the part column length R2 of the part 2 is 90 bits.

The part column length R1 of the part 1 is R1+R2-R2=4,050−90=3,960 bits.

**1022** (

The block interleaver **1022** performs the block interleaving of the type A by writing and reading the LDPC code in and from the parts 1 and 2.

That is, as shown in

When the writing of the code bits in the bottommost region of the rightmost column (C-th column) of the columns of the part 1 is ended, the writing of the remaining code bits in the columns of the part 2 from the top to the bottom (in the column direction) is performed in the columns from the left to the right.

Subsequently, when the writing of the code bits in the bottommost region of the rightmost column (C-th column) of the columns of the part 2 is ended, the code bits are read from the first rows of all of C number of columns of the part 1 in the row direction for every C=m bits, as shown in

The reading of the code bits from all of C number of columns of the part 1 is sequentially performed in the lower rows, and when the reading from the R1 row which is the last row is ended, the code bits are read from the first rows of all of C number of columns of the part 2 in the row direction for every C=m bits.

The reading of the code bits from all of C number of columns of the part 2 is sequentially performed in the lower rows, and the reading is performed up to the R2 row which is the last row.

In this manner, the code bits read from the parts 1 and 2 for every m bits are supplied as a symbol to the mapper **117** (

Group-Wise Interleaving

**1021** of

In the group-wise interleaving, the LDPC code of one codeword is interleaved for every bit group according to a predetermined pattern (hereinafter, referred to as a GW pattern) by using 360 bits corresponding to one group obtained by dividing the LDPC code of one codeword from the leading code for every 360 bits equal to the unit size P into the bit groups.

When the unit size P is 360 bits, the LDPC code having the code length N of, for example, 1,800 bits is divided into 5 (=1,800/360) bit groups of bit groups 0, 1, 2, 3 and 4. For example, the LDPC code having the code length N of 16,200 bits is divided into 45 (=16,200/360) bit groups of bit groups 0, 1, . . . , and **44**, and the LDPC code having the code length N of 64,800 bits is divided into 180 (=64,800/360) bit groups of bit groups 0, 1, . . . , and 179.

Hereinafter, the (i+1)-th bit group from the leading bit group when the LDPC code of one codeword is divided into the bit groups is represented as a bit group i. In the following description, it is assumed that the GW pattern is represented as the arrangement of numbers representing the bit groups. For example, the GW pattern of 4, 2, 0, 3, 1 for the LDPC code having the code length N of 1,800 bits represents that the arrangement of bit groups 0, 1, 2, 3 and 4 is interleaved (rearranged) into the arrangement of bit groups 4, 2, 0, 3 and 1.

Specific Example of Block Interleaving of Type A

Next, the bit interleaving performed in the bit interleaver **116** including the block interleaver **1022** corresponding to the block interleaving of the type A will be described with reference to

_{g}=12 and the number of columns is N_{c}=4 as a specific example of the block interleaving of the type A. In

In the case 1 of the block interleaving of the type A, a column length N_{r1 }of the part 1 is floor(N_{g}/N_{c})×360=12/4×360=3×360 bits. Since a column length N_{r2 }of the part 2 is (N_{g}×360−N_{r1}×N_{c})/N_{c}=(12×360−3×360×4)/4=0 bits, only the storage region of the part 1 is used, and the storage region of the part 2 is not used. A floor function is a function obtained by rounding numbers after a decimal point.

In **23**, that is, an input of the group-wise interleaver **1021**, and a group-wise interleaver (GWI) output represents an output of the group-wise interleaver **1021**. That is, the group-wise interleaver **1021** interleaves the arrangement of bit groups 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12 into the arrangement of bit groups 4, 7, 9, 2, 12, 8, 10, 1, 5, 11, 3, and 6 according to the GW pattern of 4, 7, 9, 2, 12, 8, 10, 1, 5, 11, 3, 6.

The block interleaver **1022** performs the writing of the output from the group-wise interleaver **1021** in the columns of the part 1 from the top to the bottom (in the column direction) in the columns from the left to the right.

Thus, as shown in “block interleaver (BLI) write” of

Thereafter, the writing of the code bits in the bottommost region of the fourth column (rightmost column) of the columns of the part 1 is ended, as shown in “BLI read” of

In this manner, the code bits read from the part 1 for every m bits are supplied as a symbol to the mapper **117** (**117**, the LDPC code from the bit interleaver **116** is mapped to a signal point of 16 (2^{4}) signal points representing the symbol for every symbol.

_{g}=14 and the number of columns is N_{c}=4 as a specific example of the block interleaving of the type A. In

In the case 2 of the block interleaving of the type A, a column length N_{r1 }of the part 1 is floor(N_{g}/N_{c})×360=14/4×360=3×360 bits. Since a column length N_{r2 }of the part 2 is (N_{g}×360−N_{r1}×N_{c})/N_{c}=(14×360−3×360×4)/4=(2×360)/4=180 bits, the storage region of the part 2 is used in addition to the storage region of the part 1.

In **1021**. That is, the group-wise interleaver **1021** interleaves the arrangement of bit groups 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, and 14 into the arrangement of bit groups 4, 7, 13, 2, 12, 8, 10, 1, 14, 11, 3, 6, 9, and 5 according to the GW pattern of 4, 7, 13, 2, 12, 8, 10, 1, 14, 11, 3, 6, 9, 5.

The block interleaver **1022** performs the writing of the output from the group-wise interleaver **1021** in the columns of the part 1 from the top to the bottom (in the column direction) in the columns from the left to the right. When the writing of the code bits in the bottommost region of the rightmost column of the columns of the part 1 is ended, the writing of the remaining code bits in the columns of the part 2 from the top to the bottom (in the column direction) is performed in the columns from the left to the right.

Thus, as shown in “BLI write” of

In the part 2, the coding bits of the bit group 9-1 are written in the first column (left most column), the coding bits of the bit group 9-2 are written in the second column, the coding bits of the bit group 5-1 are written in the third column, and the coding bits of the bit group 5-2 are written in the fourth column (rightmost column).

Here, the bit group 9-1 and the bit group 9-2 are respectively 180 bits, and the bit group 9 is formed by these bit groups. The bit group 5-1 and the bit group 5-2 are respectively 180 bits, and the bit group 5 is formed by these bit groups.

Subsequently, when the writing of the cod bits in the bottommost region of the fourth column (rightmost column) of the columns of the part 2 is ended, the code bits are read from the first rows of all of four columns of the part 1 in the row direction for every C=m bits as shown in “BLI read” of

The writing of the code bits from all of four columns of the part 1 is sequentially performed in the lower rows, and when the reading from the last row is ended, the code bits are read from the first rows of all of four columns of the part 2 in the row direction for every C=m bits.

The reading of the code bits from all of four columns of the part 2 is sequentially performed in the lower rows, and is performed up to the last row.

In this manner, the code bits read from the parts 1 and 2 for every m bits are supplied as the symbol to the mapper **117** (**117**, the LDPC code from the bit interleaver **116** is mapped to a signal point of 16 (2^{4}) signal points representing the symbol for every symbol.

Block Interleaver **1022** Corresponding to Block Interleaving of Type B

Next, the block interleaving of the type B will be described. **1022** (

The block interleaver **1022** corresponding to the block interleaving of the type B includes a storage region called a part 1, and a storage region called a part 2.

The part 1 is configured in such a manner that columns as storage regions that store one bit in the row (transverse) direction and store a predetermined number of bits in the column (longitudinal) direction are arranged in the row direction by the number C equal to the number of bits m of the symbol. The part 2 is configured in such a manner that rows as storage regions that store one bit in the column (longitudinal) direction and store a predetermined number of bits are arranged in the row (transverse) direction in the row direction.

When a part column length which is the number of bits stored in the column direction by the columns of the part 1 is represented as R1 and a low length of the rows of the part 2 is represented as R2, R1×C+R2 is equal to the code length N (in the second embodiment, 64,800 bits or 16,200 bits) of the LDPC code to be subject to the block interleaving.

The part column length R1 is equal to a multiple of 360 bits which is the unit size P, and the row length R2 is equal to a value obtained by multiplying the remainder when the column length R1+R2/C which is the sum of the part column length R1 of the part 1 and a value obtained by dividing the row length R2 by C is divided by 360 bits which is the unit size P by C.

Here, the column length R1+R2/C is equal to a value obtained by dividing the code length N of the LDPC code to be subject to the block interleaving by the number of bits m of the symbol.

For example, when the 16-QAM modulation scheme is performed on the LDPC code having a code length N of 16,200 bits, since the number of bits m of the symbol is 4 bits, the column length R1+R2/C is 4,050 (=16,200/4) bits.

In addition, the remainder when the column length R1+R2/C=4,050 is divided by 360 bits which is the unit size P is 90, the row length R2 of the part 2 is 360(=90×4) bits.

The part column length R1 of the part 1 is R1+R2/C-R2/4=4,050−90=3,960 bits.

**1022** (

The block interleaver **1022** performs the block interleaving of the type B by writing and reading the LDPC code in and from the parts 1 and 2.

That is, as shown in

When the writing of the code bits in the bottommost region of the rightmost column (C-th column) of the columns of the part 1 is ended, the writing of the remaining code bits is performed in the rows of the part 2 from the left to the right (in the row direction).

Thereafter, when the writing of the code bits in the rightmost row of the rows of the part 2 is ended, the code bits are read from the first rows of all of C number of columns of the part 1 in the row direction for every C=m bits, as shown in

The reading of the code bits from all of C number of columns of the part 1 is sequentially performed in the lower rows, and when the reading from the R1 row which is the last row is ended, the code bits are read from the rows of the part 2 from the left to the right (in the row direction) for every C=m bits.

In this manner, the code bits read from the parts 1 and 2 for every m bits are supplied as the symbol to the mapper **117** (

Specific Example of Block Interleaving of Type B

Next, the bit interleaving performed in the bit interleaver **116** having the block interleaver **1022** corresponding to the block interleaving of the type B will be described with reference to

_{g}=12 and the number of columns is N_{c}=4 as a specific example of the block interleaving of the type B. In

In the case 1 of the block interleaving of the type B, a column length N_{r1 }of the part 1 is floor(N_{g}/N_{c})×360=12/4×360=3×360 bits. Since a row length N_{r2 }of the part 2 is N_{g×360}−N_{r1}×N_{c}=12×360−3×360×4=0 bits, only the storage region of the part 1 is used, and the storage region of the part 2 is not used.

In **1021**. That is, the group-wise interleaver **1021** interleaves the arrangement of bit groups 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12 into the arrangement of bit groups 4, 7, 9, 2, 12, 8, 10, 1, 5, 11, 3, and 6 according to the GW pattern of 4, 7, 9, 2, 12, 8, 10, 1, 5, 11, 3, 6.

The block interleaver **1022** iteratively performs the writing of the output from the group-wise interleaver **1021** in the columns of the part 1 from the left to the right (in the row direction) for every bit group.

Thus, as shown in “BLI write” of

Thereafter, when the writing of the code bits in the bottommost region of the fourth column (rightmost column) of the part 1 is ended, as shown in “BLI read” of

In this manner, the code bits read from the part 1 for every m bits are supplied as the symbol to the mapper **117** (**117**, the LDPC code from the bit interleaver **116** is mapped to a signal point of 16 (**2**^{4}) signal points representing the symbol for every symbol.

_{g}=14 and the number of columns is N_{c}=4 as a specific example of the block interleaving of the type B. In

In the case 2 of the block interleaving of the type B, a column length N_{r1 }of the part 1 is floor(N_{g}/N_{c})×360=14/4×360=3×360 bits. Since a row length N_{r2 }of the part 2 is N_{g×360}−N_{r1}×N_{c}=14×360−3×360×4=2×360 bits, the storage region of the part 2 is used in addition to the storage region of the part 1.

In **1021**. That is, the group-wise interleaver **1021** interleaves the arrangement of bit groups 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, and 14 into the arrangement of bit groups 4, 7, 13, 2, 12, 8, 10, 1, 14, 11, 3, 6, 9, and 5 according to the GW pattern of 4, 7, 13, 2, 12, 8, 10, 1, 14, 11, 3, 6, 9, 5.

The block interleaver **1022** iteratively performs the writing of the output from the group-wise interleaver **1021** in the columns of the part 1 from the left to the right (in the row direction) for every bit group. When the writing of the code bits in the bottommost region of the rightmost column of the columns of the part 1 is ended, the writing of the remaining code bits is performed on the rows of the part 2 from the left to the right (in the row direction).

Thus, as shown in “BLI write” of

Subsequently, when the writing of the code bits in the rightmost row of the part 2 is ended, the code bits are read from the first rows of all of four columns of the part 1 in the row direction for every C=m bits, as shown in “BLI read” of

The reading of the code bits from all of four columns of the part 1 is sequentially performed in the lower rows, and when the reading in the last row is ended, the code bits are read from the rows of the part 2 from the left to the right (in the row direction) for every C=m bits. Here, the code bits of the bit groups 9 and 5 written in the rows of the part 2 are read by 4 bits in sequence from the leading bit.

In this manner, the code bits read from the parts 1 and 2 for every m bits are supplied as the symbol to the mapper **117** (**117**, the LDPC code from the bit interleaver **116** is mapped to a signal point of 16 (**2**^{4}) signal points representing the symbol for every symbol.

Rewriting of GW Pattern Depending on Type of Block Interleaving

The group-wise interleaver **1021** has to prepare the GW pattern for the block interleaving of the type A and the GW pattern for the block interleaving of the type B depending on the type of the block interleaving performed in the block interleaver **1022** provided at the latter stage.

In the block interleaving of the type A and the block interleaving of the type B, since the writing method and a part of the reading method performed on the storage regions are different, it is necessary to provide two types of address generating circuits for each type. For this reason, it has been requested that the block interleaving of the type A and the block interleaving of the type B are realized by using a common address generating circuit as described above.

Thus, in the group-wise interleaver **1021**, it is possible to realize the common address generating circuit by converting the GW pattern for the block interleaving of the type B into the GW pattern for the block interleaving of the type A or the GW pattern for the block interleaving of the type A into the GW pattern for the block interleaving of the type B.

Here, the rewriting (converting) of the GW pattern performed in the group-wise interleaver **1021** will be described with reference to

_{g}=12 and the number of columns is N_{c}=4 as a specific conversion example of the GW pattern.

In **1022** corresponding to the block interleaving of the type A is illustrated on the left side in the drawing, and the block interleaver **1022** corresponding to the block interleaving of the type B is illustrated on the right side in the drawing.

Similarly to

In **1021**. As shown on the left side in the drawing, the group-wise interleaver **1021** interleaves the arrangement of bit groups 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12 into the number of bit groups 4, 12, 5, 7, 8, 11, 9, 10, 3, 2, 1, and 6, and outputs the interleaved arrangement to the block interleaver **1022** corresponding to the block interleaving of the type A.

That is, the group-wise interleaver **1021** interleaves the arrangement of bit groups 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12 into the arrangement of bit groups 4, 12, 5, 7, 8, 11, 9, 10, 3, 2, 1, and 6 according to the GW pattern of 4, 12, 5, 7, 8, 11, 9, 10, 3, 2, 1, 6 for the block interleaving of the type A.

The block interleaver **1022** corresponding to the block interleaving of the type A performs the writing of the output from the group-wise interleaver **1021** in the columns of the part 1 from the top to the bottom (in the column direction) in the columns from the left to the right.

Thus, as shown in “Type ABLI write” on the left side in the drawing, the code bits of the bit groups 4, 12, and 5 are written in the first column (leftmost column), the code bits of the bit groups 7, 8, and 11 are written in the second column, the code bits of the bit groups 9, 10, and 3 are written in the third column, and the code bits of the bit groups 2, 1, and 6 are written in the fourth column (rightmost column). When the writing of the code bits in the bottommost region of the fourth column of the columns of the part 1 is ended, the writing of the code bits is ended.

Meanwhile, as shown on the right side in the drawing, the group-wise interleaver **1021** interleaves the arrangement of bit groups 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12 into the arrangement of bit groups 4, 7, 9, 2, 12, 8, 10, 1, 5, 11, 3, and 6, and outputs the interleaved arrangement to the block interleaver **1022** corresponding to the block interleaving of the type B.

That is, the group-wise interleaver **1021** interleaves the arrangement of bit groups 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12 into the arrangement of bit groups 4, 7, 9, 2, 12, 8, 10, 1, 5, 11, 3, and 6 according to the GW pattern of 4, 7, 9, 2, 12, 8, 10, 1, 5, 11, 3, 6 for the block interleaving of the type B.

The block interleaver **1022** corresponding to the block interleaving of the type B iteratively performs the writing of the output from the group-wise interleaver **1021** in the columns of the part 1 from the left to the right (in the row direction) for every bit group.

Thus, as shown in “Type B BLI write” on the right side in the drawing, the code bits of the bit groups 4, 12, and 5 are written in the first column (leftmost column), the code bits of the bit groups 7, 8, and 11 are written in the second column, the code bits of the bit groups 9, 10, and 3 are written in the third column, and the code bits of the bit groups 2, 1, and 6 are written in the fourth column (rightmost column). When the writing of the code bits in the bottommost region of the fourth column of the columns of the part 1 is ended, the writing of the code bits is ended.

In this manner, the group-wise interleaver **1021** performs the interleaving according to the GW pattern depending on the type of the block interleaving, and thus, in the block interleaver **1022**, the writing results of the code bits written in the columns of the part 1 are the same in the block interleaving of the type A and the block interleaving of the type B.

That is, in both of the block interleaving of the type A and the block interleaving of the type B, the code bits of the bit groups 4, 12, and 5 are written in the first column, the code bits of the bit groups 7, 8, and 11 are written in the second column, the code bits of the bit groups 9, 10, and 3 are written in the third column, the code bits of the bit groups 2, 1, and 6 are written in the fourth column.

As stated above, if the writing results of the code bits written in the columns of the part 1 are the same, it is possible to use the write address generated in any one of the address generating circuit for the block interleaving of the type A and the address generating circuit for the block interleaving of the type B. That is, it is possible to realize the block interleaving of the type A and the block interleaving of the type B by using the common address generating circuit.

Thus, in the group-wise interleaver **1021** of

For example, in the group-wise interleaver **1021** of

In this case 1-1, when the block interleaving is performed in the block interleaver **1022**, the group-wise interleaver **1021** rewrites the GW pattern of 4, 7, 9, 2, 12, 8, 10, 1, 5, 11, 3, 6 for the block interleaving of the type B into the GW pattern of 4, 12, 5, 7, 8, 11, 9, 10, 3, 2, 1, 6 for the block interleaving of the type A. Thus, the block interleaving result of the type A performed by the group-wise interleaver **1021** is the same as the block interleaving result of the type B.

In the group-wise interleaver **1021** of

For example, in the group-wise interleaver **1021** of

In the case 1-2, when the block interleaving of the type B is performed in the block interleaver **1022**, the group-wise interleaver **1021** rewrites the GW pattern of 4, 12, 5, 7, 8, 11, 9, 10, 3, 2, 1, 6 for the block interleaving of the type A into the GW pattern of 4, 7, 9, 2, 12, 8, 10, 1, 5, 11, 3, 6 for the block interleaving of the type B. Thus, the block interleaving result of the type B performed by the group-wise interleaver **1021** is the same as the block interleaving result of the type A.

As mentioned above, it is possible to achieve the common address generating circuit by converting the GW pattern for the block interleaving of the type B into the GW pattern for the block interleaving of the type A or the GW pattern for the block interleaving of the type A into the GW pattern for the block interleaving of the type B by the group-wise interleaver **1021**.

Further, since the GW pattern is merely rewritten in the group-wise interleaver **1021** depending on the type of the block interleaving, performance degradation due to the converting of the GW pattern does not occur. For example, when it is assumed that the block interleaving of the type A is performed, since the completely same performance is obtained in the case where the block interleaving of the type A is performed according to the GW pattern for the block interleaving of the type A and the case where the block interleaving of the type B is performed according to the GW pattern for the block interleaving of the type B, the performance degradation due to the converting of the GW pattern does not occur.

Similarly to **1022** of **117** (

_{g}=14 and the number of columns is N_{c}=4 as a specific conversion example of the GW pattern.

Similarly to **1022** corresponding to the block interleaving of the type A is illustrated on the right side in the drawing, and the block interleaver **1022** corresponding to the block interleaving of the type B is illustrated on the right side in the drawing.

Similarly to

In **1021**. As shown on the left side in the drawing, the group-wise interleaver **1021** interleaves the arrangement of bit groups 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, and 14 into the arrangement of bit groups 4, 12, 14, 7, 8, 11, 13, 10, 3, 2, 1, 6, 9, and 5, and outputs the interleaved arrangement to the block interleaver **1022** corresponding to the block interleaving of the type A.

That is, the group-wise interleaver **1021** interleaves the arrangement of bit groups 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, and 14 into the arrangement of bit groups 4, 12, 14, 7, 8, 11, 13, 10, 3, 2, 1, 6, 9, and 5 according to the GW pattern of 4, 12, 14, 7, 8, 11, 13, 10, 3, 2, 1, 6, 9, 5 for the block interleaving of the type A.

The block interleaver **1022** corresponding to the block interleaving of the type A performs the writing of the output from the group-wise interleaver **1021** in the columns of the part 1 from the top to the bottom (in the column direction) in the columns from the left to the right. When the writing of the code bits in the bottommost region of the rightmost column of the columns of the part 1 is ended, the writing of the remaining code bits in the columns of the part 2 from the top to the bottom (in the column direction) is performed in the columns from the left to the right.

Thus, as shown in “Type A BLI write” on the left side in the drawing, the code bits of the bit groups 4, 12, and 14 are written in the first column (leftmost column), the code bits of the bit groups 7, 8, and 11 are written in the second column, the code bits of the bit groups 13, 10, and 3 are written in the third column, and the code bits of the bit groups 2, 1, and 6 are written in the fourth column (rightmost column).

In the part 2, the coding bits of the bit group 9-1 are written in the first column (leftmost column), the coding bits of the bit group 9-2 are written in the second column, the coding bits of the bit group 5-1 are written in the third column, and the coding bits of the bit group 5-2 are written in the fourth column (rightmost column).

Here, the bit group 9-1 and the bit group 9-2 are respectively 180 bits, and the bit group 9 is formed by these groups. Further, the bit group 5-1 and the bit group 5-2 are respectively 180 bits, and the bit group 5 is formed by these groups. When the writing of the code bits in the bottommost region of the fourth column of the columns of the part 2 is ended, the writing of the code bits is ended.

Meanwhile, as shown on the right side in the drawing, the group-wise interleaver **1021** interleaves the arrangement of bit groups 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, and 14 into the arrangement of bit groups 4, 7, 13, 2, 12, 8, 10, 1, 14, 11, 3, 6, 9, and 5, and outputs the interleaved arrangement to the block interleaver **1022** corresponding to the block interleaving of the type B.

That is, the group-wise interleaver **1021** interleaves the arrangement of bit groups 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, and 14 into the arrangement of bit groups 4, 7, 13, 2, 12, 8, 10, 1, 14, 11, 3, 6, 9, and 5 according to the GW pattern of 4, 7, 13, 2, 12, 8, 10, 1, 14, 11, 3, 6, 9, 5 for the block interleaving of the type B.

The block interleaver **1022** corresponding to the block interleaving of the type B iteratively performs the writing of the output from the group-wise interleaver **1021** in the columns of the part 1 from the left to the right (in the row direction) for every bit group. When the writing of the code bits in the bottommost region of the rightmost column of the columns of the part 1 is ended, the writing of the remaining code bits in the rows of the part 2 from the left to the right (in the row direction) is performed.

Thus, as shown in “Type B BLI write” on the right side in the drawing, the code bits of the bit groups 4, 12, and 14 are written in the first column (leftmost column), the code bits of the bit groups 7, 8, and 11 are written in the second column, the code bits of the bit groups 13, 10, and 3 are written in the third column, and the code bits of the bit groups 2, 1, and 6 are written in the fourth column (rightmost column). The code bits of the bit groups 9, and 5 are written in the rows of the part 2. When the writing of the code bits in the rightmost row of the rows of the part 2 is ended, the writing of the code bits is ended.

In this manner, the group-wise interleaver **1021** performs the interleaving according to the GW pattern depending on the type of the block interleaving, and thus, the writing results of the code bits written in the columns of the part 1 are the same in the block interleaving of the type A and the block interleaving of the type B in the block interleaver **1022**.

That is, in both of the block interleaving of the type A and the block interleaving of the type B, the code bits of the bit groups 4, 12, and 14 are written in the first column, the code bits of the bit groups 7, 8, and 11 are written in the second column, the code bits of the bit groups 13, 10, and 3 are written in the third column, and the code bits of the bit groups 2, 1, and 6 are written in the fourth column.

Similarly to

Thus, in the group-wise interleaver **1021** of

For example, in the group-wise interleaver **1021** of

In the case 2-1, when the block interleaving of the type A is performed in the block interleaver **1022**, the group-wise interleaver **1021** rewrites the GW pattern of 4, 7, 13, 2, 12, 8, 10, 1, 14, 11, 3, 6, 9, 5 for the block interleaving of the type B into the GW pattern of 4, 12, 14, 7, 8, 11, 13, 10, 3, 2, 1, 6, 9, 5 for the block interleaving of the type A. Thus, the block interleaving result of the type A performed by the group-wise interleaver **1021** is the same as the block interleaving result of the type B.

In the group-wise interleaver **1021** of

For example, in the group-wise interleaver **1021** of

In this case 2-2, when the block interleaving of the type B is performed in the block interleaver **1022**, the group-wise interleaver **1021** rewrites the GW pattern of 4, 12, 14, 7, 8, 11, 13, 10, 3, 2, 1, 6, 9, 5 for the block interleaving of the type A into the GW pattern of 4, 7, 13, 2, 12, 8, 10, 1, 14, 11, 3, 6, 9, 5 for the block interleaving of the type B. Thus, the block interleaving result of the type B performed by the group-wise interleaver **1021** is the same as the block interleaving result of the type A.

In this manner, it is possible to realize the common address generating circuit of the columns of the part 1 by converting the GW pattern for the block interleaving of the type B into the GW pattern for the block interleaving of the type A or the GW pattern for the block interleaving of the type A into the GW pattern for the block interleaving of the type B by the group-wise interleaver **1021**.

Moreover, since the GW pattern is merely rewritten depending on the type of the block interleaving in the group-wise interleaver **1021**, performance degradation due to the GW pattern does not occur. For example, when it is assumed that the block interleaving of the type B is performed, since the completely same performance is obtained in the case where the block interleaving of the type B is performed according to the GW pattern for the block interleaving of the type B and the case where the block interleaving of the type A is performed according to the GW pattern for the block interleaving of the rewritten type A, the performance degradation due to the converting of the GW pattern does not occur.

Here, since the write addresses of the code bits are different in the block interleaving of the type A and the block interleaving of the type B for (the storage region) of the part 2, it is necessary to provide the address generating circuit for each type.

Similarly to **1022** of **117** (

Example of GW Pattern Set to MODCOD (LDPC Code of 64 k Bits)

In

In

In

In

In

In

In

As stated above, the GW pattern for the block interleaving of the type A or the GW pattern for the block interleaving of the type B are set for each MODCOD which is the combination of the LDPC code of 64 k bits and the modulation scheme depending on the assumed type.

As described above, in the group-wise interleaver **1021**, when it is assumed that the block interleaving of the type B is performed, the GW pattern for the block interleaving of the type B is rewritten into the GW pattern for the block interleaving of the type A such that the block interleaving result obtained when the block interleaving of the type A is performed is the same as the block interleaving result obtained when the block interleaving of the type B is performed.

Further, in the group-wise interleaver **1021**, when it is assumed that the block interleaving of the type A is performed, the GW pattern for the block interleaving of the type A is rewritten into the GW pattern for the block interleaving of the type B such that the block interleaving result obtained when the block interleaving of the type B is performed is the same as the block interleaving result obtained when the block interleaving of the type A is performed.

Hereinafter, as a specific example of the GW pattern set to each MODCOD shown in

In each MODCOD, when the GW pattern for the block interleaving of the type A is set as the original GW pattern (A), the GW pattern for the block interleaving of the type B is set as the converted GW pattern (B). By contrast, when the GW pattern for the block interleaving of the type B is set as the original GW pattern (B), the GW pattern for the block interleaving of the type A is set as the converted GW pattern (A).

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (B) of

According to the converted GW pattern (A) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (B) of

According to the converted GW pattern (A) of

According to the original GW pattern (B) of

According to the converted GW pattern (A) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

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According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

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According to the converted GW pattern (B) of

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According to the converted GW pattern (B) of

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According to the converted GW pattern (B) of

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According to the converted GW pattern (B) of

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According to the converted GW pattern (B) of

According to the original GW pattern (B) of

According to the converted GW pattern (A) of

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According to the converted GW pattern (B) of

According to the original GW pattern (B) of

According to the converted GW pattern (A) of

According to the original GW pattern (B) of

According to the converted GW pattern (A) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (B) of

According to the converted GW pattern (A) of

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According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (B) of

According to the converted GW pattern (A) of

According to the original GW pattern (B) of

According to the converted GW pattern (A) of

According to the original GW pattern (B) of

According to the converted GW pattern (A) of

According to the original GW pattern (B) of

According to the converted GW pattern (A) of

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According to the converted GW pattern (B) of

According to the original GW pattern (B) of

According to the converted GW pattern (A) of

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According to the converted GW pattern (A) of

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According to the converted GW pattern (B) of

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According to the converted GW pattern (A) of

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According to the converted GW pattern (B) of

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According to the converted GW pattern (A) of

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According to the converted GW pattern (B) of

According to the original GW pattern (B) of

According to the converted GW pattern (A) of

According to the original GW pattern (B) of

According to the converted GW pattern (A) of

According to the original GW pattern (B) of

According to the converted GW pattern (A) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

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According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

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According to the original GW pattern (A) of

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According to the original GW pattern (A) of

According to the converted GW pattern (B) of

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According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

Example of GW Pattern Set to MODCOD (LDPC Code of 16 k Bits)

Similarly to

In

In

In

In

As stated above, the GW pattern for the block interleaving of the type A or the GW pattern for the block interleaving of the type B is set to each MODCOD which is the combination of the modulation scheme and the LDPC code of 16 k bits depending on the assumed type A.

As mentioned above, when it is assumed that the block interleaving of the type B is performed in the group-wise interleaver **1021**, the GW pattern for the block interleaving of the type B is rewritten into the GW pattern for the block interleaving of the type A such that a block interleaving effect obtained when the block interleaving of the type A is performed is the same as a block interleaving effect obtained when the block interleaving of the type B is performed.

When it is assumed that the block interleaving of the type A is performed in the group-wise interleaver **1021**, the GW pattern for the block interleaving of the type A is rewritten into the GW pattern for the block interleaving of the type B such that a block interleaving effect obtained when the block interleaving of the type B is performed is the same as a block interleaving effect obtained when the block interleaving of the type A is performed.

As a specific example of the GW pattern set to each MODCOD shown in

In each MODCOD, when the GW pattern for the block interleaving of the type A is set as an original GW pattern (A), the GW pattern for the block interleaving of the type B is set as a converted GW pattern (B). By contrast, when the GW pattern for the block interleaving of the type B is set as an original GW pattern (B), the GW pattern for the block interleaving of the type A is set as a converted GW pattern (A).

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (B) of

According to the converted GW pattern (A) of

According to the original GW pattern (B) of

According to the converted GW pattern (A) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

According to the original GW pattern (B) of

According to the converted GW pattern (A) of

According to the original GW pattern (A) of

According to the converted GW pattern (B) of

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Relationship between Original GW Pattern and Converted GW Pattern Next, the relationship between the original GW pattern and the converted GW pattern for each code length N of 64 k bits or 16 k bits for each modulation scheme will be described.

Here, the relationship between the GW pattern (A) and the GW pattern (B) when the GW pattern for the block interleaving of the type A (hereinafter, described as a GW pattern (A)) is set as the original GW pattern (A) and the GW pattern for the block interleaving of the type B (hereinafter, described as a GW pattern (B)) is set as the converted GW pattern (B) will be described.

For the sake of convenience in the description, only a case where the GW pattern (A) is set as the original GW pattern (A) and the GW pattern (B) is set as the converted GW pattern (B) will be described below, but it is possible to obtained the same relationship in a case where the GW pattern (B) is set as the original GW pattern (B) and the GW pattern (A) is set as the converted GW pattern (A).

In

According to the GW pattern (B) of

In **177**, **178**, **179** may be rewritten into the GW pattern (B).

According to the GW pattern (B) of

In

According to the GW pattern (B) of

In

According to the GW pattern (B) of

In **177**, **178**, **179** may be rewritten into the GW pattern (B).

According to the GW pattern (B) of

In **177**, **178**, **179** may be rewritten into the GW pattern (B).

According to the GW pattern (B) of

In

According to the GW pattern (B) of

In

According to the GW pattern (B) of

In

According to the GW pattern (B) of

In

According to the GW pattern (B) of

Configuration Example of Bit Deinterleaver **165**

**165** of

The bit deinterleaver **165** includes a block deinterleaver **1031** and a group-wise deinterleaver **1032**, and performs (bit) deinterleaving on the symbol bits of the symbol which is the data from the demapper **164** (

That is, the block deinterleaver **1031** performs the block deinterleaving (reverse processing of the block interleaving) corresponding to the block interleaving performed by the block interleaver **1022** of **164** as a target, that is, the block deinterleaving that returns the positions of (the likelihood of) the code bits of the LDPC code rearranged through the block interleaving to the original positions, and supplies an LDPC code obtained as the result to the group-wise deinterleaver **1032**.

The block deinterleaver **1031** corresponds to the block deinterleaving of the type A or the type B, and can perform the block deinterleaving of the type A or the type B.

The group-wise deinterleaver **1032** performs the group-wise deinterleaving (reverse processing of the group-wise interleaving) corresponding to the group-wise interleaving performed by the group-wise interleaver **1021** of **1031** as a target, that is, the group-wise deinterleaving that returns the arrangement of the code bits to the original arrangement by, for example, rearranging the code bits of the LDPC code in which the arrangement has been changed for every bit group through the group-wise interleaving for every bit group.

Here, when it is assumed that the block deinterleaving of the type A is performed, the group-wise deinterleaver **1032** rewrites the GW pattern for the block interleaving of the type A into the GW pattern for the block deinterleaving of the type B when the block deinterleaving of the type B is performed. That is, in this case, in the group-wise deinterleaver **1032**, the original GW pattern (A) is rewritten into the converted GW pattern (B).

When it is assumed that the block deinterleaving of the type B is performed, the group-wise deinterleaver **1032** rewrites the GW pattern for the block deinterleaving of the type B into the GW pattern for the block deinterleaving of the type A when the block deinterleaving of the type A is performed. That is, in this case, in the group-wise deinterleaver **1032**, the original GW pattern (B) is rewritten into the converted GW pattern (A).

When the parity interleaving, the group-wise interleaving and the block interleaving are performed on the LDPC code supplied to the bit deinterleaver **165** from the demapper **164**, the bit deinterleaver **165** can perform all of the parity deinterleaving (reverse processing of the parity interleaving, that is, the parity deinterleaving that returns the code bits of the LDPC code in which the arrangement has been changed through the parity interleaving to the original arrangement) corresponding to the parity interleaving, the block deinterleaving corresponding to the block interleaving, and the group-wise deinterleaving corresponding to the group-wise interleaving.

However, in the bit deinterleaver **165** of **1031** that performs the block deinterleaving corresponding to the block interleaving, and the group-wise deinterleaver **1032** that performs the group-wise deinterleaving corresponding to the group-wise interleaving are provided, but the block that performs the parity deinterleaving corresponding to the parity interleaving is not provided, and the parity deinterleaving is not performed.

Accordingly, the LDPC code on which the block deinterleaving and the group-wise deinterleaving have been performed and the parity deinterleaving has not been performed is supplied to the LDPC decoder **166** from (the group-wise deinterleaver **1032** of) the bit deinterleaver **165**.

The LDPC decoder **166** performs the LDPC decoding on the LDPC code from the bit deinterleaver **165** by using the transformation check matrix obtained by performing at least the column permutation corresponding to the parity interleaving on the parity check matrix H of the DVB method using the LDPC encoding by the LDPC encoder **115** of

Configuration Example of Block Deinterleaver **1031** Corresponding to Block Deinterleaving of Type A

**1031** of

The block deinterleaver **1031** corresponding to the block deinterleaving of the type A has the same configuration as that of the block interleaver **1022** corresponding to the block interleaving of the type A described in

Accordingly, the block deinterleaver **1031** includes a storage region called a part 1, and a storage region called a part 2, and both of the parts 1 and 2 are configured in such a manner that columns as storage regions which store one bit in the row direction and store a predetermined number of bits in the column direction are arranged by the number C equal to the number of bits m of the symbol.

The block deinterleaver **1031** performs the block deinterleaving of the type A by writing and reading the LDPC code in and from the parts 1 and 2.

In the block deinterleaving of the type A, the writing of the LDPC code (as the symbol) is performed in reading order of the LDPC code performed by the block interleaver **1022** of

Further, in the block deinterleaving of the type A, the reading of the LDPC code is performed in writing order of the LDPC code performed by the block interleaver **1022** of FIG. **218**.

That is, in the block interleaving of the type A by the block interleaver **1022** of **1031** of

Configuration Example of Block Deinterleaver **1031** Corresponding to Block Deinterleaving of Type B

**1031** of

The block deinterleaver **1031** corresponding to the block deinterleaving of the type B has the same configuration as that of the block interleaver **1022** corresponding to the block interleaving of the type B described in

Accordingly, the block deinterleaver **1031** includes a storage region called a part 1, and a storage region called a part 2.

The part 1 is configured in such a manner that columns as storage regions which store one bit in the row direction and store a predetermined number of bits in the column direction are arranged in the row direction by the number C equal to the number of bits m of the symbol. The part 2 is configured in such a manner that rows as storage regions which store one bit in the column direction and store a predetermined number of bits in the row direction.

The block deinterleaver **1031** performs the block deinterleaving of the type B by writing and reading the LDPC code in and from the parts 1 and 2.

However, in the block deinterleaving of the type B, the writing of the LDPC code (as the symbol) is performed in reading order of the LDPC code performed by the block interleaver **1022** of

Moreover, in the block deinterleaving of the type B, the reading of the LDPC code is performed in writing order of the LDPC code performed by the block interleaver **1022** of

That is, in the block interleaving of the type B by the block interleaver **1022** of **1031** of

Another Configuration Example of Bit Deinterleaver **165**

**165** of

In the drawing, the parts corresponding to those in

That is, the bit deinterleaver **165** of **1011** is newly provided.

In **165** includes the block deinterleaver **1031**, the group-wise deinterleaver **1032**, and the parity deinterleaver **1011**, and performs the bit deinterleaving on the code bits of the LDPC code from the demapper **164**.

That is, the block deinterleaver **1031** performs the block deinterleaving (reverse processing of the block interleaving) corresponding to the block interleaving performed by the block interleaver **1022** of the transmission apparatus **11** on the LDP code from the demapper **164** as a target, that is, the block deinterleaving that returns the positions of the code bits replaced through the block interleaving to the original positions, and supplies an LDPC code obtained as the result to the group-wise deinterleaver **1032**.

The group-wise deinterleaver **1032** performs the group-wise deinterleaving corresponding to the group-wise interleaving as the rearranging process performed by the group-wise interleaver **1021** of the transmission apparatus **11** on the LDPC code from the block deinterleaver **1031** as a target.

The LDPC code obtained as the result of the group-wise deinterleaving is supplied to the parity deinterleaver **1011** from the group-wise deinterleaver **1032**.

The parity deinterleaving performed by the parity deinterleaver **1011** and the LDPC decoding on the LDPC code performed by the LDPC decoder **166** are the same as those in

For the sake of convenience in the description, although it has been described in **1031** that performs the block deinterleaving, the group-wise deinterleaver **1032** that performs the group-wise deinterleaving and the parity deinterleaver **1011** that performs the parity deinterleaving are individually provided, two or more of the block deinterleaver **1031**, the group-wise deinterleaver **1032** and the parity deinterleaver **1011** may be integrally configured similarly to the parity interleaver **23**, the group-wise interleaver **1021** and the block interleaver **1022** of the transmission apparatus **11**.

Configuration Example of Reception System

**12** can be applied.

In **1101**, a transmission channel decoding unit **1102**, and an information source decoding unit **1103**.

The acquisition unit **1101** obtains a signal including the LDPC code obtained by performing at least the LDPC encoding on the LDPC target data such as image data or voice data of a program through a non-illustrated transmission channel (communication channel) such as terrestrial digital broadcasting, satellite digital broadcasting, a CATV network, or other networks other than the Internet, and supplies the obtained signal to the transmission channel decoding unit **1102**.

Here, when the signal obtained by the acquisition unit **1101** is broadcasted from, for example, a broadcasting station through the terrestrial digital broadcasting, the satellite digital broadcasting, or the cable television (CATV) network, the acquisition unit **1101** is configured as a tuner or a set-top box (STB). When the signal obtained by the acquisition unit **1101** is transmitted using, for example, multicast such as an internet protocol television (IPTV) from a web server, the acquisition unit **1101** is configured as a network interface (I/F) such as a network interface card (NIC).

The transmission channel decoding unit **1102** corresponds to the reception apparatus **12**. The transmission channel decoding unit **1102** performs transmission channel decoding including at least a process of correcting an error occurring in a transmission channel on the signal obtained by the acquisition unit **1101** through the transmission channel, and supplies a signal obtained as the result to the information source decoding unit **1103**.

That is, the signal obtained by the acquisition unit **1101** through the transmission channel is a signal obtained by performing at least an error correcting encoding for correcting the error in the transmission channel, and the transmission channel decoding unit **1102** performs the transmission channel decoding such as an error correcting process on the signal.

Here, examples of the error correcting encoding includes LDPC encoding and BCH encoding. Here, as the error correcting encoding, at least the LDPC encoding is performed.

In addition, the transmission channel decoding may include decoding on a modulation signal.

The information source decoding unit **1103** performs information source decoding including at least a process of decompressing compressed information to original information on the signal on which the transmission channel decoding has been performed.

That is, in order to reduce the amount of data such as image or voice as information, compression encoding that compresses the information may be performed on the signal obtained by the acquisition unit **1101** through the transmission channel, and in this case, the information source decoding unit **1103** performs the information source decoding such as the process (decompression process) of decompressing the compressed information to the original information on the signal on which the transmission channel decoding has been performed.

When the compression encoding has not been performed on the signal obtained by the acquisition unit **1101** through the transmission channel, the information source decoding unit **1103** does not perform the process of decompressing the compressed information to the original information.

Here, as the decompression process, there is, for example, a MPEG decoding. The transmission channel decoding may include descrambling in addition to the decompression process.

In the reception system having the aforementioned configuration, the compression encoding such as MPEG encoding is performed on data such as image or voice in the acquisition unit **1101**, and the signal on which the error correcting encoding such as LDPC encoding has been performed is obtained through the transmission channel and is supplied to the transmission channel decoding unit **1102**.

In the transmission channel decoding unit **1102**, for example, the same process as that performed by the reception apparatus **12** is performed on the signal from the acquisition unit **1101**, as the transmission channel decoding, and a signal obtained as the result is supplied to the information source decoding unit **1103**.

In the information source decoding unit **1103**, the information source decoding such as MPEG decoding is performed on the signal from the transmission channel decoding unit **1102**, and an image or a voice obtained as the result is output.

For example, the reception system of

The acquisition unit **1101**, the transmission channel decoding unit **1102** and the information source decoding unit **1103** may be independently configured as one device (hardware (integrated circuit (IC)) or software).

With regard to the acquisition unit **1101**, the transmission channel decoding unit **1102** and the information source decoding unit **1103**, a set of the acquisition unit **1101** and the transmission channel decoding unit **1102**, a set of the transmission channel decoding unit **1102** and the information source decoding unit **1103**, and a set of the acquisition unit **1101**, the transmission channel decoding unit **1102** and the information source decoding unit **1103** may be independently configured as one device.

**12** can be applied.

In the drawing, the parts corresponding to those in

The reception system of **1101**, the transmission channel decoding unit **1102** and the information source decoding unit **1103** are provided, and has a difference from the reception system of **1111** is newly provided.

The output unit **1111** is, for example, a display unit that displays an image or a speaker that outputs a voice, and outputs an image or a voice as the signal output from the information source decoding unit **1103**. That is, the output unit **1111** displays the image or outputs the voice.

For example, the reception system of

When the compression encoding has not been performed on the signal obtained in the acquisition unit **1101**, the signal output from the transmission channel decoding unit **1102** is supplied to the output unit **1111**.

**12** can be applied.

In the drawing, the parts corresponding to those in

The reception system of **1101** and the transmission channel decoding unit **1102** are provided.

However, the reception system of **1103** is not provided and a recording unit **1121** is newly provided.

The recording unit **1121** records (stores) the signal (for example, TS packet of TS of MPEC) output from the transmission channel decoding unit **1102** in a recording (storing) medium such as an optical disc, a hard disc (magnetic disc), or a flash memory.

The reception system of

In **1103**, and in the information source decoding unit **1103**, the signal on which the information source decoding has been performed, that is, the image or the voice obtained through decoding can be recorded in the recording unit **1121**.

Embodiment of Computer

Next, a series of processes described above may be performed by hardware or may be performed by software. When the series of processes is performed by software, programs constituting the software are installed in a general-purpose computer.

Here,

The programs may be previously recorded in a hard disc **705** or a ROM **703** as a recording medium embedded in the computer.

Alternatively, the programs may be temporarily or permanently stored (recorded) in a removable recording medium **711** such as a flexible disc, a compact disc read-only memory (CD-ROM), a magneto-optical (MO) disc, a digital versatile disc (DVD), a magnetic disc, or a semiconductor memory. The removable recording medium **711** may be provided as so-called package software.

The programs may be installed in the computer from the removable recording medium **711**, may be wirelessly transmitted to the computer from a download site through an artificial satellite for digital satellite broadcasting, or may be transmitted to the computer through a network such as a local area network (LAN) or the Internet in a wired manner. In the computer, the programs transmitted in this manner may be received by a communication unit **708**, and may be installed in the hard disc **705** embedded therein.

The computer includes a central processing unit (CPU) **702**. An input and output interface **710** is connected to the CPU **702** through a bus **701**, and when an instruction is input by an operation input of an input unit **707** including a keyboard, a mouse or a microphone by a user through the input and output interface **710**, the CPU **702** executes the programs stored in the read-only memory (ROM) **703** in response to the instruction. Alternatively, the CPU **702** downloads the programs stored in the hard disc **705**, the programs which is transmitted from the satellite or the network, received by the communication unit **708** and installed in the hard disc **705**, and the programs which is read from the removable recording medium **711** provided in a drive **709** and is installed in the hard disc **705** in a random-access memory (RAM) **704**, and executes the downloaded programs. Thus, the CPU **702** performs the process according to the flowchart described above or the process performed by the configuration of the block diagram described above. The CPU **702** outputs the processed result from an output unit **706** including a liquid crystal display (LCD) or a speaker through, for example, the input and output interface **710** when necessary, transmits the processed result from the communication unit **708**, or records the processed result in the hard disc **705**.

Here, in the present specification, processing steps that describe the programs for causing the computer to perform various processes are not necessarily performed in a sequence of time in the order described as the flowchart, and may include processes which are executed in parallel or individual manner (for example, a parallel process or a process by objects).

Furthermore, the programs may be processed by one computer, or may be processed in a distributed manner by a plurality of computers. Further, the programs may be executed by being transmitted to a remote computer.

The embodiments of the present technology are not limited to the embodiments described above, and can be variously changed within the scope without departing from the gist of the present technology.

That is, for example, in (the parity check matrix initial value table of) the new LDPC encoding described above, the communication channel **13** (

The GW pattern described above may be applied to encoding other than the new LDPC encoding. Moreover, a modulation scheme to which the GW pattern described above is applied is not limited to QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM or 4096-QAM.

The effects described in the present specification are merely examples, and are not limited. Other effects may be obtained.

## Claims

1. A transmitting apparatus comprising:

- circuitry configured to

- perform group-wise interleaving which interleaves an LDPC code word to obtain a group-wise interleaved LDPC code word;

- perform block interleaving which interleaves the group-wise interleaved LDPC code word to obtain a block interleaved and group-wise interleaved LDPC code word in such a manner that the group-wise interleaved LDPC code word obtained by performing the group-wise interleaving is written in m number of columns as storage regions arranged in a row direction, m bits are obtained by respectively reading the LDPC code word from m number of columns bit by bit,

- perform mapping the block interleaved and group-wise interleaved LDPC code word to any one of 2m number of signal points defined by a modulation scheme; and

- perform transmitting a digital broadcast signal including the mapped block interleaved and group-wise interleaved LDPC code word obtained by performing the group-wise interleaving, performing the block interleaving, and performing the mapping,

- wherein a type of the block interleaving includes a type A in which writing of the group-wise interleaved LDPC code word obtained by performing the group-wise interleaving in a column direction of the columns is iteratively performed on m number of columns, and a type B in which the writing of the group-wise interleaved LDPC code word obtained by performing the group-wise interleaving in the row direction of m number of columns for every bit group is iteratively performed,

- wherein a MODCOD which is a combination of the LDPC code word and the modulation scheme includes a MODCOD-A which is a MODCOD based on the block interleaving of the type A, and a MODCOD-B which is a MODCOD based on the block interleaving of the type B,

- wherein when the block interleaving of the type A is performed on an LDPC code word of the MODCOD-B, the circuitry performs the group-wise interleaving on the LDPC code word of the MODCOD-B such that a same block interleaving result as a block interleaving result obtained when the block interleaving of the type B is performed is obtained, and

- when the block interleaving of the type B is performed on an LDPC code word of the MODCOD-A, the circuitry performs the group-wise interleaving on the LDPC code word of the MODCOD-A such that a same block interleaving result as a block interleaving result obtained when the block interleaving of the type A is performed is obtained.

2. A transmitting method comprising:

- group-wise interleaving which interleaves an LDPC code word to obtain a group-wise interleaved LDPC code word;

- block interleaving which interleaves the group-wise interleaved LDPC code word to obtain a block interleaved and group-wise interleaved LDPC code word in such a manner that the group-wise interleaved LDPC code word obtained by performing the group-wise interleaving is written in m number of columns as storage regions arranged in a row direction, m bits are obtained by respectively reading the LDPC code word from m number of columns bit by bit,

- mapping the block interleaved and group-wise interleaved LDPC code word to any one of 2m number of signal points defined by a modulation scheme; and

- transmitting a digital broadcast signal including the mapped block interleaved and group-wise interleaved LDPC code word obtained by performing the group-wise interleaving, performing the block interleaving, and performing the mapping,

- wherein a type of the block interleaving includes a type A in which writing of the group-wise interleaved LDPC code word obtained by performing the group-wise interleaving in a column direction of the columns is iteratively performed on m number of columns, and a type B in which the writing of the group-wise interleaved LDPC code word obtained by performing the group-wise interleaving in the row direction of m number of columns for every bit group is iteratively performed,

- wherein a MODCOD which is a combination of the LDPC code word and the modulation scheme includes a MODCOD-A which is a MODCOD based on the block interleaving of the type A, and a MODCOD-B which is a MODCOD based on the block interleaving of the type B,

- wherein when the block interleaving of the type A is performed on an LDPC code word of the MODCOD-B, the group-wise interleaving is performed on the LDPC code word of the MODCOD-B such that a same block interleaving result as a block interleaving result obtained when the block interleaving of the type B is performed is obtained, and

- when the block interleaving of the type B is performed on the LDPC code word of the MODCOD-A, the group-wise interleaving is performed on the LDPC code word of the MODCOD-A such that a same block interleaving result as a block interleaving result obtained when the block interleaving of the type A is performed is obtained.

3. A receiving apparatus comprising:

- circuitry configured to

- perform block deinterleaving which generates, from m bits of a symbol obtained from a digital broadcast signal transmitted from a transmission apparatus, a group-wise interleaved LDPC code word obtained by performing group-wise interleaving; and

- perform group-wise deinterleaving which generates, from the group-wise interleaved LDPC code word obtained by performing the group-wise interleaving, an original LDPC code word,

- wherein the digital broadcast signal transmitted from the transmission apparatus is processed in the transmission apparatus by circuitry configured to perform group-wise interleaving which interleaves the original LDPC code word to obtain a group-wise interleaved LDPC code word, perform block interleaving which interleaves the group-wise interleaved LDPC code word to obtain a block interleaved and group-wise interleaved LDPC code word in such a manner that the group-wise interleaved LDPC code word obtained by performing the group-wise interleaving is written in m number of columns as storage regions arranged in a row direction, m bits are obtained by respectively reading the LDPC code word from m number of columns bit by bit, perform mapping the block interleaved and group-wise interleaved LDPC code word to any one of 2m number of signal points defined by a modulation scheme, and perform transmitting the digital broadcast signal including the mapped block interleaved and group-wise interleaved LDPC code word obtained by performing the group-wise interleaving, performing the block interleaving, and performing the mapping, wherein a type of the block interleaving includes a type A in which writing of the group-wise interleaved LDPC code word obtained by performing the group-wise interleaving in a column direction of the columns is iteratively performed on m number of columns, and a type B in which the writing of the group-wise interleaved LDPC code word obtained by performing the group-wise interleaving in the row direction of m number of columns for every bit group is iteratively performed, wherein a MODCOD which is a combination of the LDPC code word and the modulation scheme includes a MODCOD-A which is a MODCOD based on the block interleaving of the type A, and a MODCOD-B which is a MODCOD based on the block interleaving of the type B, wherein when the block interleaving of the type A is performed on an LDPC code word of the MODCOD-B, the circuitry of the transmission apparatus performs the group-wise interleaving on the LDPC code word of the MODCOD-B such that a same block interleaving result as a block interleaving result obtained when the block interleaving of the type B is performed is obtained, and when the block interleaving of the type B is performed on an LDPC code word of the MODCOD-A, the circuitry of the transmission apparatus performs the group-wise interleaving on the LDPC code word of the MODCOD-A such that a same block interleaving result as a block interleaving result obtained when the block interleaving of the type A is performed is obtained.

4. A receiving method for use by a receiving device comprising:

- block deinterleaving which generates, from m bits of a symbol obtained from a digital broadcast signal transmitted from a transmission apparatus, a group-wise interleaved LDPC code word obtained by performing group-wise interleaving; and

- group-wise deinterleaving which generates, from the group-wise interleaved LDPC code word obtained by performing the group-wise interleaving, an original LDPC code word,

- wherein the digital broadcast signal transmitted from the transmission apparatus is processed in the transmission apparatus by circuitry configured to perform group-wise interleaving which interleaves the original LDPC code word to obtain a group-wise interleaved LDPC code word, perform block interleaving which interleaves the group-wise interleaved LDPC code word to obtain a block interleaved and group-wise interleaved LDPC code word in such a manner that the group-wise interleaved LDPC code word obtained by performing the group-wise interleaving is written in m number of columns as storage regions arranged in a row direction, m bits are obtained by respectively reading the LDPC code word from m number of columns bit by bit, perform mapping the block interleaved and group-wise interleaved LDPC code word to any one of 2m number of signal points defined by a modulation scheme, and perform transmitting the digital broadcast signal including the mapped block interleaved and group-wise interleaved LDPC code word obtained by performing the group-wise interleaving, performing the block interleaving, and performing the mapping, wherein a type of the block interleaving includes a type A in which writing of the group-wise interleaved LDPC code word obtained by performing the group-wise interleaving in a column direction of the columns is iteratively performed on m number of columns, and a type B in which the writing of the group-wise interleaved LDPC code word obtained by performing the group-wise interleaving in the row direction of m number of columns for every bit group is iteratively performed, wherein a MODCOD which is a combination of the LDPC code word and the modulation scheme includes a MODCOD-A which is a MODCOD based on the block interleaving of the type A, and a MODCOD-B which is a MODCOD based on the block interleaving of the type B, wherein when the block interleaving of the type A is performed on an LDPC code word of the MODCOD-B, the circuitry of the transmission apparatus performs the group-wise interleaving on the LDPC code word of the MODCOD-B such that a same block interleaving result as a block interleaving result obtained when the block interleaving of the type B is performed is obtained, and when the block interleaving of the type B is performed on an LDPC code word of the MODCOD-A, the circuitry of the transmission apparatus performs the group-wise interleaving on the LDPC code word of the MODCOD-A such that a same block interleaving result as a block interleaving result obtained when the block interleaving of the type A is performed is obtained.

**Patent History**

**Publication number**: 20200059251

**Type:**Application

**Filed**: Oct 23, 2019

**Publication Date**: Feb 20, 2020

**Applicant**: SONY CORPORATION (Tokyo)

**Inventors**: Ryoji IKEGAYA (Kanagawa), Makiko YAMAMOTO (Tokyo), Lachlan MICHAEL (Saitama), Muhammad Nabil Sven LOGHIN (Tokyo), Yuji SHINOHARA (Kanagawa)

**Application Number**: 16/661,634

**Classifications**

**International Classification**: H03M 13/27 (20060101); H03M 13/25 (20060101); H03M 13/29 (20060101); H03M 13/11 (20060101); H03M 13/03 (20060101);