Attenuator De-Qing Loss Improvement and Phase Balance
The de-Qing loss and phase imbalance caused by the inherent capacitance of a switched resistance, such as a MOSFET with a resistor, can be reduced by using a shunting switch across the resistor that is in series with the resistor's switch. The shunting switch shorts across the resistor when the resistor's switch is open and in reference mode, thereby significantly reducing the resistance in series with the inherent capacitance of the open resistor's switch.
This application is a continuation of commonly owned and co-pending U.S. application Ser. No. 15/212,025, filed Jul. 15, 2016, entitled “Attenuator De-Qing Loss Improvement and Phase Balance”, the disclosure of which is incorporated herein by reference in its entirety.
The present application may be related to U.S. patent application Ser. No. 15/212,046, filed on Jul. 15, 2016, entitled “Hybrid Coupler with Phase and Attenuation Control” (Attorney Docket No. PER-178-PAP), now U.S. Pat. No. 10,211,801 issued Feb. 19, 2019, and assigned to the assignee of the present disclosure, the contents of which are hereby incorporated by reference in their entirety.
TECHNICAL FIELDVarious embodiments described herein relate generally to systems, methods, and apparatus for improving de-Qing loss and phase balance for attenuator circuits.
BACKGROUNDVarious devices can be switched between a reference mode and an attenuated mode by the use of a switched parallel resistance. For example, a Pi-pad attenuator can include transistors on the legs of the Pi-pad to turn on and off each of the legs from an “attenuation mode” (switched on) to a “reference mode” or “floating mode” (switched off). Ideally, with the transistor turned on the input signal only sees the parallel resistance at the node and with the transistor turned off the input signal only sees an open circuit at the node. However, transistors in the off state are not perfect open circuits: they have small internal conductance and capacitance. The capacitance, known as parasitic capacitance, is of particular concern for signals that contain high frequency components, as the frequency keeps on increasing capacitance starts to acts like a short circuit rather than an open circuit as desired. As it becomes more of a short circuit, any internal resistance/conductance is now seen by the RF signal. But most detrimental is the attenuating resistor that was intended to be left floating is now seen through the signal path and incurs loss to the system. The insertion loss caused by the parasitic capacitance in series with internal and external resistance (attenuating) increases as the frequency increases. This insertion loss can be known as “de-Qing” the circuit, as it lowers the Q (gain) value. Additionally, the parasitic capacitance with the parallel resistance degrades phase imbalance increasingly as the signal frequency increases. For lower frequencies, these losses might be within acceptable ranges, and so can be ignored for some designs; however, for high frequency circuits, the de-Qing and phase imbalance can be an issue.
SUMMARY OF THE INVENTIONAccording to a first aspect of the present disclosure, a circuit is disclosed, comprising: a resistive element connected to an input terminal; a primary switching element in series with the resistive element; and a shunting switching element placed across the resistive element such that it would short current around the resistive element; wherein the shunting switching element is configured to be closed when the primary switching element is open, and the shunting switching element is configured to be open when the primary switching element is closed.
According to a second aspect of the present disclosure, a method of reducing de-Qing loss for a circuit, said circuit comprising a resistive element connected to an input signal and a primary switching element in series with the resistive element and a shunting switching element across the resistive element, is disclosed, the method comprising: opening the shunting switching element when the primary switching element is closed; and closing the shunting switching element when the primary switching element is open.
According to a third aspect of the present disclosure, a polyphase filter circuit comprising: parallel filter elements comprising a resistor and a capacitor; a primary switch in series with the resistor and the capacitor; and a shunting switch in parallel with the resistor and the capacitor, configured to short across the combination of the resistor and the capacitor when the shunting switch is closed.
According to a fourth aspect of the present disclosure, a method of fabricating switchable attenuation circuit with deQuing loss reduction is disclosed, the method comprising: providing a resistive element parallel to a signal input terminal; providing a primary switching element in series with the resistive element; and providing a shunting switching element placed across the resistive element such that it would short current around the resistive element; configuring the circuit such that the shunting switching element is closed when the primary switching element is open, and the shunting switching element is open when the primary switching element is closed.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments of the present disclosure and, together with the description of example embodiments, serve to explain the principles and implementations of the disclosure.
Like reference numbers and designations in the various drawings indicate like elements.
DETAILED DESCRIPTION OF THE INVENTIONIn one embodiment, the switches (225, 230) are MOSFET transistors, and the gate width (w) of shunting switch (225) is less than the w of the primary switch (230). For example, the w of the shunting switch (225) can be 1/14 the w of the primary switch (230). In one embodiment, the switches (225, 230) have the same stack size. And this can be chosen to achieve the desired performance at a desired frequency.
The de-Qing loss reduction system can be applied to other attenuation circuits. Some, but not all, examples are provided herein. The system can also be applied to other circuits that switch resistances to achieve attenuation, filtering, or signal absorption and that would experience de-Qing at high frequencies. The application of the de-Qing loss reduction system works especially well in a CMOS integrated circuit, where the addition of a transistor is simplified.
For the non-shunted case in attenuation mode, the leg (1340-A) has a Zin (1300-ZA) is a function of the two equivalent resistances, the resistance of the primary switch in a closed state (1330-R) and the attenuating resistor (1320-R), as shown in
However, for the shunted resistance case, the phase shift caused by the transition between attenuation mode and reference mode can be greatly reduced. As shown in
The term “switch” herein includes any technology that has an electronically (or optically) controllable resistance which can toggle between an open (very high resistance) state to a closed (very low resistance) state in a very short period of time, which exhibits a capacitance in the open state. This function can be performed by a mechanical switch, a transistor (such as a MOSFET or MESFET), or a small mechanical switch (such as a microelectromechanical systems (MEMS) switch).
The term “MOSFET” technically refers to metal-oxide-semiconductors; another synonym for MOSFET is “MISFET”, for metal-insulator-semiconductor FET. However, “MOSFET” has become a common label for most types of insulated-gate FETs (“IGFETs”). Despite that, it is well known that the term “metal” in the names MOSFET and MISFET is now often a misnomer because the previously metal gate material is now often a layer of polysilicon (polycrystalline silicon). Similarly, the “oxide” in the name MOSFET can be a misnomer, as different dielectric materials are used with the aim of obtaining strong channels with smaller applied voltages. Accordingly, the term “MOSFET” as used herein is not to be read as literally limited to metal-oxide-semiconductors, but instead includes IGFETs in general.
As should be readily apparent to one of ordinary skill in the art, various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice and various embodiments of the invention may be implemented in any suitable IC technology (including but not limited to MOSFET and IGFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), GaAs pHEMT, and MESFET technologies. However, the inventive concepts described above are particularly useful with an SOI-based fabrication process (including SOS), and with fabrication processes having similar characteristics. Fabrication in CMOS on SOI or SOS enables low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (in excess of about 10 GHz, and particularly above about 20 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low by careful design.
Voltage levels may be adjusted or voltage and/or logic signal polarities reversed depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functional without significantly altering the functionality of the disclosed circuits.
A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, or parallel fashion. It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims.
Claims
1. (canceled)
2. An attenuator comprising:
- an attenuator leg comprising: a resistive element connected between an input or output of the attenuator and a ground node of the attenuator, the resistive element having a resistance; a primary switching element in series with the resistive element; and a shunting switching element in parallel with the resistive element; wherein the attenuator leg is configured to be operated in two primary states of a) the primary switching element open and the shunting switching element closed, or b) the primary switching element closed and the shunting switching element open; and wherein the attenuator leg is configured such that a phase shift of the attenuator between the two primary states is less than what a second phase shift of the attenuator is between the two states if there is no shunting switching element in the at least one attenuator leg.
3. The attenuator of claim 2, wherein the phase shift is at least 2.5 degrees less than the second phase shift over a portion of a frequency range.
4. The attenuator of claim 2, wherein the phase shift is less than half the second phase shift over a portion of a frequency range.
5. The attenuator of claim 2, wherein an insertion loss of the attenuator over the phase shift is at least 0.25 dB less than the insertion loss over the second phase shift.
6. The attenuator of claim 2, wherein the primary switching element and the shunting switching element are MOSFETs, each having a gate width.
7. The attenuator of claim 6, wherein the gate width of the primary switching element is at least four times larger than the gate width of the shunting switching element.
8. The attenuator of claim 2, wherein the attenuator is a pi pad attenuator, a T pad attenuator, an L pad attenuator, or an O pad attenuator.
Type: Application
Filed: Dec 4, 2019
Publication Date: Jun 11, 2020
Inventor: Vikas Sharma (Reading)
Application Number: 16/703,525