HIGH-VOLTAGE AND LOW-VOLTAGE DATA PATHS OF A HYBRID OUTPUT DRIVER

A hybrid output data path is provided that supports high-voltage signaling and low-voltage signaling. The high-voltage signaling is powered by a high-power supply voltage that is greater than a low-power supply voltage that powers the low-voltage signaling.

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Description
CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No. 62/794,327, filed Jan. 18, 2019, which is incorporated by reference herein,

TECHNICAL FIELD

This application relates to output drivers, and more particularly to a hybrid data path with high-voltage and low-voltage signaling to a hybrid output driver.

BACKGROUND

Input/output standards have varying power supply voltages depending upon the application. For example, various power supply voltages are used in the low-power double-data-rate (LPDDR) standards for the interface between mobile computers (e.g., smartphones and tablets) and synchronous dynamic random access memories. In the LPDDR3 standard, the nominal power supply voltage is 1.2V whereas it is 0.6 V for the LPDDR4X standard. In general, the power supply voltage is lowered for more modern standards to save power. There are bus I/O standards relatively-low power supply voltages and those with relatively-high power supply voltages. A given output driver for a system-on-a-chip (SoC) for a mobile application will typically be configured for a particular I/O power supply voltage: either a high-voltage or a low-voltage power supply voltage depending upon the desired I/O standard.

It would be more efficient for an SoC manufacturer to provide a high-voltage/low-voltage output driver that can accommodate whatever standard (either high-voltage or low-voltage) that is chosen by a given customer. For example, a high-voltage output driver and a low-voltage driver could both be multiplexed to a given output terminal for an SoC. Depending upon what application is chosen by the user, the corresponding output driver would be active and selected for by the multiplexer to drive signals over the terminal to an external device. Although such a combination of output drivers may be suitable for lower-speed signaling, the multiplexing of the two output drivers onto a single output terminal loads the output terminal with a relatively high level of output capacitance. High-speed signaling over such a loaded terminal is then hindered by the excessive capacitive loading.

There is thus a need in the art for both a low-voltage data path and a high-voltage data path to interface a digital core to a hybrid output driver.

SUMMARY

A hybrid data path for a hybrid output driver is provided that includes: a high-voltage data path having: a first multiplexer configured to provide a high-voltage pull-up data signal for the hybrid output driver through a selection of a high-voltage data signal during a high-voltage data mode and through a selection of a first constant signal charged to a high-power supply voltage during a low-voltage data mode; and a second multiplexer configured to provide a high-voltage pull-down data signal for the hybrid output driver through a selection of the high-voltage data signal during the high-voltage data mode and through a selection of a first grounded signal during the low-voltage data mode; and a low-voltage data path having: a third multiplexer configured to provide a low-voltage pull-up data signal to the hybrid output driver through a selection of a low-voltage data signal during the low-voltage data mode and through a selection of a second constant signal charged to a low-power supply voltage during the high-voltage data mode, wherein the low-power supply voltage is less than the high-power supply voltage; and a fourth multiplexer configured to provide a low-voltage pull-down data signal to the hybrid output driver through a selection for the low-voltage data signal during the low-voltage data mode and through a selection of the first constant signal during the high-voltage data mode.

A method of operation for a hybrid data path to a hybrid output driver is provided that includes: during a high-voltage data mode: selecting for a high-voltage data signal to form a high-voltage pull-up data signal for the hybrid output driver to cause the hybrid output driver to charge an output terminal to a high-power supply voltage when the high-voltage pull-up data signal is discharged; selecting for the high-voltage data signal to form a high-voltage pull-down data signal for the hybrid output driver to cause the hybrid output driver to discharge the output terminal when the high-voltage pull-down data signal is charged to the high-power supply voltage; during a low-voltage data mode: charging both the high-voltage pull-up signal and the high-voltage pull-down signal to the high-power supply voltage; and selecting for a low-voltage data signal to form a low-voltage pull-down data signal to discharge the output terminal when the low-voltage pull-down data signal is charged to a low-power supply voltage that is less than the high-power supply voltage.

A hybrid data path for a hybrid output driver is provided that includes: an output terminal; a first transistor coupled between the output terminal and an input/output (IO) power supply voltage node; a first multiplexer configured to drive a gate of the first transistor with a high-voltage data signal during a high-voltage data mode; a second transistor having a source coupled to ground; a third transistor coupled between the output terminal and a drain of the second transistor; a second multiplexer configured to drive a gate of the third transistor with the high-voltage data signal during the high-voltage data mode; and a third multiplexer configured to drive a gate of the second transistor with a low-voltage data signal during a low-voltage data mode.

These and other advantageous features may be better appreciated through the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates an SoC with a hybrid output driver having tunable pull-up and pull-down impedances in accordance with an aspect of the disclosure.

FIG. 1B illustrates the pull-up and pull-down tuning aspects of the hybrid output driver of FIG. 1A in more detail.

FIG. 1C shows some simplified views of the hybrid output driver of FIG. 1A during the high-voltage and low-voltage modes of operation.

FIG. 2 illustrates an SoC with a hybrid output driver in which the pull-up and pull-down impedances are fixed in accordance with an aspect of the disclosure.

FIG. 3 is a flowchart for a method of operation for a hybrid output driver in accordance with an aspect of the disclosure,

FIG. 4 illustrates some example electronic systems each incorporating a hybrid output driver in accordance with an aspect of the disclosure.

Implementations of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.

DETAILED DESCRIPTION

A hybrid or combination high-voltage and low-voltage data path to a hybrid output driver is disclosed that accommodates signaling with both a relatively-high power supply voltage and a relatively-low power supply voltage. The hybrid output driver drives signals from a digital core such as in an application specific integrated circuit (ASIC) or an SoC to an external circuit. It will be assumed herein the external circuit is a low-power double data rate (LPDDR) dynamic random access memory (DRAM) but it will be appreciated that any external circuit that has a low-voltage data mode of operation and a high-voltage data mode of operation will benefit from the hybrid data path and hybrid output driver disclosed herein. The relatively-low power supply voltage is the power supply voltage for the digital core and for the LPDDR. DRAM during a low-voltage data mode for the LPDDR. DRAM. The relatively-high power supply voltage is the power supply voltage for the LPDDR DRAM during a high-voltage data mode for LPDDR DRAM. The digital core continues to use the relatively-low power supply voltage while the LPDDR DRAM operates in the high-voltage data mode.

An example low-voltage data path 105, a high-voltage data path 110, and a hybrid output driver 115 are shown in Figure for an SoC 100. In SoC 100, the high-voltage data mode of operation occurs according to the LPDDR3 memory standard whereas the low-voltage data mode of operation occurs according to the LPDDR4X memory standard or protocol but it will be appreciated that the high-voltage and low-voltage signaling disclosed herein is not limited to the LPDDR standards. Moreover, although the hybrid signaling architecture is shown for SoC 100, it will be appreciated that other types of integrated circuits would also benefit from this hybrid signaling architecture.

A digital core 120 for SoC 100 resides in a low-power voltage domain powered by a core power supply voltage Vdda that is compatible with thin-oxide transistors. There is thus no need to level shift a low-voltage input data signal DQLV from digital core 120 when driving low-voltage data path 105 as the circuits within low-voltage data path 105 are constructed with thin-oxide transistors. But the low-voltage input data signal DQLV is level-shifted in high-voltage data path 110 from the core power supply voltage VDDa to a relatively-high power supply voltage (Vddpx) of 1.2V that is used for the LPDDR3 signaling. Thin-oxide devices would be stressed by the relatively-high power supply voltage Vddpx. The circuits within high-voltage data path 110 are thus constructed with thick-oxide transistors as appropriate to protect them from being stressed from such a relatively-high power supply voltage.

Operation during the high-voltage data mode will he discussed first followed by a discussion of operation during the low-voltage data mode. These modes are applicable to any input/output protocol but the following examples will be directed to low-voltage and high-voltage signaling under the LPDDR protocol. In the LPDDR arts, an example of the high-voltage data mode is the LPDDR3 protocol (also designated herein as an LP3 mode of operation. Similarly, an example of the low-voltage data mode is the LPIDDR4X protocol (also designated herein as an LP4X mode of operation). During the LP3 mode of operation, high-voltage data path 110 level-shifts the low-voltage input data signal DQLV from digital core 120 into a high-voltage input data signal that is inverted by a NAND gate 130 to form a high-voltage data signal LP3DQ in the Vddpx power supply voltage domain (e.g., 1.2V) using a level-shifter 125. The high-voltage data signal LP3DQ from high-voltage data path 110 drives the gate of both a thick-oxide pull-up PMOS transistor P1 and a thick-oxide p NMOS transistor M2 in hybrid output driver 115. An input/output (IO) power supply voltage Vddio for hybrid output driver 115 equals the Vddpx power supply voltage for the LP3 mode of operation. Conversely, I/O power supply voltage Vddio equals the Vdda power supply voltage for LP4X mode of operation.

In hybrid output driver 115, the source of pull-up transistor P1 connects to the I/O power supply node for the I/O power supply voltage Vddio whereas the drain of pull-up transistor P1 drain couples to a drain for pull-down transistor M2 through a pair of resistors R arranged in series. A node between the pair of resistors R is tied to an output terminal 140 (which is also designated herein as output pad 140) for SoC 100. Should the high-voltage data signal LP3 DQ be a logical zero (ground), it will switch on pull-up transistor P1 to charge output pad 140 towards the I/O power supply voltage Vddio (which is Vddpx during the LP3 mode of operation). At the same time, pull-down transistor M2 would be switched off by the grounded data signal LP3DQ. Output pad 140 is thus charged to Vddpx during the LP3 mode of operation when high-voltage data signal LP3DQ is a logic zero. Conversely, the high-voltage data signal LP3DQ will switch on pull-down transistor M2 and switch off pull-up transistor P1 is when high-voltage data signal LP3DQ equals Vddpx during the LP3 mode of operation. The source of pull-down transistor M2 couples to ground through a thin-oxide NMOS transistor M1 that is maintained on during the high-voltage data mode as will be explained further herein. Output pad 140 will thus be discharged towards ground in response to the high-voltage data signal LP3DQ being charged to Vddpx. An external DRAM (not illustrated) configured for LPDDR3 operation would be coupled to output pad 140 to receive the resulting high-voltage data signals from output pad 140.

To provide a tunable pull-up impedance and pull-down impedance for the high-voltage data signals, pull-up transistor P1, pull-down transistor M2, and resistors R may each be instantiated in parallel as shown in FIG. 1B. Pull-up transistor P1 and pull-down transistor M2 are thus each shown as a single transistor in FIG. 1A for illustration clarity. As will be explained further herein, high-voltage data path 110 logically ORs the high-voltage data signal LP3 DQ with a N-bit wide active-low pull-up tuning signal PCNT<1:N> in an OR gate 155 to form a high-voltage pull-up data signal. Depending upon the desired strength of the pull-up, various bits in the pull-up tuning signal PCNT<1:N> shut down the corresponding parallel instantiation of pull-up transistor P1. Pull-up transistor P1 is instantiated by N PMOS transistors arranged in parallel starting from a PMOS pull-up transistor P11 to a PMOS pull-up transistor PIN. The gate of each these parallel-arranged pull-up transistors is driven by a corresponding bit from the ORed combination of high-voltage data signal LP3DQ and pull-up tuning signal PCNT<1:N> as produced by OR gate 155. Pull-up transistor P11 is thus driven by a signal DQ+PCNT1 which equals the logical OR of the pull-up tuning signal bit PCNT<1> and the high-voltage data signal LP3DQ. Similarly, a pull-up transistor P12 is driven by a signal DQ+PCNT2 which equals the logical OR of the pull-up tuning signal bit PCNT<2> and the high-voltage data signal LP3DQ. Finally, pull-up transistor Pi is driven by a signal DQ+PCNTN which equals the logical OR of pull-up tuning signal bit PCNT<N> and the high-voltage data LP3DQ. A low-voltage pull-up circuit (not illustrated) may also function to charge output terminal 140.

A source for each of pull-up transistor P11 through pull-up transistor P1N is connected to the I/O power supply node for the I/O power supply voltage Vddio as discussed with regard to FIG. 1A. The drain of pull-up transistor P11 connects to output pad 140 through a resistor R1 whereas the drain of pull-up transistor P12 connects to output pad 140 through a resistor 2R1 having twice the resistance of resistor R1. This binary progression of resistances continues for the remaining parallel-arranged pull-up transistors such that the drain of pull-up transistor P1N connects to output pad 140 through a resistor 2NR1 having a resistance that is 2N times greater than the resistance of resistor R1. It will be appreciated that this binary progression of resistances may be varied in alternative implementations. Depending upon which bits of the pull-up tuning signal are asserted, the corresponding pull-up transistors and resistors will not contribute to the pull-up of output pad 140. In this fashion, the pull-up tuning signal PCNT<1:N> may be readily tuned to provide the desired pull-up impedance for output pad 140.

The pull-down impedance tuning is analogous in that pull-down transistor M2 is instantiated as N NMOS pull-down transistors arranged in parallel between output pad 140 and the drain of transistor M1 starting with a first pull-down transistor M21 and finishing with an Nth pull-down transistor M2N. The drain of pull-down transistor M21 connects to output pad 140 through a resistor R1. Similarly, the drain of a second pull-down transistor M22 connects to output pad 140 through a resistor 2R1. This binary progression of resistances continues such that the drain of pull-down transistor M2N connects to output pad 140 through a resistor 2NR1, As discussed with the pull-up, this binary progression of resistances may be varied in alternative implementations. A source for each of pull-down resistors M21 through M2N connects to a drain of transistor M1.

High-voltage data path 110 logically ANDS the high-voltage data signal LP3DQ with a N-bit wide active-high pull-down tuning signal NCNT<1:N> in an AND gate 160 to form a high-voltage pull-down data signal. Depending upon the desired strength of the pull-up, various bits in the pull-down tuning signal NCNT<1:N> shut down the corresponding parallel instantiation of pull-down transistor M2. The gate of each of the parallel-arranged pull-down transistors is driven by a corresponding bit from the ANDed combination of high-voltage data signal LP3DQ and pull-down tuning signal NCNT<1:N>. The gate of pull-down transistor M21 is thus driven by a signal DQ*NCNT1 which equals the logical AND of pull-down tuning signal bit NCNT<1> and the high-voltage data signal LP3DQ. Similarly, a gate of a pull-down transistor M22 is driven by a signal DQ*NCNT2 which equals the logical AND of pull-down signal tuning bit NCNT<2> and the high-voltage data signal LP3DQ. Finally, a gate of pull-down transistor M2N is driven by a signal DQ*NCNTN which equals the logical AND of pull-down tuning signal bit PCNT<N> and the high-voltage data signal LPLP3DQ. The pull-down impedance tuning for output pad 140 in hybrid output driver 115 is thus performed in an analogous fashion as discussed for the pull-up impedance timing.

Referring again to FIG. 1A, NAND gate 130 in high-voltage data path 110 NANDs the output of level-shifter with an LP3 mode signal (LP3 mode) to gate the output of level-shifter 125 if the LP3 mode of operation is not selected by a logical zero value for the LP3 mode signal. During the LP3 mode of operation, the LP3 mode signal is asserted to the Vddpx power supply voltage. NAND gate 130 thus inverts the output of level-shifter 125 during the LP3 mode of operation so that the level-shifted signal may be buffered in a buffer 135 to form the high-voltage data signal LP3DQ. An output of buffer 135 may thus be deemed form a first node for the high-voltage data signal LP3DQ. A multiplexer 145 selects for the high-voltage data signal LP3DQ from buffer 135 during the LP3 mode of operation to drive OR gate 155 that then ORs the high-voltage data signal LP3DQ with the pull-up tuning signal PCNT<1:N> to form the ORed data signals for the pull-up tuning discussed with regard to FIG. 1B. During the LP4X mode of operation, multiplexer 145 drives OR gate 155 with a logical one signal (the Vddpx power supply voltage) so that transistors P11 through P1N are switched off.

High-voltage data path 110 also includes a multiplexer 150 that selects for the high-voltage data signal LP3DQ from buffer 135 during the LP3 mode of operation to drive AND gate 160 that then ANDs the high-voltage data signal LP3DQ with the pull-down tuning signal NCNT<1:N> to form the ANDed data signals for the pull-down tuning as also discussed with regard to FIG. 1B. During the LP4X mode of operation, multiplexer 150 selects for an LP3 mode off signal (LP3 modeoff) that equals the I/O power supply voltage Vddio while the LP4X mode is enabled. The pull-down tuning signal NCNT<1:N> thus controls which of pull-down transistors M21 through M2N are switched on during the LP4X mode of operation.

Note that the portion of high-voltage data path 110 subsequent to a first inverter in buffer 135 and prior to hybrid output driver 115 may be instantiated multiple times such that each instantiation may be selectively activated or de-activated to provide further timing ability for the driving of output pad 140. Of these additional instantiations, only a second inverter in buffer 135 shown in Figure I A for illustration clarity.

The low-voltage data mode of operation (the LP4X mode of operation) will now be discussed. Low-voltage data path 105 includes a gating NAND gate 165 that gates the low-voltage input data signal DQLV from digital core 120 during the LP3 mode but passes an inverted version of the low-voltage input data signal DQLV to a buffer 170 during the LP4X mode. To perform this gating, NAND gate 165 NANDs the low-voltage input data signal DQLV with an LP4 mode signal (LP4 mode) that is asserted during the LP4X mode of operation and that is de-asserted during the LP3 mode of operation. Buffer 170 buffers the inverted version of the low-voltage data signal DQLV from NAND gate 165 to form a buffered low-voltage data signal DQ that is still within the core power supply voltage domain (Vdda) for digital core 120. An output of buffer 170 may be deemed to form a second node for the low-voltage data signal DQ. A multiplexer 175 selects for the low-voltage data signal DQ during the LP4X mode of operation to form a low-voltage pull-down data signal that drives the gate of transistor M1. Should the low-voltage input data signal DQLV be a logic zero, the low-voltage data signal DQ will be high (the Vdda power supply voltage) so that transistor M1 switches on to discharge output pad 140 towards ground. The pull-down impedance is still controlled by transistors M21 through M2N as determined by the pull-down tuning signal as also occurs during the LP3 mode.

During the LP3 mode of operation, multiplexer 175 selects for an LP4 mode off signal (LP4 modeoff) that equals the I/O power supply voltage Vddio while the LP3 mode is enabled. Transistor M1 is thus switched on while the LP3 mode is enabled.

Low-voltage data path 105 also includes a multiplexer 180 that selects for the low-voltage data signal DQ to form a low-voltage pull-up data signal that drives a gate of a thin-oxide PMOS pull-up transistor P2 having its source tied to the I/O power supply node for the Vddio power supply voltage node. The drain of pull-up transistor P2 couples to output pad 140 through a thick-oxide pull-up tuning NMS transistor M3. Transistor M3 and a resistor R may be instantiated in parallel analogously as discussed with regard to FIG. 1B. It will be appreciated that resistor R may be deleted in alternative implementations. An n-bit wide complement of the pull-up tuning signal (PCNTB) drives the gates of the parallel-arranged pull-up transistors M3 as coupled through an AND gate 185 that ANDs the complement pull-up tuning signal PCNTB with an LP4X mode signal that is asserted during the LP4X mode of operation. The pull-up from pull-up transistor P2 is thus tuned through the parallel combination of pull-up transistors M3 and corresponding resistors during the LP4X mode of operation (these transistors and resistors are represented by single pull-up transistor M3 and resistor R in FIG. 1A for illustration clarity). During the LP3 mode of operation, the LP4X mode signal is a logical zero such that all the bits of the N-hit wide complement pull-up tuning signal PCNTB are zeroes. All the pull-up transistors M3 are then switched off Similarly, multiplexer 180 in low-voltage data path 105 selects for a logical one signal during the LP3 mode of operation to switch off pull-up transistor P2. To protect the thin oxide of pull-up transistor P2 during the LP3 mode of operation, a thick-oxide transistor P3 is switched on. The gate signal for thick-oxide transistor P3 is not shown in FIG. 1A for illustration clarity but this gate signal may be implemented using a complement of the LP4 mode signal. The source of thick-oxide transistor P3 is tied to the Vddio power supply voltage node whereas its drain is tied to the drain of pull-up transistor P2. The drain and source of pull-up transistor P2 are thus both charged to Vddpx during the LP3 mode of operation to protect pull-up transistor P2. A pair of diodes D1 and D2 coupled to the output pad 140 provide electrostatic discharge protection.

Operation of hybrid output driver 115 may be better appreciated through the simplified views shown in FIG. 1C. During an LP3 mode of operation (LP3 -enable), the logical OR of the high-voltage data signal LP3DQ and the pull-up tuning signal PCNT drives the gate of pull-up transistor P1. Similarly, the logical AND of the high-voltage data signal LP3DQ and the pull-down tuning signal NCNT drives the gate of pull-down transistor M2. Transistor M1 is on. Pull-up transistors P2 and M3 are off Transistor P3 is on to protect pull-up transistor P2. Should an instantiation of hybrid output driver 115 be disabled during the LP3 mode of operation (LP3 -Disable), transistors M1, M2, M3, P1, and P2 are all off but transistor P3 remains on for protection of transistor P2.

During an LP4X mode of operation (LP4X-Enable), pull-up transistor P1 and transistor P3 are both off. The buffered data signal DQ from low-voltage data path 105 drives the gates of transistor M1 and pull-up transistor P2. The pull-down tuning signal NCNT drives the gate of pull-down transistor M2 whereas the complement pull-up signal PCTNB drives the gate of transistor M3. Should an instantiation of hybrid output driver 115 be disabled during the LP4X mode of operation (LP4X-Disable), transistors M1, M2, M3, P1, P2, and P3 are all off.

The hybrid architecture disclosed herein may be simplified as shown in FIG. 2 for an SoC 200 in which the pull-up and pull-down impedances are fixed rather than tunable. SoC 200 includes a low-voltage data path 205, a high-voltage data path 210, and a hybrid output driver 215 arranged analogously as discussed with regard to SoC 100. However, there is just a single pull-up transistor P1 and corresponding resistor R in hybrid output driver 215. There is thus no pull-up or pull-down tuning so that high-voltage data path 210 does not include corresponding NOR gate 155 and AND gate 160. High-voltage data path 210 thus includes only level-shifter 125. NAND gate 130, buffer 135, and multiplexers 145 and 150 arranged as discussed for high-voltage data path 110. Pull-up transistor P1 in hybrid output driver 215 has its gate driven by the output of multiplexer 145 from high-voltage data path 210. The pull-up impedance for hybrid output driver 215 during the LP3 mode of operation is thus controlled by the resistance for resistor R. Similarly, the output of multiplexer 150 in high-voltage data path 210 drives the gate of a single pull-down transistor M2 having a drain coupled to output pad 140 through another resistor R so that the pull-down impedance for hybrid output driver 215 during the LP3 mode of operation is also controlled by the resistance for resistor R. Low-voltage data path 205 includes NAND gate 165, buffer 170, and multiplexers 180 and 175 arranged as discussed for low-voltage data path 105.

In hybrid output driver 215, pull-down transistor M2 controls the pull-down impedance during the LP4X mode of operation. During pull-up for the LP4X mode of operation, the LP4X mode signal is asserted to switch on pull-up transistor M3 (which is not instantiated in parallel). The pull-up impedance during the LP4X mode of operation is thus controlled by the resistance of the resistor R tied to the source of transistor M3. For illustration clarity, the LP3 mode off signal that is selected by multiplexer 150 during the LP4X mode of operation is shown as a binary one in FIG. 2 since that is the value of the LP3 mode off signal when the LP4X mode is enabled. Similarly, the LP4 mode off signal that is selected by multiplexer 175 during the LP3 mode of operation is shown as a binary one signal in FIG. 2 for illustration clarity since that is the value of the LP4 mode off signal when the LP3 mode is enabled.

A method of operation for a hybrid data path for a hybrid output driver will now be discussed with regard to the flowchart, of FIG. 3. The method includes a high-voltage data mode act 300 of selecting for a high-voltage data signal to form a high-voltage pull-up data signal for the hybrid output driver to cause the hybrid output driver to charge an output terminal to a high-power supply voltage when the high-voltage pull-up data signal is discharged. An example of act 300 is the selection in multiplexer 145 for the high-voltage data signal to switch on pull-up transistor P1. The method includes another high-voltage data mode act 305 of selecting for the high-voltage data signal to form a high-voltage pull-down data signal for the hybrid output driver to cause the hybrid output driver to discharge the output terminal when the high-voltage pull-down signal is charged to the high-power supply voltage. The selection in multiplexer 150 for the high-voltage data signal to switch on pull-down transistor M2 is an example of act 305.

The method also includes a low-voltage data mode act 310 charging both the high-voltage pull-up signal and the high-voltage pull-down signal to the high-power supply voltage. The selection for the high-power supply voltage node by multiplexers 145 and 155 to switch off pull-up transistor P1 and switch on pull-down transistor M2 is example an of act 310. Finally, the method includes another low-voltage data mode act 315 of selecting for a low-voltage data signal to form a to discharge the output terminal When the low-voltage pull-down signal is charged to a low-power supply voltage that is less than the high-power supply voltage. The selection in multiplexer 175 for the low-voltage data signal to switch on pull-down transistor M2 is an example of act 315.

A hybrid data path for a hybrid output driver as disclosed herein may be advantageously incorporated in any suitable mobile device or electronic system. For example, as shown in FIG. 4, a cellular telephone 400, a laptop computer 405, and a tablet PC 410 may all include a hybrid data path in accordance with the disclosure. Other exemplary electronic systems such as a music player, a video player, a communication device, and a personal computer may also be configured with hybrid data paths constructed in accordance with the disclosure.

It will be appreciated that many modifications, substitutions and variations can be made in and to the materials, apparatus, configurations and methods of use of the devices of the present disclosure without departing from the scope thereof. In light of this, the scope of the present disclosure should not be limited to that of the particular implementations illustrated and described herein, as they are merely by way of some examples thereof, but rather, should be fully commensurate with that of the claims appended hereafter and their functional equivalents.

Claims

1. A hybrid data path for a hybrid output driver, comprising:

a high-voltage data path including: a first multiplexer configured to provide a high-voltage pull-up data signal for the hybrid output driver through a selection of a high-voltage data signal during a high-voltage data mode and through a selection of a first constant signal charged to a high-power supply voltage during a low-voltage data mode; and a second multiplexer configured to provide a high-voltage pull-down data signal for the hybrid output driver through a selection of the high-voltage data signal during the high-voltage data mode and through a selection of a first grounded signal during the low-voltage data mode; and
a low-voltage data path including: a third multiplexer configured to provide a low-voltage pull-up data signal to the hybrid output driver through a selection of a low-voltage data signal during the low-voltage data mode and through a selection of a second constant signal charged to a low-power supply voltage during the high-voltage data mode, wherein the low-power supply voltage less than the high-power supply voltage; and a fourth multiplexer configured to provide a low-voltage pull-down data signal to the hybrid output driver through a selection for the low-voltage data signal during the low-voltage data mode and through a selection of the first constant signal during the high-voltage data mode.

2. The hybrid data path of claim 1, wherein the high-voltage data path further includes:

a level-shifter for level-shifting a low-voltage input data signal into a high-voltage data input signal.

3. The hybrid data path of claim 1, wherein the high-voltage data path further includes:

an inverter for inverting a high-voltage input data signal to form the high-voltage data signal.

4. The hybrid data path of claim 3, wherein the inverter comprises a NAND gate configured to NAND the high-voltage input data signal with a high-voltage data mode signal that is asserted during the high-voltage data mode and that is de-asserted during the low-voltage data mode.

5. The hybrid data path of claim 1, wherein the low-voltage data path further includes:

an inverter for inverting a low-voltage data input signal to form the low-voltage data signal.

6. The hybrid data path of claim 5, wherein the inverter comprises a NAND gate configured to NAND the low-voltage input data signal with a low-voltage data mode signal that is asserted during the low-voltage data mode and that is de-asserted during the high-voltage data mode.

7. The hybrid data path of claim 1, further comprising:

a first logic gate configured to process an output from the first multiplexer with a pull-up impedance tuning signal to form the high-voltage pull-up data signal.

8. The hybrid data path of claim 7, further comprising:

a second logic gate configured to process an output from the second multiplexer with a pull-down impedance tuning signal to form the high-voltage pull-down data signal.

9. The hybrid data path of claim 8, wherein the first logic gate is an OR gate.

10. The hybrid data path of claim 9, wherein the pull-up impedance tuning signal is an N-bit wide digital word, N being a plural positive integer.

11. The hybrid data path of claim 9, wherein the second logic gate is an AND gate.

12. The hybrid data path of claim 11, wherein the pull-down impedance tuning signal is an N-hit wide digital word, N being a plural positive integer.

13. The hybrid data path of claim 4, wherein the high-voltage data path further includes a buffer configured to buffer the high-voltage data signal.

14. The hybrid data path of claim 6, wherein the low-voltage data path further includes a buffer configured to buffer the low-voltage data signal.

15. A method of operation for a hybrid data path to a hybrid output driver comprising:

during a high-voltage data mode:
selecting for a high-voltage data signal to form a high-voltage pull-up data signal for the hybrid output driver to cause the hybrid output driver to charge an output terminal to a high-power supply voltage when the high-voltage pull-up data signal is discharged;
selecting for the high-voltage data signal to form a high-voltage pull-down data signal for the hybrid output driver to cause the hybrid output driver to discharge the output terminal when the high-voltage pull-down data signal is charged to the high-power supply voltage;
during a low-voltage data mode:
charging both the high-voltage pull-up data signal and the high-voltage pull-down data signal to the high-power supply voltage; and
selecting for a low-voltage data signal to form a low-voltage pull-down data signal to discharge the output terminal when the low-voltage pull-down data signal is charged to a low-power supply voltage that is less than the high-power supply voltage.

16. The method of claim 15, further comprising:

during the low-voltage data mode:
selecting for the low-voltage data signal to form a low-voltage pull-up data signal to cause the hybrid output driver to charge the output terminal when the low-voltage pull-up data signal is discharged.

17. The method of claim 16, further comprising:

during the high-voltage mode:
charging both low-voltage pull-up data signal and the low-voltage pull-down data signal to the low-power supply voltage.

18. The method of claim 15, further comprising:

during the high-voltage mode:
level-shilling a low-voltage input data signal to form a high-voltage input data signal; and
inverting the high-voltage input data signal to form the high-voltage data signal.

19. The method of claim 18, further comprising:

during the low-voltage mode:
inverting the low-voltage input data signal to form the low-voltage data signal.

20. A hybrid data path for a hybrid output driver, comprising an output terminal;

a first transistor coupled between the output terminal and an input/output (IO) power supply voltage node;
a first multiplexer configured to drive a gate of the first transistor with a high-voltage data signal during a high-voltage data mode;
a second transistor having a source coupled to ground;
a third transistor coupled between the output terminal and a drain of the second transistor;
a second multiplexer configured to drive a gate of the third transistor with the high-voltage data signal during the high-voltage data mode; and
a third multiplexer configured to drive a gate of the second transistor with a low-voltage data signal during a low-voltage data mode.

21. The hybrid data path of claim 20, wherein the first multiplexer is further configured to drive the gate of the first transistor with a first constant signal charged to a high-power supply voltage during the low-voltage data mode, and wherein the third multiplexer is further configured to drive the gate of the second transistor with a second constant signal charged to low-power supply voltage during the high-voltage data mode, and wherein the low-power supply voltage is less than e high-power supply voltage.

22. The hybrid data path of claim 21, wherein the high-power supply voltage is low power double date rate 4X dynamic random access memory (DRAM) power supply voltage, and wherein the low-power supply voltage is a low power double data rate 3 DRAM power supply voltage.

23. The hybrid data path of claim 21, further comprising:

a digital core for generating a low-voltage input data signal; and
an inverter configured to invert the low-voltage input data signal to form the low-voltage data signal.
Patent History
Publication number: 20200235737
Type: Application
Filed: Jan 15, 2020
Publication Date: Jul 23, 2020
Inventors: Young Uk YIM (San Diego, CA), Jacob SCHNEIDER (San Diego, CA), Satish KRISHNAMOORTHY (San Diego, CA), Ashwin SETHURAM (San Clemente, CA), Chang Ki KWON (San Diego, CA), Mostafa Naguib ABDULLA (Rancho Cordova, CA)
Application Number: 16/743,872
Classifications
International Classification: H03K 19/003 (20060101); H03K 19/017 (20060101); G06F 3/06 (20060101);