THREE-DIMENSIONAL FERROELECTRIC RANDOM-ACCESS MEMORY (FERAM)

A 3-dimensional vertical memory string array includes high-speed ferroelectric field-effect transistor (FET) cells that are low-cost, low-power, or high-density and suitable for SCM applications. The memory circuits of the present invention provide random-access capabilities. The memory string may be formed above a planar surface of substrate and include a vertical gate electrode extending lengthwise along a vertical direction relative to the planar surface and may include (i) a ferroelectric layer over the gate electrode, (ii) a gate oxide layer; (iii) a channel layer provided over the gate oxide layer, and (iv) conductive semiconductor regions embedded in and isolated from each other by an oxide layer, wherein the gate electrode, the ferroelectric layer, the gate oxide layer, the channel layer and each adjacent pair of semiconductor regions from a storage transistor of the memory string, and wherein the adjacent pair of semiconductor regions serve as source and drain regions of the storage transistor.

Skip to: Description  ·  Claims  · Patent History  ·  Patent History
Description
CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a continuation-in-part application of U.S. patent application (“Parent application”), Ser. No. 16/558,072, entitled “Three-Dimensional Ferrelectric Random-Access Memory (FeRAM),” filed on Aug. 31, 2019, which is related to and claims priority of U.S. provisional patent application (“Provisional Application”), Ser. No. 62/846,418, entitled “3D Ferroelectric Random-Access Memory With MLC Capability,” filed on May 10, 2019. The disclosure of the Provisional Application is hereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to memory circuits. In particular, the present invention relates to high-density, ferroelectric random-access memory arrays including memory cells provided in a 3-dimensional configuration.

2. Discussion of the Related Art

An erase operation in a 3-dimensional non-volatile memory circuits (e.g., NAND-type flash memory circuits) is typically carried out on a block-by-block basis, which involves a long access time. Such memory circuits are not suitable for use in high speed (˜50 ns), high density storage class memory (SCM) applications.

Other alternative memory circuits, for example, include:

    • (i) 3D XPoint memory circuits, jointly developed by Intel Corporation and Micron Corporation, while allowing bit-by-bit access that is suitable for SCM applications, use cross-point patterning (i.e., double exposures for patterning each material layer), which is prohibitively high in manufacturing cost. Also, such 3D XPoint memory circuits are based on a phase-change material (PCM), which results in high leakage currents and, hence, high power dissipation from sneak paths. Selector devices are needed to reduce the leakage currents from sneak paths, which increase the complexity of process and device integration.
    • (ii) U.S. Pat. Nos. 10,249,370, 10,121,554, 10,121,553, and 9,892,800 disclose 3-dimensional vertical NOR-type memory string arrays, which require complicated X and Y patterning schemes. Due to NOR architecture, the power consumption is also high.

Ferroelectric memory circuits provide yet another alternative. U.S. Pat. No. 6,067,244 to T. Ma, entitled “Erroelectric Dynamic Random Access Memory, filed on Sep. 16, 1998, discloses a ferroelectric field-effect transistor (FeFET) that can serve as a memory circuit, as dipole moments in the FeFET can be aligned in either one of two configurations by an electric field. However, conventional ferroelectric materials, such as those based on lead zirconate titanate (PZT) and strontium bismuth tantalate (SBT), for example, do not provide high-density memory circuits. This is because the ferroelectric layer in an FeFET based on these materials must at least 70 nm thick.

FeFETs based on Hafnium oxide (HfD2) are, however, promising. U.S. patent application publication 2018/0366547A1 (“Liu”) discloses various examples of FeFETs. For example, FIGS. 2a and 2b, reproduced respectively from FIG. 4A and FIG. 4B in Liu's disclosure, illustrate the programmed states of exemplary FeFET 1.

As shown in both FIGS. 2a and 2b, FeFET 1 is formed on a p−-type substrate 10 and includes n+-type source and drain regions 101 and 102, respectively, channel region 103, tunneling dielectric layer 13, charge storage region 12 and gate electrode 11. Charge region 12 includes ferroelectric layer 120 and paraelectric layer 121. Paraelectric layer 121 has a “quantum well” energy band structure, which enables a charge-trapping capability suitable for a data storage application. Paraelectric layer 121 may have, for example, alternating layers of a base material and a dielectric material. The base material may be, for example, Hf1−xSixO2—x being a value between 0.02 and 0.65, while the dielectric material may be selected from the group consisting of hafnium oxide, zirconium oxide, titanium oxide, titanium nitride, tantalum nitride, aluminum oxide, tantalum oxide and any combination thereof. The alternating layers of base and dielectric materials may be formed using, for example, ALD processes.

Ferroelectric layer 120 may include an alkaline earth metal oxide or a transition metal oxide, such as hafnium oxide, zirconium oxide or hafnium zirconium oxide, with or without a 2-10% dopant selected from the group consisting of silicon, aluminum, yttrium, strontium, gadolinium, lanthanum and any combination thereof. One example of a ferroelectric material is Hf1−xSixO2, x ranging between 0.01 and 0.05. The composite material may also include hydrogen atoms in the manufacturing process. Liu discloses that the charge storage region 12 may be 1.0-30.0 nm thick, preferably 5.0-15.0 nm thick.

As shown in FIG. 2a, when a positive bias (e.g., Vt) is applied to gate electrode 11, the electric dipoles in the ferroelectric layer 12 align with the electric field, such that electrons in channel region 103 tunnel through tunnel dielectric layer 13 into and are trapped in paraelectric layer 121. The trapped charge causes positive charge carriers (i.e., holes) to accumulate in channel region 103 (“0” state, which provides a polarization switching voltage for the storage transistor). In this “0” state, FeFET 1 is non-conducting at the read voltage.

As shown in FIG. 2b, when a negative bias (e.g., −Vt) is applied to gate electrode 11, the electric dipoles in charge storage region 12 allow holes in channel region 103 to tunnel to and be trapped in paraelectric layer 121. The trapped charge cause electron accumulation at channel region 103 (“1” state, which provides a negative polarization switching voltage). In this “1” state, FeFET 1 conducting at the read voltage.

Liu also discloses that the ferroelectric layer 120 and paraelectric layer 121 need not be distinct. The ferroelectric layer 120 and paraelectric layer 121 may be provided as a single layer as a blend of the ferroelectric and paraelectric materials.

As disclosure in Liu, a hafnium oxide-based FeFET may be made with a ferroelectric layer that is less than 10 nm thick. Furthermore, such an FeFET may provide a 1-volt threshold-shift window. For example, the article, entitled “Low-Leakage-Current DRAM-Like Memory Using a One-Transistor Ferroelectric MOSFET With a Hf-Based Gate Dielectric” (“Cheng”), by C. Cheng and A. Chin, published in IEEE Electronic Device Letters, vol. 35. No. 1, 2014, pp. 138-140, disclose a high-endurance FeFET with a 30 nm thick zirconium-doped HfO2 ferroelectric layer that can be programmed or erase in 5 ns.

FIG. 1a shows an architecture of an AND-type FeFET array that can be laid out in a conventional 4F2 configuration. FIG. 1a also provides a table that shows the voltage biases for the word line (WL(m), the source line (SL(m)) and the bit line (BL(m)) of a selected FeFET, as well as the voltage biases for the word line (WL(m+1), the source line (SL(m+1)) and the bit line (BL(m+1)) of a non-selected FeFET, during program, erase and read operations. In Cheng, for example, the programming voltage Vpmg and the read voltage Vread for such an FeFET may be −4.0 volts and −0.1 volts, respectively.

FIG. 1b shows an architecture of a NOR-type FeFET array. FIG. 1b also provides a table that shows the voltage biases for the word line (WL(m), the source line (SL(m)) and the bit line (BL(m)) of a selected FeFET, as well as the voltage biases for the word line (WL(m+), the source line (SL(m+1)) and the bit line (BL(m+1)) of a non-selected FeFET, during program, erase and read operations.

SUMMARY

The present invention provides a 3-dimensional vertical memory string array that includes high-speed ferroelectric field-effect transistor (FET) cells that are low-cost, low-power, or high-density and suitable for SCM applications. The memory circuits of the present invention provide random-access capabilities.

According to one embodiment of the present invention, a memory string formed above a planar surface of substrate includes: (a) a vertical gate electrode (e.g., tungsten or a heavily doped semiconductor) extending lengthwise along a vertical direction relative to the planar surface, (b) a ferroelectric layer provided over at least a portion of the gate electrode along a horizontal direction substantially parallel the planar surface and extending lengthwise along the vertical direction; (c) a gate oxide layer provided over at least a portion of the ferroelectric layer along the horizontal direction and extending lengthwise along the vertical direction; (d) a channel layer provided over at least a portion of the gate oxide layer along the horizontal direction and extending lengthwise along the vertical direction; and conductive semiconductor regions embedded in and isolated from each other by an oxide layer arrayed along the horizontal direction, wherein the gate electrode, the ferroelectric layer, the channel layer, the gate oxide layer and each adjacent pair of semiconductor regions from a storage transistor of the memory string, and wherein the adjacent pair of semiconductor regions serve as source and drain regions of the storage transistor. In addition, a barrier layer (e.g., titanium nitride, tungsten nitride or tantalum nitride) may be provided between the gate electrode and the ferroelectric layer. The drain or source region may also be provided drain or source electrodes (e.g., tungsten or n+ polysilicon).

The memory strings of the present invention may be organized into a memory array, and a staircase configuration provides electrical contacts to each of the source or drain electrodes. Storage transistors may be provided on opposite sides of each memory hole in which the gate, the ferroelectric layer, the gate oxide layer and the channel silicon layer are provided. One or more networks of global word line conductors each connecting the gate electrodes of a selected group of the memory strings may be provided above the memory array, below the memory array or both.

The ferroelectric layer comprises a zirconium-doped or silicon-doped HfO2 ferroelectric material. The zirconium-doped hafnium silicon oxide may have a zirconium content of 40-60%, preferably 45-55%. The silicon-doped hafnium silicon oxide may have a silicon content of 2.0-5.0%, preferably 2.5-4.5%. The hafnium silicon oxide is prepared by depositing HfD2 and SiO2 or ZrO2 using an ALD layer-by-layer lamination step.

In one embodiment the memory string further includes a charge-trapping layer that is between the gate oxide layer and the ferroelectric layer or between the ferroelectric layer and the barrier layer.

Various manufacturing processes, some of which are illustrated herein, may be used to fabricate a memory array of the memory strings of the present invention.

The present invention is better understood upon consideration of the detailed description below in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1a shows an architecture of an AND-type FeFET array that can be laid out in a conventional 4F2 configuration.

FIG. 1b shows an architecture of a NOR-type FeFET array.

FIGS. 2a and 2b, reproduced from FIG. 4A and 4B of U.S. patent application publication 2018/0366547A1 (“Liu”), illustrate the programmed states of exemplary FeFET 1.

FIG. 3a shows a vertical section of memory array 300, which includes a regular arrangement of vertical 3-dimensional (3-D) FeFET strings; FIG. 3a shows, in particular, vertical 3-D FeFET strings 300a, 300b and 300c, according to one embodiment of the present invention.

FIG. 3b shows an Y-Z plane cross section of memory array 300, showing the gate, drain and source connectivities of eight vertical 3-D FeFET strings, according to one embodiment of the present invention.

FIGS. 4a, 4b, 4c, 4d(i), 4d(ii), 4e, 4f, 4g, 4h, 4h(i), 4h(ii), 4i(i), 4i(ii), 4j(i), 4j(ii), 4k(i), 4k(ii), 4l(i), and 4l(ii) illustrate an exemplary fabrication process for memory array 400, in accordance with one embodiment of the present invention.

FIG. 5 shows memory array 400 provided electrical contacts or connections to drain or source electrodes 423 via staircase structures on both sides of memory array 400 and contacts or connections to gate electrodes 423 using the bottom global word lines (e.g., global word line 401).

FIGS. 6a, 6b, 6c(i), 6c(ii), 6d, 6e, 6f(i), 6f(ii), 6g(i), 6g(ii), 6h(i), 6h(ii), 6i, and 6j illustrate an exemplary fabrication process for memory array 600, in accordance with one embodiment of the present invention.

FIGS. 7a, 7b(i), 7b(ii), 7c(i), 7c(ii), 7d, 7e, 7f, and 7g illustrate an exemplary fabrication process for memory array 700, in accordance with one embodiment of the present invention.

FIGS. 8a, 8b-1, 8b-2, 8c, 8d-1, 8d-2, 8e, 8f, 8g(i), 8g(ii), 8h(i), 8h(ii), 8i(i), 8i(ii), 9i(iii) and 8j illustrate an exemplary fabrication process for memory array 800, in accordance with one embodiment of the present invention.

To facilitate cross-referencing among the figures, like elements are assigned like reference numerals. The figures may depict 3-dimensional objects from different perspectives. To facilitate description of 3-dimensional objects, a cartesian coordinate system is provided, with X- and Y-directions denoting orthogonal horizontal directions and the Z-direction denoting the vertical direction. As this detailed description refers to structures fabricated on a planar surface of a substrate, “vertical” is understood to refer to the direction substantially perpendicular to the planar surface and “horizontal” is understood to refer to directions substantially parallel to the planar surface.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention may be carried out by, for example, a vertical metal-ferroelectric-insulator semiconductor (MFIS) transistor that includes (a) tungsten/titanium nitride or n+ polysilicon/titanium nitride gate electrode, (ii) zirconium-doped or silicon-doped HfO2 ferroelectric layer, (iii) a gate oxide layer, (iv) a p-type channel region, (v) an n-type source region, and (v) an n-type drain region.

In such an MFIS transistor, the n+ polysilicon may be arsenic-doped polysilicon with dopant concentration of 5.0×1021 to 1.0×1022 cm−3. The HfO2 ferroelectric layer may be 5.0-15.0 nm thick, preferably 8.0-12.0 nm thick, deposited by atomic layer deposition (ALD). If doped by zirconium, the ferroelectric layer should have zirconium content of 40-60%, preferably 45-55%. If doped by silicon, the ferroelectric layer should have silicon content of 2.0-5.0%, preferably 2.5-4.5%. The gate oxide layer may be, for example, 1.0-3.0 nm thick silicon oxide (SiO2) or silicon oxynitride (SiON). The p-type channel region may be, for example, intrinsic polysilicon or boron-doped polysilicon with a dopant concentration of 1.0×1016 to 1.0×1018 cm−3, deposited by chemical vapor deposition (CVD), using any of boron, diborane (H2B2), and trimethyl borane (B(CH3)3 gases, or any of their combinations). The n-type drain and source regions may each be, for example, phosphorus-doped or arsenic-doped polysilicon with a dopant concentration of 1.0×1020 to 1.0×1022 cm−3, deposited by CVD, using phosphine (PH3) or phosphorus trichloride (PCl3), if phosphorus-doped, and arsenic or arsenic hydride (AsH3), if arsenic-doped.

Si-doped Hf1−xSixOy ferroelectric thin-film may be formed by depositing HfO2 and SiO2 using ALD layer-by-layer lamination, which allows the values of x and y be adjusted by the individual cycle numbers of HfO2 and SiO2. For example, x may range from 0.02 to 0.05, preferably between 0.025 and 0.04, and y may range from 1.8 to 2.2, preferably between 1.9 and 2.1. A suitable Hf1−xSixOy ferroelectric thin-film may be, for example, between 5.0-15.0 nm thick, preferably between 8.0-12.0 nm thick for FeFET memory applications. HfD2 may be prepared from any of the following precursors: tetrakis(ethylmethylamino) hafnium (TEMAH), tetrakis(dimethylamino) hafnium (TDMAH) and hafnium tetrachloride (HfCl4), using as oxidant O3 or H2O, at a deposition temperature between 150-400° C. Similarly, SiO2 can be prepared from any of the following precursors: tetrakis(dimethylamino) silane (4DMAS), tris(dimethylamino) silane (3DMAS), tetrakis(ethylmethylamino) silane (TEMA-Si) and silicon tetrachloride (SiCl4), using as oxidant O3 or H2O, at a deposition temperature between 150-400° C.

Zr-doped HfxZr1−xOy ferroelectric thin-films may be formed by depositing HfO2 and ZrO2 using ALD layer-by-layer lamination, which allows the values of x and y be adjusted by the individual cycle numbers of HfO2 and ZrO2. For example, x may range between 0.4 and 0.6, preferably between 0.45 and 0.55, and y may range between 1.8 and 2.2, preferably between 1.9 to 2.1. A suitable HfxZr1−xOy ferroelectric thin-film may be 5.0-15.0 nm thick, preferably 8.0-12.0 nm thick for FeFET memory applications. HfO2 may be prepared from any of the following precursors: tetrakis(ethylmethylamino) hafnium (TEMAH), tetrakis(dimethylamino) hafnium (TDMAH), and hafnium tetrachloride (HfCl4), using as oxidant O3 or H2O, at a deposition temperature of 150-400° C. ZrO2 may be prepared from any of the following precursors: tetrakis(ethylmethylamino) zirconium (TEMAZ), tetrakis(dimethylamino) zirconium (TDMAZ) and zirconium tetrachloride (ZrCl4), using as oxidant O3 or H2O, at a deposition temperature between 150-400° C.

FIG. 3a shows a vertical section in the X-Z plane of memory array 300, which includes a regular arrangement of vertical 3-dimensional (3-D) FeFET strings; FIG. 3a shows, in particular, vertical 3-D FeFET strings 300a, 300b and 300c, according to one embodiment of the present invention. FIG. 3a shows three vertical 3-D FeFET strings merely for the purpose of illustration; memory array 300 may include many more than vertical 3-D FeFET strings arranged along each of the X- and Y-directions.

As shown in FIG. 3a, each vertical 3-D FeFET string includes (i) multiple annular drain electrodes 301-1, 301-2, . . . , and 301-n, (ii) multiple annular source electrodes 302-1, 302-2, . . . , and 302-n, (iii) annular channel polysilicon region 303, (iv) gate or tunnel oxide layer 303a, and (v) annular ferroelectric layer 304, surrounding common gate electrode 308. Common gate electrode 308 may have a conductor core (e.g., tungsten or heavily doped n-type polysilicon) with an outer adhesion layer or barrier layer (e.g., titanium nitride) 305. Each vertical 3-D FeFET string is electrically isolated by top and bottom isolation layers 307 and 309.

Each drain or source electrode may be provided, for example, by n-type polysilicon, titanium nitride, tungsten or any combination of these materials. Channel polysilicon region may be provided, for example, by p-type polysilicon. Ferroelectric layer 304 may be provided by, zirconium-doped or silicon-doped HfO2 ferroelectric material. Common gate electrode may be provided, for example, by tungsten/titanium nitride or n+ polysilicon/titanium nitride. Gate oxide layer 303a may be provided, for example, SiO2 or SiON.

In each vertical 3-D FeFET string, each memory cell is an MFIS transistor formed by an adjacent pair of drain and source electrodes (e.g., drain electrode 301-1 and source electrode 302-1), and the portions of channel polysilicon region 303, gate or tunnel oxide layer 303a, annular ferroelectric-paraelectric layer 304, and common gate electrode 308 between the adjacent drain and source electrodes. FIG. 3a also shows that the gate electrodes of vertical 3-D FeFET strings 300a, 300b and 300c are electrically connected by conductive global word line 306. In memory array 300, (i) the common gate electrodes in a row of vertical 3-D FeFET strings along the X-direction are electrically connected; (ii) drain electrodes at the same vertical level of the vertical 3-D FeFET strings in a row along the Y-direction are electrically connected; and source electrodes at the same vertical level of the vertical 3-D FeFET strings in a row along the Y-direction are electrically connected.

FIG. 3b shows an Y-Z plane cross section of memory array 300, showing the gate, drain and source connectivities of eight vertical 3-D FeFET strings, according to one embodiment of the present invention. Again, FIG. 3b shows eight vertical 3-D FeFET strings merely for the purpose of illustration. In any embodiment, memory array 300 may include more than eight vertical 3-D FeFET strings arranged along each of the X- and Y-directions. FIG. 3b illustrate selection of MRS transistor or cell 401 by applying selection voltage biases on associated gate electrode 308-m, drain electrode 301-m and source electrode 302-m. There are three types of non-selected MRS transistors: (a) “selected gate, non-selected drain or source” MFIS transistors—those sharing selected gate electrode 308-m, but are associated with one of non-selected drain electrodes 301 and one of the non-selected source electrodes 302; (b) “non-selected gate, selected drain or source” MRS transistors—those MRS transistors associated with one of the non-selected gate electrodes 308, but associated with selected drain electrode 301-m and selected source electrode 302-m; and (c) “non-selected gate, non-selected drain or source” MRS transistors—those MRS transistors associated with neither selected gate electrode 308-m, nor with selected drain electrode 301-m and selected source electrode 302-m. In a reading, programming, or erase operation, different voltage biases are required for a selected MRS transistor and each of the three types of non-selected MRS transistors.

FIGS. 4a-4l illustrate an exemplary fabrication process for memory array 400, in accordance with one embodiment of the present invention. As shown in vertical section in FIG. 4a, a network of conductors (“global gate lines”), including global gate line 402, are formed over semiconductor substrate 401, which may be a semiconductor wafer. The global gate lines may be formed out of tungsten, isolated from each other and from semiconductor substrate 401 by an isolation layer (e.g., silicon oxide).

Thereafter, as shown in vertical section FIG. 4b, oxide layer 403 (e.g., silicon oxide) and bottom etch stop layer 404 (e.g., n+ polysilicon) are deposited over the global gate lines.

Etch stop layer 404 may be patterned, as shown, and embedded in oxide layer 403. Then, as shown in vertical section in FIG. 4c, alternating layers of silicon oxide layers 405 and silicon nitride layers 406 are deposited, numbered herein as silicon oxide layers 405-1, . . . , and 405-n, and silicon nitride layers 406-1, . . . , 406-n, respectively.

An array of shafts (“memory holes”) 407 (e.g., memory holes 407-1, 407-2 and 407-3) are then etched through the alternating layers of silicon oxide layers 405 and silicon nitride layers 406 down to etch stop layer 404, as shown in vertical section in FIG. 4d(i). FIG. 4d(ii) shows in horizontal cross section through one of silicon nitride layers 406, showing memory holes 407-1 to 407-9 of memory array 400 at this step of formation.

Polysilicon layer 409 is then conformally deposited, followed by deposition of thin gate oxide layer 410. Polysilicon 409 may be deposited as amorphous silicon and annealed at 850° C. for 2 hours to crystallize. Protective layer 408 may then be deposited over gate oxide layer 410. A spacer etch is then carried out to remove any deposited polysilicon and gate oxide from the bottom of memory holes 407. Chemical mechanical polishing (CMP) step may be carried out to remove materials of protective layer 408, gate oxide 410, and polysilicon layer 409 from the top of the structure. The resulting structure (i.e., memory array 400 at this step of formation) is shown in vertical section in FIG. 4e.

Protective layer 408 is then removed. Ferroelectric layer 411 (e.g., a Si-doped or Zr-doped Hf1−xSixOy, HfxZr1−xOy ferroelectric thin-film) is then deposited. CMP and a bottom etch step removes excess ferroelectric material from the top of the structure and the bottom of memory holes 407. The portion of etch stop layer 404 exposed at the bottom of memory holes 407 is then removed. An oxide etch then creates vias that expose the global gate lines (e.g., global gate line 402) underlying memory holes 407. The resulting structure (vertical section) is shown in FIG. 4f.

An adhesion/barrier layer of titanium nitride (TiN) 412 is then conformally deposited.

An etch step then removes the TiN material from the portion of memory holes 407. Other barrier layers (e.g., tungsten nitride or tantalum nitride) may also be used. Memory holes 407 are then filled with gate electrode material 413, which may be a chemical vapor deposited tungsten (“CVD W”) or an n+ polysilicon (i.e., a heavily doped n-type polysilicon). Excess deposited material is then removed by CMP from the top of the structure. The resulting structure (vertical section) is shown in FIG. 4g.

Thereafter, top isolation layer 415 (e.g., silicon nitride) is provided over memory array 400. Top isolation layer 415 is then patterned and an etch step creates slots 414 (e.g., slots 414-1, 414-2, 414-3 and 414-4) through top isolation layer 415 and the alternating silicon nitride layers 406 and oxide layers 405. The resulting structure (vertical section) is shown in FIG. 4h(i). FIG. 4h(ii) shows a horizontal cross section of memory array 400 through one of nitride layers 406.

A wet etch step (e.g., hot phosphoric acid) is carried out to remove the silicon nitride layers 406. During this step, the silicon nitride material is removed from the exposed surfaces of silicon nitride layers 406 in the sidewalls of slots 414. A further etch step removes exposed portions of channel polysilicon 409 and gate oxide 410. A layer of n+ polysilicon layer 420 is then deposited and annealed. TiN layer 418 and tungsten 419 are then deposited successively to fill the voids left over from removing the silicon nitride. Excess n+ polysilicon, TiN and tungsten materials are removed from the top of the structure and the sidewalls of slots 414. The resulting structure is shown in vertical and horizontal cross sections in FIGS. 4i(i) and 4i(ii), respectively. In FIG. 4i(i), the resulting structure is magnified in inset where the top two silicon nitride layers 406 (i.e., silicon nitride layers 406-n and 406-(n−1)) have been removed. As shown in the inset, in each of the silicon nitride layer, (a) n+ polysilicon layer 420 forms pockets in channel polysilicon layer 409 and gate oxide layer 410 after thermal anneal diffusion, (b) TiN layer 418 lines the outside of n+ layer 420, and (c) tungsten layer 419 fills the remainder of the voids. The pockets of n+ polysilicon layer 420 become drain and source regions of an MRS transistor. TiN layers 418 and tungsten layers 419 become source or drain electrodes 423.

In some embodiments, silicon nitride layers 406 is not completely removed. As etching of silicon nitride layers 406 proceeds from the sidewalls of slots 414, so that a strip of silicon nitride divides and electrically the resulting source or drain terminals isolates on opposite sides of each memory hole. In this manner, each memory hole now provides two vertical 3-D FeFET strings, as the n+ polysilicon pockets on opposite sides of each silicon nitride layer of each memory hole form separate drain or source regions. This alternative embodiment is illustrated in the structure is shown in vertical and horizontal cross sections in FIGS. 4j(i) and 4j(ii), respectively. As shown in FIG. 4j(ii), silicon nitride layers 421, which is left over from the incomplete removal of silicon nitride layers 406 provide separate sets 423L and 423R of drain or source electrodes.

Silicon oxide 422 is then deposited to fill slots 414. A CMP step removes excess silicon oxide from the top of memory array 400. The resulting structure in vertical and horizontal cross sections are shown in FIGS. 4k(i) and 4k(ii), respectively, for the embodiment of FIGS. 4i(i) and 4i(ii). Likewise, the resulting structure in vertical and horizontal cross sections are shown in FIGS. 4l(i) and 4l(ii), respectively, for the embodiment of FIGS. 4j(i) and 4j(ii).

Connections to the drain or source electrodes 423 (or 423L and 423R, in the alternative embodiment) can be made using the staircase configuration used in 3-D NAND non-volatile memory arrays. FIG. 5 shows memory array 400 provided electrical contacts or connections to drain or source electrodes 423 via staircase structures on both sides of memory array 400 and contacts or connections to gate electrodes 413 using the bottom global gates (e.g., global gate 402). The staircase configuration and associated fabrication methods are known to those of ordinary skill in the art.

In one embodiment, the polarization switching voltages are ±1.5 volts across the ferroelectric capacitor layer of the MRS, for “1” and “0” states, respectively. During a programming or an erase operation, the voltage across the ferroelectric layer is roughly half of the gate-to-source voltage (VGS) of the MRS. Thus, programming of the MRS may be achieved using a programming voltage VPGM Of 6-7 volts at the gate electrode. Table 1 shows the voltage biases for MRS transistors in memory array 400 during a programming operation:

TABLE 1 Gate Drain Source MFIS TYPE Voltage Voltage Voltage Selected cell VPGM 0.0 0.0 Selected Gate, VPGM ⅔ VPGM ⅔ VPGM non-selected source or drain Non-selected ⅓ VPGM 0.0 0.0 gate, selected drain or source Non-selected ⅓ VPGM ⅔ VPGM ⅔ VPGM gate, non-selected drain or source

As shown in Table 1, program disturb is avoided in the non-selected MRS transistors because in each case, the magnitude of half gate-to-source voltage (VGS) is less than ⅓ VPGM, which is by design less than the polarization switching voltage for state “0”.

Similarly, an erase operation on an MFIS transistor may be achieved using an erase voltage VERA of 6-7 volts at the gate electrode. Table 2 shows the voltage biases for MRS transistors in memory array 400 during an erase operation:

TABLE 2 Gate Drain Source MFIS TYPE Voltage Voltage Voltage Selected cell 0.0 VERA VERA Selected Gate, 0.0 ⅓ VERA ⅓ VERA non-selected source or drain Non-selected ⅔ VERA VERA VERA gate, selected drain or source Non-selected ⅔ VERA VERA VERA gate, non-selected drain or source

As shown Table 2, erase disturb is avoided in the non-selected MRS transistors because in each case, the magnitude of half the gate-to-source voltage (VGS) are less than ⅓ VERA, which is by design less than the polarization switching voltage for state “1”.

A read operation may be achieved using a read voltage VREAD of 0.0-0.5 volts at the gate electrode and drain voltage VDD at 0.5-2.0 volts. Table 3 shows the voltage biases for MRS transistors in memory array 400 during a read operation:

TABLE 3 Gate Drain Source MFIS TYPE Voltage Voltage Voltage Selected cell VREAD VDD 0.0 Selected Gate, VREAD 0.0 0.0 non-selected source or drain Non-selected 0.0 or negative VDD 0 gate, selected drain or source Non-selected 0.0 or 1.0 negative 0.0 0.0 gate, non-selected drain or source

As shown Table 3, MRS transistors not on the same word line (i.e., non-selected gate electrodes) are provided a gate voltage of 0.0 volts or less, which results in a very low current drawn in these transistors.

FIGS. 6a-6j illustrate an exemplary fabrication process for memory array 600, in accordance with one embodiment of the present invention. Unlike memory array 400, the gate electrodes of the MRS transistors in memory array 600 are not connected by a network of global gate lines formed underneath the memory array. Instead, as shown in vertical section FIG. 6a, oxide layer 603 (e.g., silicon oxide) and bottom etch stop layer 604 (e.g., silicon nitride) are deposited in succession over a planar surface of semiconductor substrate 601. Etch stop layer 604 may be patterned, as shown, and embedded in oxide layer 603. Then, as shown in vertical section in FIG. 6b, alternating layers of silicon oxide layers 605 and silicon nitride layers 606 are deposited, numbered herein as silicon oxide layers 605-1, . . . , and 605-n, and silicon nitride layers 606-1, . . . , 606-n, respectively. An array of memory holes 607 (e.g., memory holes 607-1, 607-2 and 607-3) are then etched through the alternating layers of silicon oxide layers 605 and silicon nitride layers 606 down to etch stop layer 604, as shown in vertical section in FIG. 6c(i). FIG. 6c(ii) shows in horizontal cross section through one of silicon nitride layers 606, showing memory holes 607-1 to 607-9 of memory array 600 at this step of formation.

Polysilicon layer 609 is then conformally deposited, followed by deposition of thin gate oxide layer 610. Polysilicon 609 may be deposited as amorphous silicon and annealed at 850° C. for 2 hours to crystallize. Ferroelectric layer 611 (e.g., a Si-doped or Zr-doped Hf1−XSixOy, HfxZr1−xOy ferroelectric thin-film) is then deposited. The resulting structure (vertical section) is shown in FIG. 6d.

An adhesion/barrier layer of titanium nitride (TiN) 612 is then conformally deposited. Memory holes 607 are then filled with gate electrode material 613, which may be a CVD W or an n+ polysilicon. A CMP step removes excess gate oxide material 613 from the top of memory array 600. The resulting structure (vertical section) is shown in FIG. 6e.

Thereafter, top isolation layer 615 (e.g., silicon nitride) is provided over memory array 600. Top isolation layer 615 is then patterned and an etch step creates slots 614 (e.g., slots 614-1, 614-2, 614-3 and 614-4) through top isolation layer 615, TiN layer 612, ferroelectric layer 611, gate oxide layer 610, channel polysilicon layer 609 and the alternating silicon nitride layers 606 and oxide layers 605. The resulting structure (vertical section) is shown in FIG. 6f(i). FIG. 6f(ii) shows a horizontal cross section of memory array 600 through one of nitride layers 606.

An etch step (hot phosphoric acid) is carried out to remove the silicon nitride layers 606. During this step, the silicon nitride material is removed from the exposed surfaces of silicon nitride layers 606 in the sidewalls of slots 614. A further etch step removes exposed portions of channel polysilicon 609 and gate oxide 610. A layer of n+ polysilicon layer 620 is then deposited and annealed. TiN layer 618 and tungsten 619 are then deposited successively to fill the voids left over from removing the silicon nitride. Excess n+ polysilicon, TiN and tungsten materials are removed from the top of the structure and the sidewalls of slots 614, in substantially. These steps are provided in substantially the same manner as discussed above with respect to vertical and horizontal cross sections in FIGS. 4i(i) and 4i(ii), respectively. The pockets of n+ polysilicon layer 620 become drain and source regions of an MRS transistor. TiN layers 618 and tungsten layers 619 become source or drain electrodes 623. Silicon oxide 622 is then deposited to fill slots 614. A CMP step removes excess silicon oxide from the top of memory array 600. The resulting structure in vertical and horizontal cross sections are shown in FIGS. 6g(i) and 6g(ii), respectively,

As discussed above with respect to FIGS. 4j(i) and 4j(ii), in some embodiments, silicon nitride layers 606 is not completely removed. As etching of silicon nitride layers 606 proceeds from the sidewalls of slots 614, so that a strip of silicon nitride divides and electrically the resulting source or drain terminals isolates on opposite sides of each memory hole. In this manner, each memory hole now provides two vertical 3-D FeFET strings, as the n+ polysilicon pockets on opposite sides of each silicon nitride layer of each memory hole form separate drain or source regions. This alternative embodiment is illustrated in the structure is shown in vertical and horizontal cross sections in FIGS. 6h(i) and 6h(ii), respectively. As shown in FIG. 6h(ii), silicon nitride layers 621, which is left over from the incomplete removal of silicon nitride layers 606 provide separate sets 623L and 623R of drain or source electrodes.

Silicon oxide layer 618 is deposited over top isolation layer 615, filling any gap on memory array 600 and planarized by a CMP step. Thereafter, silicon oxide layer 618 is patterned. An etch step creates via through silicon oxide layer 618 and top isolation layer 615 to expose gate electrode material 613. Metallic conductor (e.g., TiN and tungsten plug) 616 is then provided to fill the vias. A CMP step planarizes the surface of memory array 600. The resulting structure is shown in vertical section in FIG. 6i. Thereafter, top global gates (e.g., global gate 617) are provided above silicon oxide layer 618 to electrically connect gate electrodes 613 through the conductor-filled vias, as shown in FIG. 6j.

FIGS. 7a-7g illustrate an exemplary fabrication process for memory array 700, in accordance with one embodiment of the present invention. Unlike the MRS transistors of memory arrays 400 and 600 discussed above, an MFIS transistor of memory array 700 includes an additional charge-storage layer between the gate oxide layer and the ferroelectric layer.

FIG. 7a shows memory array 700 after (i) a network of global gate lines (e.g., tungsten), including global gate line 702, are formed over semiconductor substrate 701, which may be a semiconductor wafer, and (ii) oxide layer 703 (e.g., silicon oxide) and bottom etch stop layer 704 (e.g., n+ polysilicon) are deposited over the global gate lines; and (iii) alternating layers of silicon oxide layers 705 and n+ polysilicon 706 are deposited, numbered herein as silicon oxide layers 705-1, . . . , and 705-n, and n+ polysilicon layers 706-1, . . . , 706-n, respectively. The structure of FIG. 7a may be formed using substantially the same steps as those described above with respect to FIGS. 4a-4c, except conductive n+ polysilicon material replaces silicon nitride in the alternating layers. Using n+ polysilicon is an option for drain and source electrodes, although n+ polysilicon has a higher resistivity than metal. However, if metal is selected for drain and source electrodes, a metal replacement step (see, e.g., FIGS. 4i and 4j for memory array 400 and FIGS. 6f and 6g for memory array 600) may be required.

Slots 714 may be created at this time, instead of after the MRS transistors have been substantially formed (see, e.g., FIGS. 4h(i) and 6f(i), which creating slots 414 of memory array 400 and slots 614 of memory array 600), because the metal replacement step is not necessary. (The metal replacement steps access the silicon nitride layers through the slots.) Slots 714, which divide memory array 700 into sections 708, may then be filled with oxide, as shown in vertical and horizontal sections in FIGS. 7b(i) and 7b(ii).

Memory holes 707 (e.g., memory holes 407-1, 407-2 and 407-3) are then etched through the alternating layers of silicon oxide layers 705 and n+ polysilicon layers 706 down to etch stop layer 704, as shown in vertical section in FIG. 7c(i). FIG. 7c(ii) shows in horizontal cross section through one of n+ polysilicon layers 706, showing memory holes 707-1 to 707-9 of memory array 700 at this step of formation.

Polysilicon layer 709 is then conformally deposited, followed by deposition of thin gate oxide layer 710. Polysilicon 709 may be deposited as amorphous silicon and annealed at 850° C. for 2 hours to crystallize. Protective layer 708 may then be deposited over gate oxide layer 710. A spacer etch is then carried out to remove any deposited polysilicon and gate oxide from the bottom of memory holes 707. A CMP step may be carried out to remove materials of protective layer 708, gate oxide 710, and polysilicon layer 709 from the top of the structure. The resulting structure (i.e., memory array 700 at this step of formation) is shown in vertical section in FIG. 7d.

Protective layer 708 is then removed. Thereafter, charge-trapping layer 733 is conformally deposited. An anisotropic etch then removes the charge-trapping material at the bottom of memory holes 707 to expose the underlying etch stop layer 704. The exposed portions of etch stop layer 704 and the portions of oxide layer 703 are removed in successive etching steps to create vias that expose the global gate lines underneath. The resulting structure is shown in vertical section in FIG. 7e.

Ferroelectric layer 711 (e.g., a Si-doped or Zr-doped Hf1−xSixOy, Hf1−xZrxOy ferroelectric thin-film) is then deposited. CMP and a bottom etch step removes excess ferroelectric material from the top of the structure and the bottom of memory holes 707. An adhesion/barrier layer of titanium nitride (TiN) 712 is then conformally deposited. An etch step then removes the TiN material from the portion of memory holes 707. Memory holes 707 are then filled with gate electrode material 713, which may be a CVD W or an n+ polysilicon. Excess deposited material is then removed by CMP from the top of the structure. The resulting structure (vertical section) is shown in FIG. 7f.

Thereafter, top isolation layer 715 (e.g., silicon nitride) is provided over memory array 700. The resulting structure (vertical section) is shown in FIG. 7g.

FIGS. 8a-8j illustrate an exemplary fabrication process for memory array 800, in accordance with one embodiment of the present invention. Unlike the MRS transistors of memory arrays 400, 600 and 700 discussed above, an MRS transistor of memory array 800 has a unit cell in which the source and drain lines are fabricated out of the same layer of semiconductor material.

FIG. 8a shows memory array 800 after (i) a network of global gate lines (e.g., tungsten), including global gate line 802, are formed over semiconductor substrate 801, which may be a semiconductor wafer, and (ii) oxide layer 803 (e.g., silicon oxide) and bottom etch stop layer 804 (e.g., n+ polysilicon) are deposited over the global gate lines; and (iii) alternating layers of silicon oxide layers 805 and silicon nitride layers 806 are deposited, numbered herein as silicon oxide layers 805-1, . . . , and 805-n, and silicon nitride layers 806-1, . . . , 806-n, respectively. (In FIG. 8a, semiconductor substrate 801 and global gate layer 802 are omitted; semiconductor substrate 801 and global gate layer 802 have substantially the same structure, and are formed in substantially the same manner, as semiconductor substrate 701 and global gate layer 702 discussed above.) The structure of FIG. 8a may be formed using substantially the same steps as those described above with respect to FIGS. 4a-4c Memory holes 807 (e.g., memory holes 407-1, 407-2 and 407-3) are then etched through the alternating layers of silicon oxide layers 805 and silicon nitride layers 806 down to etch stop layer 804, as shown in vertical section in FIG. 8b(i). FIG. 8b(ii) shows in horizontal cross section through one of silicon nitride layers 706, showing memory holes 807-1 to 807-9 of memory array 800 at this step of formation.

Thereafter, a silicon nitride recess etch using, for example, hot phosphoric acid, is performed to recess silicon nitride layers 806 from exposed sidewalls of memory holes 807, as shown in FIG. 8c. Polysilicon layer 809 (e.g., p−-type) is then deposited to fill the recesses created by the silicon nitride recess etch. An anisotropic etch step removes the excess polysilicon material from memory holes 809, including the sidewalls, exposing etch stop layer 804. Excess polysilicon material may also be removed from top oxide layer 805-n.

The resulting structure is shown in FIG. 8d(i). FIG. 8d(ii) shows a horizontal section through one of silicon nitride layers 806. Polysilicon 709 may be deposited as amorphous silicon and annealed at 850° C. for 2 hours to crystallize.

Thin gate oxide layer 810 and ferroelectric layer 811 (e.g., a Si-doped or Zr-doped Hf1−xSixOy, Hf1−xZrxOy ferroelectric thin-film) are then conformally deposited into memory holes 807. A CMP step removes excess gate oxide and ferroelectric materials from the top of the structure. An adhesion/barrier layer of titanium nitride (TiN) 812 is then conformally deposited. The resulting structure is shown in FIG. 8e.

Gate electrode material 813, which may be a CVD W or an n+ polysilicon, is then deposited to fill the remainder of memory holes 807. Excess deposited gate electrode and TiN materials are then removed by CMP from the top of memory array 800. The resulting structure (vertical section) is shown in FIG. 8f. Thereafter, top isolation layer 815 (e.g., silicon nitride) is provided over memory array 800. Slots 814 are then cut. The resulting structure is shown in FIG. 8g(i). A horizontal structure through one of the silicon nitride-channel polysilicon layers is shown in FIG. 8g(ii).

A hot phosphoric acid etch recesses silicon nitride layers 806 from the sidewalls of slots 814, as shown in FIG. 8h(i). A horizontal structure through one of the silicon nitride-channel polysilicon layers is shown in FIG. 8g(ii). Thereafter, n+ polysilicon layer 818 is deposited by diffusion conformally to line the layers of pockets from recessing silicon nitride layers 805. If necessary, an anneal step provides crystallization and activates the dopants. Thereafter, the remaining of the layers of pockets are lined by adhesive layer 817 (e.g., TiN) and filled by tungsten layer 819. Excess TiN, tungsten and n+ polysilicon materials are then removed from the sidewalls and at the bottoms of slots 814 and from the top of structure. The pockets in each slot is designated to become either source regions 821 or drain regions 822, with adjacent slots being assigned the opposite types. The resulting structure is shown in FIG. 8i(i). A horizontal structure through one of the pocket layers is shown in FIG. 8i(ii). Portion 820 of the structure of FIG. 8i(i) is enlarged in FIG. 8i(iii).

Slots 814 are then filled with by insulator 825 (e.g., a silicon oxide), which also provided as a top gap fill layer. After planarization using CMP, gate line contacts 826 are through top gap fill layer 825 and top isolation layer 813. One or more layers 827 of conductors (“gate lines”) may be provided to electrically connect gate line contacts 826. The resulting structure is shown in FIG. 8j.

The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. For example, with respect to FIGS. 7a-7g, the locations of ferroelectric layer 711 and charge-trapping layer 733 can be swapped, and an additional blocking oxide layer can be inserted between titanium nitride layer 712 and ferroelectric layer 711. The present invention is set forth in the accompanying drawings.

Claims

1. A memory string formed above a planar surface of substrate, comprising:

a gate electrode extending lengthwise along a vertical direction relative to the planar surface,
a ferroelectric layer provided over at least a portion of the gate electrode along a horizontal direction and extending lengthwise along the vertical direction;
a gate oxide layer provided over at least a portion of the ferroelectric layer along the horizontal direction and extending lengthwise along the vertical direction;
a plurality of semiconductor structure provided along the vertical direction adjacent the gate oxide layer, each semiconductor structure comprises (i) a first semiconductor material of a first conductivity type; and (ii) second and third semiconductor materials electrically being isolated from each other and each being coplanar with and adjacent the first semiconductor material, the second and third semiconductor materials each being of a second conductivity type different from the first conductivity type, wherein the gate electrode, the ferroelectric layer, the gate oxide layer and the semiconductor structure from a storage transistor of the memory string, and wherein the first, second and third semiconductor materials forming the channel, source and drain regions of the storage transistor.

2. The memory string of claim 1, further comprising a barrier layer provided between the gate electrode and the ferroelectric layer.

3. The memory string of claim 2, wherein the barrier layer comprises titanium nitride, tungsten nitride or tantalum nitride.

4. The memory string of claim 1, wherein the gate electrode comprises tungsten or a heavily doped semiconductor.

5. The memory string of claim 1, further comprising a conductor adjacent to each of the second and third semiconductor materials of each semiconductor structure.

6. The memory string of claim 5, wherein the conductor comprises tungsten, a metallic adhesive layer, or a combination thereof.

7. The memory string of claim 5, wherein the drain or source region each comprise n+ polysilicon.

8. The memory string of claim 1, wherein the memory string is one of a plurality of memory strings in a memory array, wherein the memory array comprises a staircase configuration providing electrical contacts to each of the source or drain electrodes.

9. The memory string of claim 1, wherein the memory string is one of a plurality of memory strings in a memory array, wherein the memory array comprises a network of global word line conductors each connecting the gate electrodes of a selected group of the memory strings.

10. The memory string of claim 9, wherein the network of global word line conductors is provided above the memory strings.

11. The memory string of claim 1, wherein the ferroelectric layer comprises a HfO2 ferroelectric material.

12. The memory string of claim 11, wherein the ferroelectric layer is 5.0-30.0 nm thick, preferably 8.0-20.0 nm thick.

13. The memory string of claim 11, wherein the ferroelectric layer comprises a zirconium-doped hafnium silicon oxide.

14. The memory string of claim 13, wherein the zirconium-doped hafnium silicon oxide has a zirconium content of 40-60%, preferably 45-55%.

15. The memory string of claim 13, wherein the zirconium-doped hafnium silicon oxide comprises HfxZr1−xOy ferroelectric thin-films, where x ranges between 0.4 and 0.6, preferably between 0.45 and 0.55, and y ranges between 1.8 and 2.2, preferably between 1.9 to 2.1.

16. The memory string of claim 13, wherein the zirconium-doped hafnium silicon oxide is prepared by depositing HfO2 and ZrO2 using an ALD layer-by-layer lamination step.

17. The memory string of claim 11, wherein the ferroelectric layer comprises a silicon-doped hafnium silicon oxide.

18. The memory string of claim 17, wherein the silicon-doped hafnium silicon oxide has a silicon content of 2.0-5.0%, preferably 2.5-4.5%.

19. The memory string of claim 17, wherein the silicon-doped hafnium silicon oxide comprises HfxSi1−xOy ferroelectric thin-films, where x ranges from 0.02 to 0.05, preferably between 0.025 and 0.04, and y ranges from 1.8 to 2.2, preferably between 1.9 and 2.1.

20. The memory string of claim 17, wherein the silicon-doped hafnium silicon oxide is prepared by depositing HfO2 and SiO2 using an ALD layer-by-layer lamination step.

21. The memory string of claim 1, further comprising a charge-trapping layer between the gate oxide layer and the ferroelectric layer or between the ferroelectric layer and a barrier layer adjacent the gate electrode.

22. The memory string of claim 1, wherein the barrier layer comprises titanium nitride.

23. A process for fabricating a memory structure above a planar surface of a substrate, comprising:

forming a bottom isolation layer on the planar surface;
forming and patterning an etch stop layer above the bottom isolation layer,
forming a predetermined number of alternating layers of intermediate isolation material and a first dielectric material;
cutting a plurality of shafts from the top of the alternating layers of the intermediate isolation material and the first dielectric material down to the etch stop layer;
recessing each of the layers of the first dielectric material to create a first plurality of pockets;
filling each of the pockets with a first semiconductor material of a first conductivity type;
forming conformally a gate oxide layer over the sidewalls of the shafts, the gate oxide material being in contact with the first semiconductor material in the pockets along the sidewalls of the shafts;
forming conformally a ferroelectric layer over the gate oxide layer,
filling the shafts of a conductive gate material to form a gate electrode;
forming a plurality of slots through the alternating layers of intermediate isolation material and the first dielectric material between the filled shafts;
recessing the first dielectric material exposed along the sidewalls of the slots to form a second plurality of pockets and exposing in each pocket at least a portion of the first semiconductor material; and
forming conformally a second semiconductor material of a second conductivity type on the inside walls of the second plurality of pockets.

24. The process of claim 23, further comprising forming conformally an adhesion conductor layer between the conductive gate material and the ferroelectric layer.

25. The process of claim 23, further comprising filling the second plurality of pockets with a metallic conductor.

26. The process of claim 25, wherein the conductor comprises tungsten, a metallic adhesive layer, or a combination thereof.

27. The process of claim 23, further comprising forming a barrier layer between the gate electrode and the ferroelectric layer.

28. The process of claim 27, wherein the barrier layer comprises titanium nitride, tungsten nitride or tantalum nitride.

29. The process of claim 23, wherein the gate electrode comprises tungsten or a heavily doped semiconductor.

30. The process of claim 23, wherein the ferroelectric layer comprises a HfO2 ferroelectric material.

31. The process of claim 30, wherein the ferroelectric layer is 5.0-30.0 nm thick, preferably 8.0-20.0 nm thick.

32. The process of claim 30, wherein the ferroelectric layer comprises a zirconium-doped hafnium silicon oxide.

33. The process of claim 32, wherein the zirconium-doped hafnium silicon oxide has a zirconium content of 40-60%, preferably 45-55%.

34. The process of claim 32, wherein the zirconium-doped hafnium silicon oxide comprises HfxZr1−xOy ferroelectric thin-films, where x ranges between 0.4 and 0.6, preferably between 0.45 and 0.55, and y ranges between 1.8 and 2.2, preferably between 1.9 to 2.1.

35. The process of claim 32, wherein the zirconium-doped hafnium silicon oxide is prepared by depositing HfO2 and ZrO2 using an ALD layer-by-layer lamination step.

36. The process of claim 30, wherein the ferroelectric layer comprises a silicon-doped hafnium silicon oxide.

37. The process of claim 36, wherein the silicon-doped hafnium silicon oxide has a silicon content of 2.0-5.0%, preferably 2.5-4.5%.

38. The process of claim 36, wherein the silicon-doped hafnium silicon oxide comprises HfxSi1−xOy ferroelectric thin-films, where x ranges from 0.02 to 0.05, preferably between 0.025 and 0.04, and y ranges from 1.8 to 2.2, preferably between 1.9 and 2.1.

39. The process of claim 36, wherein the silicon-doped hafnium silicon oxide is prepared by depositing HfO2 and SiO2 using an ALD layer-by-layer lamination step.

40. The process of claim 23, further comprising forming a charge-trapping layer between the gate oxide layer and the ferroelectric layer or between the ferroelectric layer and a barrier layer adjacent the gate electrode.

Patent History
Publication number: 20200357822
Type: Application
Filed: Jan 2, 2020
Publication Date: Nov 12, 2020
Inventor: Yung-Tin Chen (Santa Clara, CA)
Application Number: 16/733,102
Classifications
International Classification: H01L 27/11597 (20060101); G11C 11/22 (20060101); H01L 27/11587 (20060101);