DOUBLE SYNCHRONOUS UNIFIED VIRTUAL OSCILLATOR CONTROL FOR GRID-FORMING AND GRID-FOLLOWING POWER ELECTRONIC CONVERTERS
A power electronic converter can utilize exemplary double synchronous unified virtual oscillator control (DSUVOC) logic or circuitry to convert direct current to alternating current that is input into a power grid. An exemplary DSUVOC controller of the present disclosure includes a double synchronous space vector oscillator component, a sequence extraction component, a fault detection component, a pre-synchronization component, a virtual impedance component, a terminal voltage compensation component, and/or an active damping component, wherein the double synchronous unified virtual oscillator controller is capable of controlling a grid following or a grid forming power electronic converter enabling synchronization and fault ride-through under both balanced and unbalanced conditions.
This application claims priority to co-pending U.S. provisional application entitled, “Universal Oscillator Control for Grid Following and Grid Forming Converters,” having Ser. No. 62/972,791, filed Feb. 11, 2020, which is entirely incorporated herein by reference.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENTThis invention was made with government support under Grant No. EEC-0812121 awarded by the National Science Foundation. The government has certain rights in the invention.
BACKGROUNDWith the increasing penetration of distributed generation resources into the power system, coordinated control of low-inertia systems has garnered significant research efforts [1]. Grid-forming (GFM) converters (GFMCs) are considered to be a key enabling technology for the future grid with reduced inertia [2]. The prevalent and most widely investigated control strategies for GFMCs have been developed based on mimicking the characteristics of synchronous machines by voltage source converters (VSCs). Droop control [3], power synchronization control (PSC) [4], synchronverters [5], virtual synchronous machines (VSM/VISMA) [6], and synchronous power controllers (SPC) [7] are examples of emulation based GFM control methods.
However, power electronic converters can provide minimal inertial response and are typically designed with very limited over-current capability. The synchronization among droop-based resources has been studied using phase-coupled oscillator models which are well defined only in the near synchronous time scale, and therefore, provide good approximation of dynamic behavior only in networks with significant inertia.
To circumvent phasor based approximate modelling and design, a class of nonlinear control methods has been proposed which leverage the well established theoretical results on synchronization in oscillator networks. In papers by Johnson et al. (B. B. Johnson, S. V. Dhople, A. O. Hamadeh, and P. T. Krein, “Synchronization of Parallel Single-Phase Inverters With Virtual Oscillator Control,” IEEE Transactions on Power Electronics, vol. 29, no. 11, pp. 6124-6138, November 2014 and B. B. Johnson, M. Sinha, N. G. Ainsworth, F. Dorfler, and S. V. Dhople, “Synthesizing Virtual Oscillators to Control Islanded Inverters,” IEEE Transactions on Power Electronics, vol. 31, no. 8, pp. 6002-6015, August 2016) [8], [9], VSCs are controlled to emulate the dynamics of weakly nonlinear limit-cycle oscillators, such as the dead-zone oscillator and the Van der Pol oscillator. These class of so-called virtual oscillator control (VOC) methods incorporate a droop like terminal response implicitly embedded in their nonlinear dynamics. However, VOC requires a design trade-off between transient performance and harmonic distortion, specially 3rd harmonic, in the output voltage.
Moreover, VOC is non-ideal for three-phase application and, for explicit real and reactive power dispatch, additional compensation loops with distinct time-scale separation are required [10]. Another oscillator based method, well-suited for three phase implementation, was recently proposed which enables explicit power and voltage reference dispatch [11]-[13]. This so-called dispatchable virtual oscillator control (dVOC) utilizes super-critical Andronov-Hopf bifurcation which leads to a unique and stable limit-cycle behavior [14]. The theoretical development of dVOC was inspired by consensus in multi-agent networks, and therefore, the controller design was presented in a network-oriented top-down approach [11]. A different approach for the controller parameter selection based on the voltage and current capacity of the power electronic converter was presented in a paper by Lu, et al. (M. Lu, S. Dutta, V. Purba, S. Dhople, and B. Johnson, “A Grid-compatible Virtual Oscillator Controller: Analysis and Design,” in 2019 IEEE Energy Conversion Congress and Exposition (ECCE), 2019) [13].
Overall, VOC and dVOC have been developed for grid forming (GFM) operation of VSCs utilizing the almost global asymptotic synchronization guarantee in nonlinear oscillator networks. The superior synchronization property of nonlinear oscillators has not been explored for grid following (GFL) operation. Despite the growing interest in GFM converters, GFL converters remain predominant and are essential for a class of applications such as point-of-load (POL) converters and active-front-end rectifiers.
A major constraint of oscillator based methods arises from the lack of fault ride-through capability. The capability to ride-through AC/grid faults with defined fault current contribution while operating within safe current limits allowable by the converter hardware is essential for stable operation and protection coordination in power electronics dominated electrical grids. However, no compatible fault ride-through strategy has been reported for oscillator based GFM controllers, which severely limits practical applications. Moreover, fault-handling in GFM converters, even in conventional droop based VSCs, remains an open research problem till date. In a PSC based converter, a backup PLL is run for fault management; during grid faults, the converter control system switches from PSC to PLL based current controlled operation [4]. In droop based GFM converters, over-current protection may be achieved by directly limiting the reference to the inner current control loop; but this causes wind-up in the outer droop control loops which eventually leads to a loss of synchronization and instability [15]. As an alternative, switching to PLL based grid-following operation during faults has been proposed in [16], [17], and dynamic virtual impedance control and adaptive droop control during faults were proposed in [18]. Fault ride-through becomes even more challenging under asymmetric AC faults. Under such conditions, a complex PLL structure, namely, decoupled double synchronous reference frame (DDSRF) PLL, is required to retain synchronization with the AC grid [19]. However, PLLs lead to sub-synchronous oscillations or even instability under weak grid conditions [4], [20]. No PLL-less grid synchronization method under asymmetric grid conditions has been reported for either GFL or GFM converters till date. Furthermore, a lack of robust synchronization capability under widely varying grid impedance conditions requires control parameter tuning under variable grid conditions, which increases the cost of development, deployment, and maintenance of grid tied power electronic converters.
Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.
The present disclosure describes various embodiments of systems, apparatuses, and methods for a double synchronous unified virtual oscillator controller (DSUVOC) of a power electronic converter. In accordance with embodiments of the present disclosure, a double synchronous unified virtual oscillator controller (DSUVOC) enables phase-locked-loop (PLL)-less grid synchronization and ride-through in grid following and grid forming power electronic converters under nominal conditions as well as under both symmetric (balanced) and asymmetric (unbalanced) AC fault conditions.
In a grid following power electronic converter, an exemplary DSUVOC achieves grid connected operation with bidirectional power flow control and DC bus voltage regulation. Grid forming (GFM) operation is achieved in both grid connected and islanded modes with seamless transition between the two. For both GFL and GFM modes of operation, an exemplary DSUVOC enables fast over-current limiting and simultaneous synchronization to the positive and negative sequence symmetrical components of the AC network/grid voltage without any phase-locked-loop (PLL) circuitry. This enables ride-through of balanced/symmetrical and unbalanced/asymmetrical faults without the need for switching to a separate set of back-up controller under fault conditions. The PLL-ness nature of the DSUVOC enables robust synchronization of power electronic converters under widely varying grid strengths ranging from strong to ultra-weak grids using identical control parameters. The GFL and GFM operation, fault ride-through response, and robust operation under variable grid conditions of an exemplary DSUVOC are validated through hardware experiments in a hybrid AC-DC microgrid.
Space vector notations are used in subsequent analysis and descriptions of an exemplary DSUVOC controller. The space vector representation of a set of three-phase quantities, such as [uu uv uw]T, in the stationary αβ reference frame is obtained using magnitude-invariant Clarke transformation. The corresponding space vector is denoted as u=[uα uβ]T ↔u=uα +juβ, where j=√{square root over (−1)} denotes the imaginary unit. The column vector u and the complex representation u of space vectors are used interchangeably in the rest of the present disclosure. A subscript of ‘0’, such as in u0 or u0, denote the reference/set-point or nominal value of the respective state/variable. Positive and negative sequence components correspond to the symmetrical components of a three-phase quantity. A ‘+’ or ‘−’ in the subscript represents the +ve or −ve sequence component of the corresponding variable; the +ve and −ve sequence components of u are denoted as u+=[uα+ uβ+]T ↔u+=uα++juβ+ and u−=[uα− uβ−]T ↔u−=uα−+juβ−. Similarly, the +ve and −ve sequence components of u0 are denoted as u0+=[uα0+ uβ0+]T↔u0+=uα0++juβ0+ and u0−=[uα0− uβ0−]T u0−=uα0−+juβ0−. The magnitude of a vector is denoted as e.g., û=∥u∥=(uα2+uβ2)0.5.
A three-phase power electronic converter using DSUVOC is shown in
The double synchronous space vector oscillator component, shown in
Here, N=1 or N=3 is used for single-phase or three-phase applications, respectively. The choice of how the double sequence current reference is generated is not unique and different selection rules may be used to achieve various control objectives such as constant real power flow, constant reactive power flow, balanced three-phase current injection, etc. Note that under symmetric/balanced grid condition v−=0 and hence a balanced three-phase current reference, i.e., i0−=0, is obtained.
The double sequence vector limiter (DSVL) is used to limit the current reference below the maximum current value allowable for the power electronic converter hardware. For i0+≠0, i0−≠0, the two sequence vectors rotate in an opposite direction and lead to a resultant rotating vector in the stationary frame with a time-varying magnitude. Therefore, to ensure safe converter operation, the current references of all three phases must be checked and limited within safe values. In the DSVL, the three-phase current references [iu0, iv0, iw0] are determined as:
Next, the instantaneous maximum phase current reference is determined as i0max=max{iu0, iv0, iw0}. The saturated current reference vectors are then obtained as
i0+=ksati0+; i0−=ksati0− (3)
Here, ksat=lm/i0max where lm denotes the maximum current allowable by the converter hardware.
The positive and negative sequence space vector oscillators (SVO) serve as the synchronizing units for positive and negative sequence components, respectively. The implementation structure of the +ve and −ve sequence SVOs are shown in
{dot over (v)}+=jω0+
{dot over (v)}−=jω0+
Here, ω0 denotes the nominal frequency; {circumflex over (v)}0+ and {circumflex over (v)}0− denote the peak values of the +ve sequence and −ve sequence voltage references v0+ and v0−, respectively; η+>0 and η−>0 are the synchronization gains; μ+>0 and μ−>0 are the voltage magnitude correction gains; and ϕ∈
is chosen for desired droop relation. For instance,
gives a real power versus frequency and reactive power versus voltage droop response, whereas ϕ=0 leads to the opposite droop relation. To facilitate a smooth and seamless transition between normal operations and a fault ride-through operation, the SVO dynamics are adjusted through a mode transition signal xr generated by the fault detection (FD) block (see
where η0+ and η0− are the nominal synchronization gains and τf denotes the settling time.
Another alternative implementation of the space vector oscillators can be represented as:
{dot over (v)}+=jω0+
{dot over (v)}−=jω0+
In Equation (4a) and (4b), the error in the squares of the voltage vector magnitudes ({circumflex over (v)}0+2−∥v+∥2) and ({circumflex over (v)}0−2−∥v−∥2) are used in the magnitude correction terms, respectively, whereas in Equation (6a) and (6b), errors in the voltage vector magnitudes ({circumflex over (v)}0+−∥v+∥) and ({circumflex over (v)}0−−∥v−∥) are used, respectively. For brevity, in the following texts the analysis and design are shown using Equation (4a) and (4b). Similar analysis, design, and controller implementation can be achieved using Equation 6(a) and 6(b) as well.
From the converter output current i ↔[iα iβ]T, the sequence extraction (SE) block calculates the +ve and −ve sequence components i+↔[iα+ iβ+]T and i−↔[iα− iβ−]T as:
iα+=0.5(iα−(iβ⊥) (7a)
iβ+=0.5(iβ+iα⊥) (7b)
iα−=0.5(iα+iβ⊥) (7c)
iβ−=0.5(iβ−iα⊥) (7d)
where iα⊥ and iβ⊥ denote the T0/4 delayed versions of iα and iβ, respectively, and T0=2π/ω.
The fault detection (FD) subsystem may detect and latch a fault state due to overcurrent, i.e., max{iu, iv, iw}>lm, or due to unbalance in the grid voltage, i.e.,
where kuft denotes the maximum allowable unbalance factor. The unbalance factor is defined as the ratio of the −ve sequence component vg− to the +ve sequence component vg+ of the grid voltage vg. The fault signal xf is shown in
Under the normal mode of operation, xr=0 and the negative sequence SVO can be disabled. For ease of explanation of the synchronizing mechanism of the SVO, the normal operation is considered. Substituting Equation (1) into Equation (4a), the instantaneous voltage and frequency of the SVO output voltage are derived as:
where
Equation (8) reduces to:
For μ=0, Q=Q0 is achieved. For GFL operation, μ=0 is used. Therefore, accurate tracking of the reactive power reference is achieved. However, a real power droop response is observed for any deviation of the grid frequency from the nominal value, i.e., ω≠ω0. Integral compensation can be used to achieve accurate tracking of a real power reference. For ϕ=0 and μ=0, accurate tracking of the real power reference is achieved by the SVO dynamics, but integral compensation is required to obtain accurate tracking of the reactive power reference. For DC bus voltage regulation in a GFL application,
and μ=0 can be used where the real power set-point P0 is dynamically generated by applying a closed-loop compensator, such as a proportional-integral (PI) compensator, on the DC bus voltage error, which is shown in
For GFM operation μ≠0 is used. For μ≠0 and
the voltage and magnitude and frequency can be derived from Equation (9) as:
Accordingly, a real power versus frequency and reactive power versus voltage droop responses are obtained. For ϕ=0, opposite droop relations are obtained as:
In Equation (10a) and (11a), the droop response is obtained in terms of the square of the voltage vector magnitude due to SVO implementation following Equation (4a) and (4b). The droop response in terms of voltage vector magnitude, instead of its square, can be obtained with an SVO implementation following Equation (6a) and (6b).
There are two key purposes of virtual impedance, namely, harmonic compensation and the stabilization of SVOs. Non-ideal effects, such as dead-time, introduce harmonic distortion in va. Moreover, harmonic distortion in the network/grid voltage vg or nonlinear loads lead to undesired harmonic distortion in the output current. Contrarily, in certain applications, specifically in an islanded microgrid, harmonic current injection by the GFM converters may be desired to compensate for harmonic distortion in the network voltage. The converter output impedance or admittance can be selectively increased to very high values at the harmonic frequencies to achieve the desired harmonic compensation in converter output current or network voltage, respectively. In a power electronic converter, harmonic current suppression is achieved by virtual impedance as:
Here, Kh and ωB,h denote the desired impedance magnitude and the bandwidth of the resonant filter at harmonic frequency ωh, respectively. On the other hand, virtual resistance Rvir emulation is necessary to ensure dynamic stability of the SVOs. A virtual inductance Lvir may also be used in different applications where very fast over-current limiting is required under fault operation with a strong grid condition. A limited bandwidth of ωc in Equation (7) is used for the virtual resistance and inductance emulation. Further detail and design guidelines for Zv(s) can be found in a paper by Awal, et al. (M. A. Awal, H. Yu, I. Husain, W. Yu, and S. Lukic, “Selective Harmonic Current Rejection for Virtual Oscillator Controlled Grid-Forming Voltage Source Converters,” in IEEE Transactions on Power Electronics) [21].
In existing literature, the high frequency dynamics of the higher order input filters, such as LCL filters, of oscillator based VSCs have been completely ignored which may lead to undesired resonances in the high frequency range (hundreds of Hz to few kHz). The digital controller implementation delay and variation in network/grid impedance further aggravates the severity of such resonances and may even destabilize the system in extreme cases. In various embodiments, an exemplary DSUVOC includes an observer band active damping (OBAD) component that utilizes an observer to estimate the states of the LCL filter, and using the observer estimated states, active damping of the of high frequency resonances is achieved [22].
For the analysis and design of the observer based active damping, the slower dynamics of the SVOs and the selectively tuned dynamics of virtual impedance emulation can be ignored. The LCL filter is modelled as:
The system matrices A and B can be determined using the LCL filter parameters. A discrete observer is designed using the LCL filter model, in which the discrete observer is implemented as:
{circumflex over (x)}[k+1]=Aobs{circumflex over (x)}[k]+Bobsuobs[k];{circumflex over (x)}=[{circumflex over (l)}a{circumflex over (l)}g{circumflex over (v)}f]T;uobs=[vavgim]T (14)
where im=ia or im=ig can be used based on availability of feedback signal. The output of the OBAD block is calculated as vad=Rad({circumflex over (l)}a−{circumflex over (l)}g), where Rad denotes the active damping gain.
The power electronic converter can connect/disconnect to/from the network using a static-transfer-switch (STS). This process of synchronizing the converter output voltage with the grid voltage is termed as pre-synchronization. The pre-synchronization can be achieved by a first-order low-pass filter in the form of a virtual RL branch. A virtual current ips can be generated by the pre-synchronization block to estimate the current that would flow if the STS were closed. The virtual current is generated as:
The parameters can be chosen as Lps (La+Lg) and Rps≈Rvir. It is worth noting that exact knowledge of the LCL filter parameters are not required for the parameter selection. To illustrate the functionality, two distinct use-cases can be defined for the pre-synchronization component.
For GFM converters while serving local loads, the voltages across the STS need to be synchronized prior to closing the STS. In such scenarios, the virtual current ips is added to the actual converter output current and the resultant total current is used as feedback to the SVOs. The virtual current ips gives an estimate of the current that would flow between the power electronic converter and the network at the PoC if the STS were closed. Due to the virtual current ips feedback, SVOs adjust the oscillator voltage to minimize the virtual real and reactive power flow. When the amplitude of the virtual current |ips| stabilizes, the STS can be closed safely.
For GFL operation, the STS can be closed before the switching of the power devices are initiated. For instance, during start-up of an active-front-end rectifier, the DC bus may be charged by using the switch network as an uncontrolled diode bridge. Meanwhile, the SVOs can be synchronized with the measured voltage vg using the pre-synchronization filter. Once |ips| stabilizes, the DC bus voltage control loop and the switching of the power devices can be initialized without large transients. Alternatively, PLL based pre-synchronization may also be used where PLLs are run to detect the phase and voltage magnitude mismatches between the converter output voltage and the grid voltage. Two sets of PI compensators can be used on the differences, and dynamic adjustments ΔV0 and Δω0 are generated which are added to the nominal voltage and frequency set-points. Note that these PLLs are not required for grid synchronization when the power electronic converter is connected to the electrical network/grid; rather, the double synchronous space vector oscillator serves as the synchronizing units.
The droop responses given by Equations (8), (9), (10), and (11) appear at the converter's switch terminals and not at the PoC. The LCL filter causes voltage deviation from the ideal droop response depending on the power flow between the converter and the grid. The terminal voltage compensation (TVC) (see
vtvc=jω0(La+Lg)i (16)
In various embodiments, DSUVOC is a vector controller running on both a and β axis. In a single-phase implementation, a full vector controller is used. The feedback signal iβ can be generated by delaying the actual converter output current ia=ig or ia by T0/4=2π/(4ω0), where ω0 denotes the nominal frequency of the power electronic converter and the modulating signal for PWM is obtained from vca. All analysis and design guidelines presented in the present disclosure are generalized to apply identically for single phase and three phase applications using a parameter N denoting the number of phases, i.e., N=1 and N=3 for single and three phase systems, respectively.
The GFL and GFM modes of operation of the DSUVOC are validated through hardware experiments using laboratory prototypes. For digital implementation, the SVO dynamic equations are discretized using Huen's method, which is a second order Runge-Kutta technique [23].
In various embodiments, a single-phase active rectifier is used to validate the GFL operation, which has real and reactive powers ratings of Prated=3 kW and Qrated=1.5 kVAR, respectively. Accordingly, experiments are done for single phase systems, and hence, the negative sequence SVO is disabled. The subscript ‘+’ is dropped from all parameters for simplicity, and the nominal DC bus voltage is set as vdc*=200 V.
Next,
A step change in the DC load is introduced from 0.5 kW to 1.2 kW at t=t2 while the reactive power reference is kept at Q0=0 and the corresponding response is shown in
DSUVOC GFM operation is validated in a hybrid AC-DC microgrid, and the microgrid structure is shown in
The converter output current without using the harmonic compensation method is illustrated in
Next, unintentional islanding is demonstrated in
An additional set of experiments is performed to validate the fault ride-through capability of the power electronic converter with DSUVOC control.
Next, the fault ride-through capability of the DSUVOC controller is tested under grid-tied operation. While connected to a grid (emulated by a programmable AC source vTH and an impedance ZTH), a sudden voltage sag is introduced to emulate a grid fault.
Next,
Due to its enhanced synchronization capability, an exemplary DSUVOC can enable stable converter operation under widely varying grid impedance conditions without the need for any change/tuning of control parameters.
In accordance with embodiments of the present disclosure, an exemplary DSUVOC provides a comprehensive solution for grid following and grid forming converters. Through experiments, an exemplary GFL controller is shown to retain synchronization with the grid without a dedicated PLL. DC bus voltage regulation is also demonstrated using an exemplary GFL controller. The GFM controller achieves seamless transition from islanded to grid-connected mode using the PLL-less pre-synchronization method as well as serving local loads without interruption in an event of unintentional islanding. Both symmetrical and asymmetrical fault ride-through operations under islanded and grid-tied operations have been demonstrated. Robust converter operation under widely varying grid impedances ranging from 10% p.u. to 100% p.u. using identical control parameters has been achieved.
An exemplary double synchronous unified virtual oscillator controller has several advantages over existing grid-forming and grid following power electronic converter technologies. While grid-forming converters are the fundamental building blocks in self-sustaining microgrid applications, an exemplary double synchronous unified virtual oscillator controller reduces the number of voltage and current sensors in half compared to existing grid forming control methods, thereby leading to lower cost. Further, an exemplary DSUVOC controller is easily scalable enabling plug-and-play type application, thereby simplifying commissioning in the field. For grid following operations, an exemplary DSUVOC controller enables grid synchronization without phase-locked-loops which can be very useful in weak grid and ultra-weak grid conditions. For example, in an HVDC-VSC (High Voltage Direct Current—Voltage Source Converter) application, an exemplary DSUVOC controller is expected to give significant performance improvement in terms of stability.
An exemplary double synchronous unified virtual oscillator controller enables fast over-current limiting and ride-through of both balanced/symmetric and unbalanced/asymmetric AC faults without the need for switching to a back-up-controller. Additionally, a PLL is not required for such fault ride-through or any mode of operation in both grid following and grid forming power electronic converters. Due to its PLL nature, robust synchronization under a variable grid condition is achieved, while a stable converter operation is achieved using identical control parameters irrespective of grid impedance variations ranging from 10% p.u. to 100 p.u.
Potential applications of an exemplary grid-forming controller include, but are not limited to, battery energy storage systems, parallel UPS (uninterruptible power supply) systems, interfacing converters for distributed and renewable (such as solar, wind and wave) energy resources, and solid-state-transformers. Potential applications of an exemplary grid-following controller include, but are not limited to, a PV (photovoltaic) inverter, wind power converter, an active-front-end motor drive, HVDC-VSC, and UPS. A grid following controller may also be used in STATCOM (static synchronous compensator) and active power filter applications. The robust synchronizing capability irrespective of grid impedance variations can substantially reduce the cost of commissioning/deployment and maintenance of power electronic converter under changing grid conditions.
In brief, a power electronic converter can utilize exemplar DSUVOC control logic or circuitry to convert direct current to alternating current that is input into a power grid. An exemplary DSUVOC controller includes a double synchronous space vector oscillator component, a sequence extraction (SE) component, a fault detection (FD) component, a pre-synchronization (PS) component, a virtual impedance (VI) component, a terminal voltage compensation (TVC) component, and/or an active damping (AD) component, wherein the double synchronous unified virtual oscillator controller is configured to control the power electronic converter for both grid forming and grid following modes of operation. In various embodiments, a processor of a power electronics converter can be configured to implement the DSUVOC control operations described herein. Accordingly, such operations can be programmed on a digital controller, in various embodiments.
It should be emphasized that the above-described embodiments are merely possible examples of implementations, merely set forth for a clear understanding of the principles of the present disclosure. Many variations and modifications may be made to the above-described embodiment(s) without departing substantially from the principles of the present disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure.
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Claims
1. A double synchronous unified virtual oscillator controller of a power electronic converter in a power grid, comprising:
- a double synchronous space vector oscillator configured to generate a voltage vector output using feedback of an output current of a power electronic converter, the double synchronous space vector oscillator comprising a double sequence current reference generation component, a double sequence vector limiter component, a positive sequence space vector oscillator component, and a negative sequence space vector oscillator component;
- a sequence extraction component that is configured to extract positive and negative sequence symmetrical components of the output current of the power electronic converter;
- a fault detection component that is configured to detect and latch a fault condition based on the feedback of the output current of the power electronic converter or a grid voltage at a point-of-coupling of the power electronic converter with the power grid;
- a virtual impedance component that is configured to achieve harmonic current suppression in the output current of the power electronic converter;
- an observer based active damping component that is configured to achieve resonance damping in a high frequency range originating from a higher-order filter of the power electronic converter, wherein the higher-order filter is at least a second order filter;
- a terminal voltage compensation component that is configured to compensate a voltage deviation due to the input filter or other non-ideal effects of the power electronic converter;
- a pre-synchronization component that is configured to synchronize the double synchronous space vector oscillator with a terminal voltage of the power electronic converter at the point-of-coupling before being connected to the power grid,
- wherein the double synchronous unified virtual oscillator controller is configured to control the power electronic converter for both grid forming and grid following operations.
2. The double synchronous unified virtual oscillator controller of claim 1, wherein the higher-order filter comprises an LCL filter.
3. The double synchronous unified virtual oscillator controller of claim 1, wherein the power electronic converter connects to the power grid via a static transfer switch.
4. The double synchronous unified virtual oscillator controller of claim 1, wherein the double synchronous unified virtual oscillator controller is configured to provide grid synchronization in a grid-following mode of operation with bidirectional power flow control capability without using a phase-locked-loop.
5. The double synchronous unified virtual oscillator controller of claim 1, wherein the double synchronous unified virtual oscillator controller is configured to provide DC bus voltage regulation in a grid-following mode of operation without a phase-locked-loop.
6. The double synchronous unified virtual oscillator controller of claim 1, wherein the double synchronous unified virtual oscillator controller is configured to implement a grid forming mode of operation that implements a droop response for both grid connected and islanded operations.
7. The double synchronous unified virtual oscillator controller of claim 6, wherein the double synchronous unified virtual oscillator controller is implemented using an error in voltage vector magnitude in a voltage magnitude correction term.
8. The double synchronous unified virtual oscillator controller of claim 6, wherein the double synchronous unified virtual oscillator controller is implemented using an error in square of voltage vector magnitude in a voltage magnitude correction term.
9. The double synchronous unified virtual oscillator controller of claim 6, wherein the double synchronous unified virtual oscillator controller is configured to generate a switching duty ratio based on a DC bus voltage measurement.
10. The double synchronous unified virtual oscillator controller of claim 6, wherein the double synchronous unified virtual oscillator controller is configured to provide voltage regulation support without communication through a communication network.
11. The double synchronous unified virtual oscillator controller of claim 1, wherein the double synchronous unified virtual oscillator controller is configured to enable grid synchronization of a grid following power electronic converter or a grid forming power electronic converter under balanced and unbalanced grid voltage conditions without operation of a phase-locked-loop.
12. The double synchronous unified virtual oscillator controller of claim 1, wherein the double synchronous unified virtual oscillator controller is configured to enable a ride-through of balanced and unbalanced grid faults by limiting the output current of the power electronic converter without switching to a phase-locked-loop based back-up controller.
13. The double synchronous unified virtual oscillator controller of claim 1, wherein the double synchronous unified virtual oscillator controller is configured to enable grid synchronization of the power electronic converter under variable grid impedance conditions without tuning of control parameters.
14. The double synchronous unified virtual oscillator controller of claim 1, wherein the virtual impedance component is configured to suppress harmonic distortion in the output current of a grid-following power electronic converter or a grid-forming power electronic converter.
15. The double synchronous unified virtual oscillator controller of claim 1, wherein the terminal voltage compensation component is configured to eliminate a voltage deviation caused by the higher order input filter of the power electronic converter.
16. The double synchronous unified virtual oscillator controller of claim 1, wherein the double sequence vector limiter component is configured to limit a reference of the output current of the power electronic converter within limits allowable by power electronic converter hardware.
17. The double synchronous unified virtual oscillator controller of claim 1, wherein the positive sequence space vector oscillator component and the negative sequence space vector oscillator component are configured to enable simultaneous synchronization with positive and negative sequence symmetrical components of the grid voltage without operation of a phase-locked-loop.
18. The double synchronous unified virtual oscillator controller of claim 1, wherein active resistances in the positive and negative sequence space vector oscillator components are configured to enable over-current limiting protection under fault conditions.
19. The double synchronous unified virtual oscillator controller of claim 1, wherein the pre-synchronization component is configured to achieve start-up in a grid-following power electronic converter or seamless islanded to grid connected transition in a grid forming power electronic converter without operation of a phase-locked-loop.
20. The double synchronous unified virtual oscillator controller of claim 1, wherein the double sequence current reference generation component is configured to achieve different control objectives in the power electronic converter, wherein the different control objectives include at least one of constant real power flow, constant reactive power flow, or balanced output current.
Type: Application
Filed: Feb 11, 2021
Publication Date: Aug 12, 2021
Inventors: M A. Awal (Raleigh, NC), Iqbal Husain (Raleigh, NC)
Application Number: 17/173,505