METHOD FOR IMPROVING CONTROL GATE UNIFORMITY DURING MANUFACTURE OF PROCESSORS WITH EMBEDDED FLASH MEMORY
A device has a semiconductor substrate including a recessed region. The recessed region has a center portion and a periphery portion. An isolation region abuts the periphery portion. A plurality of gate stacks are in the recessed region. A protective layer overlying the plurality of gate stacks and the isolation region has a substantially planar upper surface across the recessed region and the isolation region.
Flash memories have some particular advantages and benefits, as compared to other types of solid-state non-volatile memory structures. Many of these advantages and benefits are related, for example, to improved read, write, and/or erase speeds, power consumption, compactness, cost, etc. Flash memories are commonly used in high-density data storage devices configured for use with cameras, cell phones, audio recorders, portable USB data storage devices—often referred to as thumb drives or flash drives—etc. Typically, in such applications, a flash memory is manufactured on a dedicated microchip, which is then coupled with another chip or chips containing the appropriate processor circuits, either together in a single package, or in separate packages configured to be electrically coupled.
Processors with embedded flash memories are a more recent development. In such devices, a flash memory array is manufactured together with logic and control circuitry on a single chip. This arrangement is often used in microcontroller units (MCU), i.e., small computer devices integrated onto single chips, which are typically designed to repeatedly perform a limited number of specific tasks. MCUs are often used in smart cards, wireless communication devices, automobile control units, etc. Integration of memory with related processing circuitry can improve processing speed while reducing package size, power consumption, and cost.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides various embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
In the drawings, some elements are designated with a reference number followed by a letter, e.g., “704a, 704b.” In such cases, the letter designation is used where it may be useful in the corresponding description to refer to or to differentiate between specific ones of a number of otherwise similar or identical elements. Where the description omits the letter from a reference, and refers to such elements by number only, this can be understood as a general reference to any or all of the elements identified by that reference number, unless other distinguishing language is used.
Reference to a semiconductor substrate can include within its scope any elements that are formed or deposited on a substrate, unless the context clearly limits the scope further. For example, reference to planarizing a surface of a semiconductor substrate can refer to planarizing one or more layers of material deposited or otherwise formed on the actual base material of the substrate, including, for example polysilicon layers, metallic layers, dielectric layers, or a combination of materials, layers, and/or elements.
A microcontroller unit (MCU) typically includes a number of discrete devices, such as, e.g., a central processing unit (CPU) core, static random access memory (SRAM) arrays (or modules), flash memory modules, a system integration module, a timer, an analog-to-digital converter (ADC), communication and networking modules, power management modules, etc. Each of these devices, in turn, comprises a number of passive and active electronic components, such as, e.g., resistors, capacitors, transistors, and diodes. A large number of these components, particularly the active components, are based on various types of metal-oxide semiconductor field effect transistors (MOSFET), or variations thereof. In a MOSFET, conductivity in a channel region extending between source and drain terminals is controlled by an electric field in the channel region, produced by a voltage difference between a control gate and the body of the device.
The flash memory array 104 is positioned within a recessed region 140, and isolated by a shallow trench isolation (STI) region 115a. The memory array 104 includes a plurality of flash memory cells 118 that are, in many respects similar to the logic transistors 108, each having a control gate 120, a channel region 122, and a gate dielectric 124. However, each of the flash memory cells 118 also includes a floating gate 126 positioned between the control gate 120 and the gate dielectric 124. In the embodiment shown, an erase gate dielectric 128 is positioned between each floating gate 126 and a corresponding erase gate 130. Alternating source and drain regions 132, 134 are interleaved between memory cells 118 so that each memory cell shares a source 132 with an adjacent memory cell on one side and a drain 134 with an adjacent memory cell on the opposite side. Select gates 136 are positioned between the drains 134 and the control and floating gates 120, 126 of each memory cell 118. Various layers of material, 138 are shown in general outline, which are not configured to act as conductors or semiconductors in the device 100. These layers may comprise dielectrics, resist overlays, passivation layers, etch stop layers, spacers, etc., and include a dielectric layer 138a positioned between each of the floating gates 126 and the respective control gate 120 of the memory cells 118.
Because of the similarities in the structures of the logic transistors 108 and the flash memory cells 118, they would be of similar heights except for the added height of the floating gates 126 and corresponding dielectric layers 138 of the memory cells. This can be a problem because, at several points during the manufacturing process, chemical/mechanical polishing (CMP) procedures are performed to produce a substantially flattened surface for succeeding process steps. A CMP procedure that reduces the control gates 110 of the logic transistors 108 to the appropriate height can damage the taller control gates 120 of the memory cells 118.
One solution is to form the memory array 102 in a recessed region 140, in which a surface 142 of the semiconductor substrate 102 within the recessed region is reduced in height, relative to a surface 144 of the substrate outside the recessed region, by a distance about equal to the total thickness of the floating gates 126 and the dielectric 138a. This difference in height between the surfaces 142 and 144 may be termed a step height or step height differential between the surface 142 of the recessed region 140 in which memory cells of the memory array 102 are formed and the surface 144 of the periphery around the recessed region in which other components are formed. According to an embodiment, the recessed region 140 is formed via an etching procedure, in which the surface of the semiconductor substrate 102 is etched evenly across the intended recessed region to a desired depth, resulting in a substantially planar surface 142 on which the memory cells 118 are subsequently formed.
According to an alternative embodiment, a layer of semiconductor material is deposited or grown on the surface of the substrate 102 outside the intended recessed region 140, raising the surface 144 to a desired height above the recessed surface 142. For the purposes of the present disclosure, reference to the formation of a recessed region includes any process that results in a defined region having a depth, relative to the surrounding substrate, about equal to the height difference between floating gate transistors and MOSFET transistors that do not employ floating gates.
As noted above, the logic transistors 108 operate by application of an electric field over the respective channel region 112, thereby changing the conductivity of the channel region. The electric field is produced by application of a voltage potential between the control gate 110 and the semiconductor body 102. A MOSFET can be configured either to increase or decrease conductivity when an electric field of a selected polarity is present. Typically, transistors in a logic circuit are designed to function like switches, turning on or off in response to an electric field of a selected strength, and controlling a flow of current in the channel region.
In the memory cells 118, during a write operation, electrons can be forced to tunnel through the gate dielectric 124 to the floating gate 126, where they can remain trapped indefinitely, by applying a write voltage to the control gate 120 while applying a voltage potential across the channel region 122. If there is a sufficient number of electrons trapped on the floating gate 126, the electrons can block an electric field produced by the control gate 120, preventing the control gate from acting to change conductivity in the channel region 122. Thus, the presence of electrons can be detected by applying a voltage potential across the drain and source regions 132, 134 while applying a read voltage to the control gate 120 to produce an electric field, and testing for a current flow in the channel region 122. Typically, a binary value of one is the default setting of a flash memory cell at the time of manufacture and before programming, while a binary value of zero is indicated if channel current is unaffected by a read voltage at the control gate 120. A binary zero value on a flash memory cell can be erased—i.e., returned to a one—by applying a sufficiently powerful erase voltage to the erase gate 130. This causes electrons trapped on the floating gates 126 of the memory cells 118 adjacent to the energized erase gate 130 to tunnel out through the erase gate dielectrics 128 to the erase gate 130. In practice, there are many more memory cells 118 adjacent to the erase gate 130, extending along rows lying perpendicular to the view of
As advances in technology enable ever smaller and more compact features, power and voltage requirements are reduced while memory density and speed increase. However, a problem that has arisen with the reduction in size is that a very small variation in gate dimensions can have a progressively increasing impact on performance, because such a variation represents a larger change, relative to the proportionately smaller nominal gate dimensions. This becomes a greater issue as technology nodes drop below 65 nm, 40 nm, and 28 nm scales.
Initially, as shown in
Proceeding to the stage shown in
In
Turning finally to
As shown in
In order to utilize the memory cells 118 near the edges of the recessed region 140, the operating parameters of the entire memory array 108 can be modified, to ensure that data is not lost or corrupted because the memory cells near the edges of the recessed region are not properly written or erased. Modifying the operating parameters of the entire memory cell in this manner can result in less than optimal performance of the entire array. One alternative is to leave the cells nearest the edges of the recessed region 140 inactive—or leave the edge region empty—but this will result in a loss of capacity. The reduced total capacity may be minimal if all of the memory cells of a device are in a single array, but many MCU devices are designed to place smaller memory arrays adjacent to circuits that will be using them, to increase throughput speed. In such devices, smaller memory arrays are positioned at multiple locations on the device. Consequently, the total area of the edge regions is much larger than in a single array, so the lost capacity is also much greater.
The inventors have also recognized that the problem could be eliminated if the BARC were deposited on a substantially planar surface. However, planarizing the surface at the process stage shown in
Embodiments described hereafter with reference to
As shown in
Other processes may be utilized to remove the sacrificial layer 180 and to partially remove the protective layer 162. The portion of the protective layer 162 remaining after the etching of the surface of the substrate to remove the sacrificial layer 180 and partially remove the protective layer depends on the specific etching process utilized. In one embodiment, the etching process partially removes the protective layer 162 to leave a remaining portion of the protective layer having a depth of 1500-2000 angstroms. The described embodiments of the present disclosure, which apply the sacrificial layer 180 through spin coating and remove the sacrificial layer and partially remove the protective layer, improve the uniformity of the BARC layer 188 deposited across the center and periphery portions of the flash memory array 104 (
According to an embodiment, the etch of the sacrificial layer 180 proceeds directly following the deposition and—if necessary—planarizing of the sacrificial layer, without any intervening process steps. According to another embodiment, one or more process steps are performed between the deposition of the sacrificial layer 180 and its subsequent removal in the etch procedure. These intervening process steps can include processes that are unrelated to the formation of the memory array 104.
Proceeding to
The embodiments shown and described herein provide improvements to a process for manufacturing microelectronic devices that include embedded flash memory arrays. According to various embodiments, prior to defining control and floating gate stacks of the memory arrays in recessed regions on a semiconductor substrate, a planar surface is provided on the substrate over layers of material from which the gate stacks are to be formed, for deposition of an anti-reflective coating and of a patterning film at an even thickness. This is beneficial because the anti-reflective coating, in particular, has a tendency to vary in thickness when it is deposited over a non-planar surface, which in turn, can contribute to non-uniformity of control and floating gate dimensions. The dimensions of the control and floating gates have a direct impact on critical operating characteristics of a memory device, such as read, write, and erase speeds, program and erase state voltage and current levels, power consumption, etc. If gate dimensions vary within a memory array, a typical practice is to operate the entire array based on the operating characteristics of the weakest cells. Thus, significant variation in dimensions is a problem because, if even a small percentage of the cells in an array require higher voltages and/or longer read and write times, the entire array is operated at the same levels, resulting in a loss of efficiency and speed for the entire array. By providing the planar surface, non-uniformity in gate dimensions of the memory arrays is reduced or eliminated. This, in turn, results in arrays with higher overall speed and efficiency.
According to an embodiment, the improvements include forming a protective layer over a non-planar surface of a semiconductor substrate, in particular, for example, over a recessed region of the semiconductor substrate, in which an embedded memory array is to be formed. A sacrificial layer is then deposited over the protective layer, to a depth sufficient to permit formation of a substantially planar surface on the sacrificial layer. The sacrificial layer is then etched to a depth that removes the sacrificial layer and leaves a planar surface formed in the protective layer.
According to another embodiment, the method includes forming a recessed region in a semiconductor substrate, and forming gate materials for a plurality of floating gates and control gates of a memory array, in layers over the recessed region. A protective layer is then formed over the gate materials in the recessed region, and planarized to improve uniformity of gate dimensions. An etch mask is formed over the planarized protective layer, and gate stacks of the memory array are formed in the recessed region, by etching the gate materials. According to an embodiment, planarizing the protective layer includes depositing a self-leveling sacrificial layer over the protective layer to produce a substantially planar surface, then etching the surface at an even rate, and to a depth sufficient to remove the sacrificial layer, which results in a planar surface on the protective layer.
According to another embodiment, the method includes forming a protective layer over a stack of gate-material layers in a recessed region of a semiconductor substrate. A self-leveling sacrificial layer is then deposited over the protective layer to a depth sufficient to produce a planarized surface of the semiconductor substrate, and the sacrificial layer is etched back at an even rate to a depth sufficient to produce a substantially planar surface on the protective layer.
Ordinal numbers, e.g., first, second, third, etc., are used in the claims according to conventional claim practice, i.e., for the purpose of clearly distinguishing between claimed elements or features thereof, etc. Ordinal numbers may be assigned arbitrarily, or assigned simply in the order in which elements are introduced. The use of such numbers does not suggest any other relationship, such as order of operation, relative position of such elements, etc. Furthermore, an ordinal number used to refer to an element in a claim should not be assumed to correlate to a number used in the specification to refer to an element of a disclosed embodiment on which that claim reads, nor to numbers used in unrelated claims to designate similar elements or features.
While the method and process steps recited in the claims may be presented in an order that corresponds to an order of steps disclosed and described in the specification, except where explicitly indicated, the order in which steps are presented in the specification or claims is not limiting with respect to the order in which the steps may be executed.
The abstract of the present disclosure is provided as a brief outline of some of the principles of the invention according to one embodiment, and is not intended as a complete or definitive description of any embodiment thereof, nor should it be relied upon to define terms used in the specification or claims. The abstract does not limit the scope of the claims.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A device, comprising:
- a semiconductor substrate including a recessed region, the recessed region having a center portion and a periphery portion;
- an isolation region abutting the periphery portion;
- a plurality of gate stacks in the recessed region; and
- a protective layer overlying the plurality of gate stacks and the isolation region, having a substantially planar upper surface across the recessed region and the isolation region.
2. The device of claim 1, wherein each of the gate stacks comprises:
- a floating gate on the recessed region of the semiconductor substrate;
- a control gate on the floating gate; and
- a protective cap layer on the floating gate formed of the protective layer.
3. The device of claim 2, wherein the protective cap layer has a depth of 1500-2000 angstroms in the recessed region.
4. The device of claim 3, wherein the protective cap layer includes a first dielectric layer of a first material and a second dielectric layer of a second material different from the first material.
5. The device of claim 4, wherein the first material is silicon nitride and the second material is silicon oxide.
6. The device of claim 5, wherein the second dielectric layer is thicker than the first dielectric layer.
7. The device of claim 2, wherein the recessed region has a depth greater than about 300 Angstroms.
8. The device of claim 7, wherein an upper surface of the control gate is at a level above the depth of the recessed region.
9. The device of claim 2, wherein each of the gate stacks further includes a dielectric layer between the floating gate and the substrate.
10. The device of claim 2, further comprising protective dielectric layers on opposing sides of each of the gate stacks.
11. A device, comprising:
- a semiconductor substrate including a recessed region, the recessed region having a center portion and a periphery portion; and
- a flash memory array in the recessed region, the flash memory array including a plurality of gate stacks and each of the gate stacks having a width, the widths of the gate stacks being uniform for the gate stacks in the center portion of the recessed region and the gate stacks in the periphery portion of the recessed region.
12. The device of claim 11, further comprising a plurality of transistors outside the recessed region.
13. The device of claim 12, wherein:
- each of the gate stacks includes: a floating gate; and a first control gate on the floating gate;
- each of the transistors includes: a second control gate; and
- upper surfaces of the first control gate and the second control gate are substantially coplanar.
14. The device of claim 13, wherein the second control gates have greater width than the first control gates.
15. The device of claim 11, further comprising an erase gate and a select gate on opposing sides of each of the gate stacks.
16. The device of claim 15, wherein neighboring pairs of the gate stacks share a single erase gate.
17. The device of claim 16, wherein each erase gate is over a source/drain region.
18. A device, comprising:
- a memory array in a first region of a substrate surrounded by a second region of the substrate, the memory array including: a plurality of gate stacks in a central region of the first region and a peripheral region of the first region, each gate stack including: a dielectric layer; a floating gate separated from the substrate by the dielectric layer; and a control gate; wherein the control gates of the gate stacks have uniform width in the central region and the peripheral region; and
- processor circuits in the second region of the substrate, including a plurality of transistors, each having a control gate extending to the same height above the substrate as the control gates of the gate stacks.
19. The device of claim 18, wherein the first region is separated from the second region by an isolation structure.
20. The device of claim 19, wherein the isolation structure includes a step height differential between a first side abutting the first region and a second side abutting the second region.
Type: Application
Filed: Jul 13, 2021
Publication Date: Nov 4, 2021
Inventors: Meng-Han LIN (Hsinchu), Wei Cheng WU (Hsinchu)
Application Number: 17/374,591