INTEGRATED SCHOTTKY DIODE WITH GUARD RING
Described examples include an integrated circuit having a semiconductor substrate having an epitaxial layer located thereon, the epitaxial layer having a surface. The integrated circuit also has a buried layer formed in the semiconductor substrate, the epitaxial layer located between the buried layer and the surface. The integrated circuit also has a Schottky contact and an ohmic contact formed on the surface. The integrated circuit also has a Pdrift region in the epitaxial layer located between the ohmic contact and the Schottky contact.
This application is a division of U.S. patent application Ser. No. 16/563,366, issued as U.S. Pat. No xx,xxx,xxx. which is incorporated herein by reference in its entirety.
TECHNICAL FIELDThis relates generally to semiconductor devices, and more specifically, but not exclusively, to Schottky diodes.
BACKGROUNDA Schottky barrier is the junction between a conductor, usually a metal, and a lightly doped semiconductor. This barrier may function as a diode. The anode of a Schottky diode includes the metal and the cathode of the Schottky diode includes the semiconductor. Schottky diodes provide higher performance in certain circuits than p-type/n-type diodes in that Schottky diodes have a smaller forward bias voltage drop than p-n junction diodes. In rectifiers, this means that Schottky-based rectifiers may consume less power (e.g., product of voltage drop and current through the Schottky diode is lower). In other circuits, Schottky diodes may prevent saturation of transistors, and thus decrease the shut-off time of those transistors. However, incorporating Schottky diodes into an integrated circuit manufacturing process flow often requires additional masking steps and sometimes additional metal deposition steps, thus increasing cost. In addition, it is difficult to manufacture Schottky diodes capable of operation with high voltages into integrated circuits with complementary metal-oxide semiconductor (CMOS) devices.
SUMMARYIn accordance with an example, an integrated circuit includes a semiconductor substrate having an epitaxial layer located thereon, the epitaxial layer having a surface. The integrated circuit also has a buried layer formed in the semiconductor substrate, the epitaxial layer located between the buried layer and the surface. The integrated circuit also has a Schottky contact and an ohmic contact formed on the surface. The integrated circuit also has a Pdrift region in the epitaxial layer located between the ohmic contact and the Schottky contact.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are not necessarily drawn to scale.
The term “coupled” may include connections made with intervening elements, and additional elements and various connections may exist between any elements that are “coupled.” Also, in this description, the terms “on” and “over” may include layers or other elements where intervening or additional elements are between an element and the element that it is “on” or “over.” The term “directly on” with respect a first layer over a second layer means the first layer touches the second layer.
Examples described hereinbelow provide a Schottky diode with high-voltage capability using a lateral diffused metal-oxide semiconductor (LDMOS) manufacturing process by modifying the position and size of elements fabricated using that LDMOS process. In an example, an integrated circuit has a semiconductor substrate having an epitaxial layer located thereon, the epitaxial layer having a surface. The integrated circuit also has a buried layer formed in the semiconductor substrate, the epitaxial layer located between the buried layer and the surface. The integrated circuit also has a Schottky contact and an ohmic contact formed on the surface. The integrated circuit also has a Pdrift region in the epitaxial layer located between the ohmic contact and the Schottky contact.
Pdrift regions 115 are formed from one or more implants producing at least one lightly doped region having a conductivity type opposite to the conductivity type of epitaxial layer 106, e.g. p-type regions, thus providing additional p-n junction surface area. The p-n junction may distribute the electric field applied between anode contact 144 and cathode contacts 138 when Schottky diode 100 is reverse biased. Gate layer 122 is formed on a dielectric isolation layer such as first insulating layer 116 and a second insulating layer 117, e.g. a gate dielectric layer. Gate layer 122 may partially overlap a heavily doped p-type region like p+ region 129. In an example, gate layer 122 is a polysilicon plate and the polysilicon plate ends above first insulating layer 116. The p+ regions 129 may each be located partially within corresponding Pdrift regions 115 and partially within the epitaxial layer 106 (e.g. at the interface between the Pdrift regions 115 and the epitaxial layer 106), such that a p-n junction is formed between each p+ region 129 and the epitaxial layer 106 on a side of the p+ region 129 opposite the surface of the epitaxial layer 106. Thus, each p+ region 129 is located between a corresponding one of the gate layers 122 and the Schottky barrier 146, and between a corresponding one of the Pdrift regions 115 and the Schottky barrier 146. In an example, gate layer 122 is coupled to a reference potential such as ground (via an unseen connection), forming a field plate proximate to the Pdrift region 115. The gate layer 122 may thereby affect more of the electric field between anode contact 144 and cathode contact 138 in conjunction with the p-n junction between Pdrift regions 115 and n− epitaxial layer 106, and thus away from the Schottky barrier 146. This arrangement may reduce leakage at the perimeter that might otherwise occur due to high electric field. More specifically, the gate layers 122, p+ regions 129 and Pdrift regions 115 may cooperate to produce a depletion region between the Pdrift regions 115 extending into the epitaxial layer 106. The depletion region may have the effect of reducing the electrical field strength near the Schottky barrier 146, which could otherwise cause unacceptable leakage at the Schottky barrier 146. The epitaxial layer 106 outside the depletion region and between the cathode contact regions 131 and Schottky barrier 146 may function as an n-type drift region for carriers (electrons) during operation of Schottky diode 100.
Step 304 includes forming Pdrift region 412 under a gate region (e.g. the channel region) in transistor 401 and forming a Pdrift region 415 in Schottky diode 400 as shown in
Step 305 includes forming n-well 408 in transistor 401, but not in the Schottky diode 400, as shown in
Step 306 includes forming a first insulating layer 416 as shown in
Step 308 includes forming field plate 422D and gate 422T as shown in
Step 310 includes forming double-diffused well (d-well) 424 in transistor 401 as shown in
Step 312 includes forming Pdrift region ohmic p+ contact 429, and LDMOS body ohmic p+ region 430, n+ cathode ohmic region 431, n+ source 426 and drain n+ 428 as shown in
Step 314 includes forming a thin metal silicide, in this example a silicide of cobalt, titanium, nickel, or similar metals as shown in
After silicide formation, step 316 includes forming a first level metal insulator 436 as shown in
Modifications are possible in the described examples, and other examples are possible, within the scope of the claims.
Claims
1. A method of forming an integrated circuit, comprising:
- forming a Schottky contact at a top surface of a semiconductor layer having a first conductivity type; and
- forming an ohmic contact to the semiconductor layer; and
- forming a first doped region at the top surface between the Schottky contact and the ohmic contact, the first doped region having an opposite second conductivity type and forming a closed path around the Schottky contact.
2. The method of claim 1, further comprising forming a doped buried layer having the first conductivity type between the semiconductor layer and a semiconductor substrate.
3. The method of claim 1, wherein the semiconductor layer includes an N-type epitaxial layer having first doping level.
4. The method of claim 1, further comprising forming a second doped region having the second conductivity type that intersects the surface between the first doped region and the Schottky contact.
5. The method of claim 4, further comprising forming a field plate that extends over the first doped region and the second doped region.
6. The method of claim 1, further comprising forming a dielectric isolation layer over the surface of the semiconductor layer between the ohmic contact and the Schottky contact.
7. The method of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.
8. The method of claim 1, further comprising forming a field plate over the first doped region.
9. The method of claim 1, further including forming an isolation structure that extends from the surface into the semiconductor layer, the isolation structure surrounding the ohmic contact and the Schottky contact.
10. The method of claim 1, further comprising forming a gate layer over the first doped region, and forming a lateral diffused metal-oxide semiconductor (LDMOS) transistor in or over the semiconductor layer, the LDMOS transistor including a gate formed from a same material layer as the gate layer.
11. A method of forming an integrated circuit, comprising:
- forming an epitaxial layer having a first n-type dopant concentration over a semiconductor substrate, the epitaxial layer having a top surface;
- forming an buried layer located between the semiconductor substrate and the epitaxial layer and having a second n-type dopant concentration greater than the first n-type dopant concentration;
- forming a doped p-type region located at the top surface, the p-type region surrounding an enclosed portion of the epitaxial layer at the top surface; and
- forming a metal silicide at the top surface over the enclosed portion.
12. The method of claim 11, further comprising forming first and second n-type regions at the surface of the epitaxial layer and having a greater dopant concentration than the epitaxial layer, the p-type region and the metal silicide being located between the first and second n-type regions.
13. The method of claim 11, further including forming first and second dielectric isolation layers over the epitaxial layer, the first dielectric isolation layer extending over the p-type region, and the second dielectric isolation layer extending over the p-type region, the metal silicide located between the first and second dielectric isolation layers.
14. The method of claim 11, wherein the p-type region is a first p-type region having a first dopant concentration, and further comprising forming a second p-type region having a greater second dopant concentration located at the surface, an interface between the first p-type region and the epitaxial layer ending at the second p-type region.
15. The method of claim 15, further comprising forming a polysilicon plate over the first p-type region and ending over the second p-type region.
16. The method of claim 16, further comprising forming first and second dielectric isolation layers over the epitaxial layer, the first dielectric isolation layer extending over the first p-type region, and the second dielectric isolation layer extending over the first p-type region, wherein the polysilicon plate ends over the first dielectric isolation layer and over the second dielectric isolation layer.
17. The method of claim 16, further comprising forming a gate dielectric layer between the polysilicon plate and the first p-type region.
18. A method of forming an electronic device, comprising:
- forming a buried layer in a semiconductor substrate, the buried layer separated from a surface of the semiconductor substrate by a semiconductor layer having a first conductivity type;
- forming a Schottky barrier to the semiconductor layer;
- forming an ohmic contact to the semiconductor layer; and
- forming a doped region having an opposite second conductivity type in the semiconductor layer between the Schottky barrier and the ohmic contact, the doped region completely surrounding the Schottky barrier at the surface.
19. The method of claim 19, further comprising forming an insulating layer on the surface between the Schottky barrier and the ohmic contact, and wherein the insulating layer ends over the doped region.
20. The method of claim 20, wherein the first conductivity type is N-type and the second conductivity type is P-type.
Type: Application
Filed: Jan 14, 2022
Publication Date: May 5, 2022
Inventor: Sheldon Douglas Haynie (Morgan Hill, CA)
Application Number: 17/576,142