3D PACKAGE CONFIGURATION
A novel 3D package configuration is provided by stacking a plurality of semiconductor package units or a folded flexible circuit board structure on a lead frame and electrically connected therewith based on the foldable characteristics of the flexible circuit board, and the high temperature resistance of the flexible circuit board which is suitable for insulating layer process, metal layer process, photolithography process, etching and development process, to make conventional semiconductor dies of various functions be bonded on one die and/or two side of a flexible circuit board and electrically connected therewith in advance.
This application claims the priority benefit of Taiwanese Application Serial Number 109145694, filed on Dec. 23, 2020, which is incorporated herein by reference.
TECHNICAL FILEDThis invention relates to a package configuration, and particularly relates to a 3D package configuration.
BACKGROUND OF THE INVENTIONThe application of 3D package configurations is rapidly developing to solve important technical issues such as miniaturization, multi-function integration, faster interconnection, and energy saving. A typical 3D package configuration usually obtained by stacking dies with through-silicon vias (TSV) or dies interconnected by micro-bumps and electrically connected to each other by micro-bumps.
However, the above-mentioned 3D package configurations usually involve thin film deposition, photolithography, development, etching, metallization and other semiconductor manufacturing processes, which are not only complicated in process and time-wasting in packaging, but also low yield rate and high cost. In view of these disadvantages, a novel 3D package configuration that can be manufactured by conventional techniques is highly expected by the industry.
SUMMARY OF THE INVENTIONThis invention discloses a 3D package configuration, comprising a lead frame and a plurality of semiconductor package units vertically stacked on the lead frame in sequence, wherein the semiconductor package units are electrically connected to each other and electrically connected to the lead frame, and each of the semiconductor package units comprises: a semiconductor die with a top surface and a bottom surface opposite to each other, and a plurality of side surfaces adjacent to the top surface and the bottom surface; and a folded flexible circuit board with a first surface and a second surface opposite to each other, wherein the bottom surface of the semiconductor die is bonded to the first surface and electrically connected to the folded flexible circuit board, and the first surface of the folded flexible circuit board is attached onto the top surface, the bottom surface and one of the side surfaces of the semiconductor die.
The above-mentioned 3D package configuration, wherein the folded flexible circuit board comprises: a flexible insulating substrate; a circuit formed on a surface of the flexible insulating substrate; and an insulating layer overlaying the circuit; wherein, the first surface of the folded flexible circuit board comprises a plurality of first bonding pads electrically connected to the circuit, and the bottom surface of the semiconductor die is bonded to the first surface and electrically connected to the folded flexible circuit board through the first bonding pads; wherein, the second surface of the folded flexible circuit board and the flexible insulating substrate corresponding to the top surface of the semiconductor die respectively comprise a plurality of second bonding pads and a plurality of first conductive holes electrically connected to the circuit, and the second surface of the folded flexible circuit board and the flexible insulating substrate corresponding to the bottom surface of the semiconductor die respectively comprise a plurality of third bonding pads and a plurality of second conductive holes electrically connected to the circuit, and each of the third bonding pads is electrically connected to the circuit through one of the second conductive holes; wherein, the semiconductor package units are vertically and sequentially stacked to interconnect with each other by bonding the third bonding pads of one of the semiconductor package unit to the second bonding pads of another adjacent one of the semiconductor package units, and the bottommost one of the semiconductor package units is directly bonded to the lead frame and electrically connected therewith through the third bonding pads.
The above-mentioned 3D package configuration, wherein the material of the flexible insulating substrate is selected from one of the group consisting of Polyester resin, Polyimide (PI), Modified Polyimide (MPI), Covalent Organic Framework (COF), Liquid Photo-Imageable (LPI), Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and flexible epoxy bonded fiber-glass board, or combinations thereof.
The above-mentioned 3D package configuration, wherein the material of the circuit is selected from one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof.
The above-mentioned 3D package configuration, wherein one of the semiconductor package units comprises a high power consuming semiconductor die.
The above-mentioned 3D package configuration, further comprising a heat dissipating mechanism, wherein the heat dissipating mechanism is sandwiched between the top surface of the high power consuming semiconductor die and first surface of the folded flexible circuit board attached on the top surface of the high power consuming semiconductor die.
This invention discloses another 3D package configuration, comprising a lead frame; and a folded flexible circuit board structure vertically stacked on the lead frame and electrically connected therewith, comprising: a flexible circuit board with a first surface and a second surface opposite to each other, wherein the flexible circuit board having a first die bonding zone formed on the first surface and at least one second die bonding zone formed on the first surface and/or the second surface; at least one first semiconductor die bonded to the first die bonding zone and electrically connected to the flexible circuit board; and at least one second semiconductor die bonded to the second die bonding zone and electrically connected to the flexible circuit board; wherein, the at least one second semiconductor die is vertically stacked above the at least one first semiconductor die by folding the flexible circuit board to form the folded flexible circuit board structure, and the folded flexible circuit board structure is vertically stacked on the lead frame and electrically connected therewith through lead frame bonding pads.
The above-mentioned another 3D package configuration, comprising a plurality of second semiconductor dies spaced with each other, and a plurality of second die bonding zones formed on the first surface and/or the second surface of the flexible circuit board, wherein each of the second semiconductor dies bonded on each of the second semiconductor die bonding zones and electrically connected to the flexible circuit board through each of the second die bonding pads in each of the second die bonding zones, and the second semiconductor die are vertically and sequentially stacked above the at least one first semiconductor die by folding the flexible circuit board, wherein the first die bonding zone overlaps with the second die bonding zones.
The above-mentioned another 3D package configuration, wherein the second die bonding zones are concurrently formed on the first surface of the flexible circuit board or concurrently formed on the second surface of the flexible circuit board.
The above-mentioned another 3D package configuration, wherein the second die bonding zones are alternatively formed on the first surface and the second surface of the flexible circuit board.
The above-mentioned another 3D package configuration, wherein the flexible circuit board comprises: a flexible insulating substrate; a circuit formed on a surface of the flexible insulating substrate; and an insulating layer overlaying the circuit; wherein, the first die bonding zone comprises a plurality of first die bonding pads electrically connected to the circuit to make the first semiconductor die electrically connected to the circuit through the first die bonding pads, and the at least one second die bonding zone comprises a plurality of second die bonding pads electrically connected to the circuit to make the at least one second semiconductor die electrically connected to the circuit through the second die bonding pads, and a plurality of lead frame bonding pads under the first die bonding zone are formed on the second surface of the flexible circuit board, and each of the lead frame bonding pads is electrically connected to each of the first die bonding pads corresponding thereof through a conductive hole.
The above-mentioned another 3D package configuration, wherein the material of the flexible insulating substrate is selected from one of the group consisting of Polyester resin, Polyimide (PI), Modified Polyimide (MPI), Covalent Organic Framework (COF), Liquid Photo-Imageable (LPI)—Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and flexible epoxy bonded fiber-glass board, or combinations thereof.
The above-mentioned another 3D package configuration, wherein the material of the circuit is selected from one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof.
The above-mentioned another 3D package configuration, wherein one of the second semiconductor dies bonded to one of the second chip bonding regions adjacent to a terminal of the flexible circuit board is a tel-communication chip, and an antenna region is formed between the terminal of the flexible circuit board and the telcommunication chip, wherein the antenna region comprises an integrated antenna circuit formed on the insulating substrate of the flexible circuit board and overlaid by the insulating layer of the flexible circuit board, and the tel-communication chip is electrically connected to the integrated antenna circuit through the second chip bonding pads.
The above-mentioned another 3D package configuration, wherein the material of the integrated antenna circuit is selected from one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof.
The above-mentioned another 3D package configuration, wherein one of the at least one first semiconductor die is a high power consuming semiconductor die.
The above-mentioned another 3D package configuration, further comprising a heat dissipating mechanism, wherein the heat dissipating mechanism is sandwiched between the top surface of the first semiconductor die and the folded flexible circuit board of the folded flexible circuit board structure.
This invention discloses further another 3D package configuration, comprising: a lead frame; and a folded flexible circuit board structure vertically stacked on the lead frame and electrically connected therewith, comprising: a first flexible circuit board with a first surface and a second surface opposite to each other, wherein the first flexible circuit board includes a first die bonding zone and at least one second die bonding zone formed on the first surface; at least one first semiconductor die bonded to the first die bonding zone and electrically connected to the first flexible circuit board; and at least one second semiconductor die bonded to the at least one second die bonding zone and electrically connected to the first flexible circuit board; a second flexible circuit board with a third surface and a fourth surface opposite to each other, wherein the second flexible circuit board includes at least one third die bonding zone formed on the third surface; and at least one third semiconductor die bonded to the at least one third die bonding zone and electrically connected to the second flexible circuit board; wherein, the at least one third semiconductor die and the at least one second semiconductor die are alternatively vertically stacked above the at least one first semiconductor die by folding the first flexible circuit board and the second flexible circuit board to make the first die bonding zone, the at least one second die bonding zone and the at least one third die bonding zone overlap with each other to form the folded flexible circuit board structure, and a plurality of lead frame bonding pads under the first die bonding zone are formed on the third surface of the second flexible circuit board, and each of the lead frame bonding pads is electrically connected to each of the first die bonding pads corresponding thereof through a conductive hole; wherein, the folded flexible circuit board structure is vertically stacked on the lead frame and electrically connected therewith through the lead frame bonding pads.
The above-mentioned further another 3D package configuration, comprising a plurality of second semiconductor dies spaced with each other, and a plurality of second chip bonding regions formed on the first surface of the first flexible circuit board, wherein each of the second semiconductor dies is bonded to each of the second chip bonding region and electrically connected to the first flexible circuit board through a second bonding pad in each of the second chip bonding region.
The above-mentioned further another 3D package configuration, comprising a plurality of third semiconductor dies spaced with each other, and a plurality of third chip bonding regions formed on the third surface of the second flexible circuit board, wherein each of the third semiconductor dies is bonded to one of the third chip bonding regions and electrically connected to the second flexible circuit board through a third bonding pad in each of the third bonding regions.
The above-mentioned further another 3D package configuration, wherein the first flexible circuit board comprises a plurality of first bonding pads and a plurality of second bonding pads respectively formed on the second surface corresponding to the first die bonding zone and the at least one second die bonding zone, and the second flexible circuit board comprises a plurality of third bonding pads formed on the fourth surface corresponding to the at least one third die bonding zone, and the first flexible circuit is joined with the second flexible circuit board to generate a foldable flexible circuit board by bonding the first bonding pads and the second pads formed on the second surface of the first flexible circuit board to the third bonding pads formed on the fourth surface of the second flexible circuit board.
The above-mentioned further another 3D package configuration, wherein the first flexible circuit board comprises: a first flexible insulating substrate; a first circuit formed on a surface of the first flexible insulating substrate; and a first insulating layer overlaying the first circuit; wherein, the first die bonding zone comprises a plurality of first bonding pads electrically connected to the first circuit to make the at least one first semiconductor die electrically connected to the first circuit through the first bonding pads, and the at least one second die bonding zone comprises a plurality of second die bonding pads electrically connected to the first circuit to make the at least one second semiconductor die electrically connected to the first circuit through the second die bonding pads.
The above-mentioned further another 3D package configuration, wherein the material of the first flexible insulating substrate is selected from one of the group consisting of Polyester resin, Polyimide (PI), Modified Polyimide (MPI), Covalent Organic Framework (COF), Liquid Photo-Imageable (LPI)—Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and flexible epoxy bonded fiber-glass board, or combinations thereof.
The above-mentioned further another 3D package configuration, wherein the material of the first circuit is selected from one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof.
The above-mentioned further another 3D package configuration, wherein the second flexible circuit board comprises: a second flexible insulating substrate; a second circuit formed on a surface of the second flexible insulating substrate; and a second insulating layer overlaying the second circuit; wherein, the at least one third die bonding zone is arranged to interlace with the first die bonding zone and the least one second die bonding zone, and the at least one third die bonding zone comprises a plurality of third bonding pads electrically connected to the second circuit to make the at least one third semiconductor die electrically connected to the second circuit through the third bonding pads.
The above-mentioned further another 3D package configuration, wherein the material of the second flexible insulating substrate is selected from one of the group consisting of Polyester resin, Polyimide (PI), Modified Polyimide (MPI), Covalent Organic Framework (COF), Liquid Photo-Imageable (LPI), Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and flexible epoxy bonded fiber-glass board, or combinations thereof.
The above-mentioned further another 3D package configuration, wherein the material of the second circuit is selected from one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof.
The above-mentioned further another 3D package configuration, wherein the at least one first semiconductor die is a high power consuming semiconductor die.
The above-mentioned further another 3D package configuration, further comprising a heat dissipating mechanism, wherein the heat dissipating mechanism is sandwiched between the top surface of the at least one first semiconductor die and the folded first flexible circuit board of the folded flexible circuit board structure.
In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details.
It is apparent that departures from specific designs and methods described and shown will suggest themselves to those skilled in the art and may be used without departing from the spirit and scope of the invention. The present invention is not restricted to the particular constructions described and illustrated, but should be construed to cohere with all modifications that may fall within the scope of the appended claims.
Embodiments Embodiment 1Please refer to
This present Embodiment 1 discloses a 3D package configuration 80 as shown in
The above-mentioned semiconductor package unit 50, wherein the semiconductor die 10 can be for example but not limited to a Central Processing Unit (CPU) die, a Graphics Processing Unit (GPU) die, a Digital Signal Processor (DSP) die, a Micro-Processing Unit (MPU) die, a Micro-Controlling Unit (MCU) die, a Dynamic Random Access Memory (DRAM) die, a Static Random Access Memory (SRAM) die, a Standard Logic IC die, an Application-Specific Integrated Circuit (ASIC) die, a sensing die with a specific sensing function, or a driving IC die.
The above-mentioned semiconductor package unit 50, wherein the first bonding pads 32 and the second bonding pads 34 are for example but not limited to solder balls or metallic bumps formed by a material selected from one of the group consisting of tin, tin alloys including tin/copper alloy, tin/ITO alloy, tin/silver alloy, tin/bismuth alloy and tin/lead alloy, and conductive polymers.
The above-mentioned semiconductor package unit 50, wherein the material of the flexible insulating substrate 22 is selected from for example but not limited to one of the group consisting of Polyester resin, Polyimide (PI), Modified Polyimide (MPI), Covalent Organic Framework (COF), Liquid Photo-Imageable (LPI)—Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and flexible epoxy bonded fiber-glass board, or combinations thereof.
The above-mentioned semiconductor package unit 50, wherein the circuit 24 of the flexible circuit board 20 can be a single-layered circuit or a multiple-layered circuit, and the insulating layer 26 overlaying the circuit 24 can also be a single-layered insulating layer or a multiple-layered insulating layer.
The above-mentioned semiconductor package unit 50, wherein the material of the circuit is selected from for example but not limited to one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof.
The above-mentioned semiconductor package unit 50 can be manufactured by for example but not limited to the processes as shown in
First, a flexible circuit board 20 as shown in
Next, as shown in
Furthermore, as shown in
Please refer to
This present Embodiment 2 discloses a 3D package configuration 1500 as shown in
The flexible circuit board 200 according to Embodiment 2 of this invention comprises one first semiconductor die 110 bonded to the first die bonding zone. However, the flexible circuit board 200 according to other embodiments of this invention can alternatively comprise more than one first semiconductor dies 110 bonded to the first die bonding zone if necessary.
As shown in
A plurality of second semiconductor dies 120 were bonded to the second die bonding zone formed on the first surface 200A. However, According to another embodiment of this invention, one second semiconductor die 120 can also optionally be bonded to the second die bonding zone formed on the first surface 200A if necessary.
The first semiconductor die 110 and the second semiconductor dies 120 of the 3D package configuration 1500 can respectively be for example but not limited to a CPU die, a GPU die, a DSP die, a MPU die, a MCU die, a DRAM die, a SRAM die, a Standard Logic IC die, an ASIC die for a special application, a sensing die with a specific sensing function, or a driving IC die.
The first die bonding pads 131, the second die bonding pads 132 and the lead frame bonding pads 136 of the 3D package configuration 1500 are for example but not limited to solder balls or metallic bumps formed by a material selected from one of the group consisting of tin, tin alloys including tin/copper alloy, tin/ITO alloy, tin/silver alloy, tin/bismuth alloy and tin/lead alloy, and conductive polymers.
The material for the flexible insulating substrate 220 of the 3D package configuration 1500 is selected from for example but not limited to one of the group consisting of Polyester resin, Polyimide (PI), Modified Polyimide (MPI), Covalent Organic Framework (COF), Liquid Photo-Imageable (LPI), Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and flexible epoxy bonded fiber-glass board, or combinations thereof.
The material for the circuit 240 of the 3D package configuration 1500 is selected from for example but not limited to one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof.
The above-mentioned 3D package configuration 1500, wherein the circuit 240 of the flexible circuit board 200 can be a single-layered circuit or a multiple-layered circuit, and the insulating layer 260 overlaying the circuit 240 can also be a single-layered insulating layer or a multiple-layered insulating layer.
According to another embodiment of this invention, additional adhesive layers can be coated on the first surface 200A of the flexible circuit board 200 or the second surface 200B of the flexible circuit board 200 to fasten the folded flexible circuit board structure 1500 vertically stacked on the lead frame 60.
Furthermore, as shown in
Please refer to
This present Embodiment 3 discloses a 3D package configuration 1600 as shown in
The flexible circuit board 200 according to Embodiment 3 of this invention comprises one first semiconductor die 110 bonded to the first die bonding zone. However, the flexible circuit board 200 according to other embodiments of this invention can alternatively comprise more than one first semiconductor dies 110 bonded to the first die bonding zone if necessary.
As shown in
A plurality of second semiconductor dies 120 were bonded to the second die bonding zone formed on the first surface 200A. However, According to another embodiment of this invention, one second semiconductor die 120 can also optionally be bonded to the second die bonding zone formed on the second surface 200B if necessary.
The first semiconductor die 110 and the second semiconductor dies 120 of the 3D package configuration 1600 can respectively be for example but not limited to a CPU die, a GPU die, a DSP die, a MPU die, a MCU die, a DRAM die, a SRAM die, a Standard Logic IC die, an ASIC die for a special application, a sensing die with a specific sensing function, or a driving IC die.
The first die bonding pads 131, the second die bonding pads 132 and the lead frame bonding pads 136 of the 3D package configuration 1600 are for example but not limited to solder balls or metallic bumps formed by a material selected from one of the group consisting of tin, tin alloys including tin/copper alloy, tin/ITO alloy, tin/silver alloy, tin/bismuth alloy and tin/lead alloy, and conductive polymers.
The material for the flexible insulating substrate 220 of the 3D package configuration 1600 is selected from for example but not limited to one of the group consisting of Polyester resin, Polyimide (PI), Modified Polyimide (MPI), Covalent Organic Framework (COF), Liquid Photo-Imageable (LPI), Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and flexible epoxy bonded fiber-glass board, or combinations thereof.
The material for the circuit 240 of the 3D package configuration 1600 is selected from for example but not limited to one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof.
The above-mentioned 3D package configuration 1600, wherein the circuit 240 of the flexible circuit board 200 can be a single-layered circuit or a multiple-layered circuit, and the insulating layer 260 overlaying the circuit 240 can also be a single-layered insulating layer or a multiple-layered insulating layer.
According to another embodiment of this invention, additional adhesive layers can be coated on the first surface 200A of the flexible circuit board 200 or the second surface 200B of the flexible circuit board 200 to fasten the folded flexible circuit board structure 1600 vertically stacked on the lead frame 60.
Furthermore, as shown in
Please refer
This present Embodiment 4 discloses a 3D package configuration 1700 as shown in
The flexible circuit board 200 according to Embodiment 4 of this invention comprises one first semiconductor die 110 bonded to the first die bonding zone. However, the flexible circuit board 200 according to other embodiments of this invention can alternatively comprise more than one first semiconductor dies 110 bonded to the first die bonding zone if necessary.
As shown in
The first semiconductor die 110 and the second semiconductor dies 120 of the 3D package configuration 1700 can respectively be for example but not limited to a CPU die, a GPU die, a DSP die, a MPU die, a MCU die, a DRAM die, a SRAM die, a Standard Logic IC die, an ASIC die for a special application, a sensing die with a specific sensing function, or a driving IC die.
The first die bonding pads 131, the second die bonding pads 132 and the lead frame bonding pads 136 of the 3D package configuration 1700 are for example but not limited to solder balls or metallic bumps formed by a material selected from one of the group consisting of tin, tin alloys including tin/copper alloy, tin/ITO alloy, tin/silver alloy, tin/bismuth alloy and tin/lead alloy, and conductive polymers.
The material for the flexible insulating substrate 220 of the 3D package configuration 1700 is selected from for example but not limited to one of the group consisting of Polyester resin, Polyimide (PI), Modified Polyimide (MPI), Covalent Organic Framework (COF), Liquid Photo-Imageable (LPI), Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and flexible epoxy bonded fiber-glass board, or combinations thereof.
The above-mentioned 3D package configuration 1700, wherein the circuit 240 of the flexible circuit board 200 can be a single-layered circuit or a multiple-layered circuit, and the insulating layer 260 overlaying the circuit 240 can also be a single-layered insulating layer or a multiple-layered insulating layer.
According to another embodiment of this invention, additional adhesive layers can be coated on the first surface 200A of the flexible circuit board 200 or the second surface 200B of the flexible circuit board 200 to fasten the folded flexible circuit board structure 1200 vertically stacked on the lead frame 60.
Furthermore, as shown in
Please refer to
This present Embodiment 5 discloses a 3D package configuration 1800 as shown in
The flexible circuit board 400 according to Embodiment 5 of this invention comprises one first semiconductor die 110 bonded to the first die bonding zone. However, the flexible circuit board 400 according to other embodiments of this invention can alternatively comprise more than one first semiconductor dies 110 bonded to the first die bonding zone if necessary.
As shown in
As shown in
The first semiconductor die 110, the second semiconductor die 120 and the third semiconductor die 130 of the 3D package configuration 1800 can respectively be for example but not limited to a CPU die, a GPU die, a DSP die, a MPU die, a MCU die, a DRAM die, a SRAM die, a Standard Logic IC die, an ASIC die for a special application, a sensing die with a specific sensing function, or a driving IC die.
The first die bonding pads 131, the second die bonding pads 132, the third die bonding pads 332, the first bonding pads 133, the second bonding pads 134, the third bonding pads 334 and the lead frame bonding pads 136 of the 3D package configuration 1800 are for example but not limited to solder balls or metallic bumps formed by a material selected from one of the group consisting of tin, tin alloys including tin/copper alloy, tin/ITO alloy, tin/silver alloy, tin/bismuth alloy and tin/lead alloy, and conductive polymers.
The material for the first flexible insulating substrate 225 and the second flexible insulating substrate 320 of the 3D package configuration 1800 is selected from for example but not limited to one of the group consisting of Polyester resin, Polyimide (PI), Modified Polyimide (MPI), Covalent Organic Framework (COF), Liquid Photo-Imageable (LPI), Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and flexible epoxy bonded fiber-glass board, or combinations thereof.
The material for the first circuit 245 and the second circuit 240 of the 3D package configuration 1800 is selected from for example but not limited to one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof.
The above-mentioned 3D package configuration 1800, wherein the first circuit 245 of the first flexible circuit board 250 and the second circuit 240 of the second flexible circuit board 300 can be a single-layered circuit or a multiple-layered circuit, and the first insulating layer 265 overlaying the first circuit 245 and the second insulating layer 360 overlaying the second circuit 240 can also be a single-layered insulating layer or a multiple-layered insulating layer.
According to another embodiment of this invention, additional adhesive layers can be coated on the first surface 250A and the second surface 250B of the first flexible circuit board 250, and/or the third surface 300A and the fourth surface 300B of the second flexible circuit board 300 to fasten the folded flexible circuit board structure 1300 vertically stacked on the lead frame 60.
Furthermore, as shown in
Please refer to
This present Embodiment 6 discloses a 3D package configuration 1900 as shown in
The flexible circuit boards 200 of this present Embodiment 6 comprises a first semiconductor die 110 bonded to the first die bonding zone, and a plurality of second semiconductor dies including 120A, 120B, 120C and 120D respectively bonded to each of the second die bonding zones. However, the flexible circuit board 200 according to other embodiments of this invention can alternatively comprise more than one first semiconductor dies 110 bonded to the first die bonding zone, and more than one second semiconductor dies 120A, 120B, 120C and 120D bonded to each of the second die bonding zones, if necessary.
As shown in
Alternatively, as shown in
Alternatively, as shown in
The first semiconductor die 110 and the second semiconductor dies 120A, 120B, 120C and 120D of the 3D package configurations 1900, 1900′ and 1900″ can respectively be for example but not limited to a CPU die, a GPU die, a DSP die, a MPU die, a MCU die, a DRAM die, a SRAM die, a Standard Logic IC die, an ASIC die for a special application, a sensing die with a specific sensing function, or a driving IC die.
The first die bonding pads 131, the second die bonding pads 132 and the lead frame bonding pads 136 of the 3D package configurations 1900, 1900′ and 1900″ are respectively for example but not limited to solder balls or metallic bumps formed by a material selected from one of the group consisting of tin, tin alloys including tin/copper alloy, tin/ITO alloy, tin/silver alloy, tin/bismuth alloy and tin/lead alloy, and conductive polymers.
The material for the flexible insulating substrate 220 of the 3D package configurations 1900, 1900′ and 1900″ can be selected from for example but not limited to one of the group consisting of Polyester resin, Polyimide (PI), Modified Polyimide (MPI), Covalent Organic Framework (COF), Liquid Photo-Imageable (LPI), Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and flexible epoxy bonded fiber-glass board, or combinations thereof.
The material for the circuit 240 of the 3D package configurations 1900, 1900′ and 1900″ is selected from for example but not limited to one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof.
The above-mentioned 3D package configurations 1900, 1900′ and 1900″, wherein the circuit 240 of the flexible circuit board 200 can be a single-layered circuit or a multiple-layered circuit, and the insulating layer 260 overlaying the circuit 240 can also be a single-layered insulating layer or a multiple-layered insulating layer.
According to another embodiment of this invention, additional adhesive layers can be coated on the first surface 200A or the second surface 200B of the flexible circuit board 200 of the 3D package configurations 1900, 1900′ and 1900″ to fasten the folded flexible circuit board structures 1400, 1400′ and 1400″ vertically stacked on the lead frame 60.
Embodiment 7Please refer to FIGS. A-1, 7A-2, 7B-7C, and
This present Embodiment 7 discloses a 3D configuration 2000 as shown in FIG, 7D, comprising a lead frame 60; and a folded flexible circuit board structure 1510 vertically stacked on the lead frame 60 and electrically connected therewith. The folded flexible circuit board structure 1510 comprises a cross-shaped flexible circuit board 200 as shown in
The flexible circuit boards 200 of this present Embodiment 7 comprises a first semiconductor die 110 bonded to the first die bonding zone, and a plurality of second semiconductor dies including 120A, 120B, 120C and 120D respectively bonded to each of the second die bonding zones. However, the flexible circuit board 200 according to other embodiments of this invention can alternatively comprise more than one first semiconductor dies 110 bonded to the first die bonding zone, and more than one second semiconductor dies 120A, 120B, 120C and 120D bonded to each of the second die bonding zones, if necessary.
As shown in
Alternatively, as shown in
Alternatively, as shown in
The first semiconductor die 110 and the second semiconductor dies 120A, 120B, 120C and 120D of the 3D package configurations 2000, 2000′ and 2000″ can respectively be for example but not limited to a CPU die, a GPU die, a DSP die, a MPU die, a MCU die, a DRAM die, a SRAM die, a Standard Logic IC die, an ASIC die for a special application, a sensing die with a specific sensing function, or a driving IC die.
The first die bonding pads 131, the second die bonding pads 132 and the lead frame bonding pads 136 of the 3D package configurations 2000, 2000′ and 2000″ are respectively for example but not limited to solder balls or metallic bumps formed by a material selected from one of the group consisting of tin, tin alloys including tin/copper alloy, tin/ITO alloy, tin/silver alloy, tin/bismuth alloy and tin/lead alloy, and conductive polymers.
The material for the flexible insulating substrate 220 of the 3D package configurations 2000, 2000′ and 2000″ can be selected from for example but not limited to one of the group consisting of Polyester resin, Polyimide (PI), Modified Polyimide (MPI), Covalent Organic Framework (COF), Liquid Photo-Imageable (LPI), Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and flexible epoxy bonded fiber-glass board, or combinations thereof.
The material for the circuit 240 of the 3D package configurations 2000, 2000′ and 2000″ is selected from for example but not limited to one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof.
The above-mentioned 3D package configurations 2000, 2000′ and 2000″, wherein the circuit 240 of the flexible circuit board 200 can be a single-layered circuit or a multiple-layered circuit, and the insulating layer 260 overlaying the circuit 240 can also be a single-layered insulating layer or a multiple-layered insulating layer.
According to another embodiment of this invention, additional adhesive layers can be coated on the first surface 200A or the second surface 200B of the flexible circuit board 200 of the 3D package configurations 2000, 2000′ and 2000″ to fasten the folded flexible circuit board structures 1510, 1510′ and 1510″ vertically stacked on the lead frame 60.
Embodiment 8Please refer to
This present Embodiment 8 discloses a 3D package configuration 2100 as shown in
The flexible circuit boards 200 of this present Embodiment 8 comprises a first semiconductor die 110 bonded to the first die bonding zone, and a plurality of second semiconductor dies including 120A, 120B and 120C respectively bonded to each of the second die bonding zones. However, the flexible circuit board 200 according to other embodiments of this invention can alternatively comprise more than one first semiconductor dies 110 bonded to the first die bonding zone, and more than one second semiconductor dies 120A, 120B, and 120C bonded to each of the second die bonding zones, if necessary.
As shown in
Alternatively, as shown in
Alternatively, as shown in
The first semiconductor die 110 and the second semiconductor dies 120A, 120B and 120C of the 3D package configurations 2100, 2100′ and 2100″ can respectively be for example but not limited to a CPU die, a GPU die, a DSP die, a MPU die, a MCU die, a DRAM die, a SRAM die, a Standard Logic IC die, an ASIC die for a special application, a sensing die with a specific sensing function, or a driving IC die.
The first die bonding pads 131, the second die bonding pads 132 and the lead frame bonding pads 136 of the 3D package configurations 2100, 2100′ and 2100″ are respectively for example but not limited to solder balls or metallic bumps formed by a material selected from one of the group consisting of tin, tin alloys including tin/copper alloy, tin/ITO alloy, tin/silver alloy, tin/bismuth alloy and tin/lead alloy, and conductive polymers.
The material for the flexible insulating substrate 220 of the 3D package configurations 2100, 2100′ and 2100″ can be selected from for example but not limited to one of the group consisting of Polyester resin, Polyimide (PI), Modified Polyimide (MPI), Covalent Organic Framework (COF), Liquid Photo-Imageable (LPI), Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and flexible epoxy bonded fiber-glass board, or combinations thereof.
The material for the circuit 240 of the 3D package configurations 2100, 2100′ and 2100″ is selected from for example but not limited to one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof.
The above-mentioned 3D package configurations 2100, 2100′ and 2100″, wherein the circuit 240 of the flexible circuit board 200 can be a single-layered circuit or a multiple-layered circuit, and the insulating layer 260 overlaying the circuit 240 can also be a single-layered insulating layer or a multiple-layered insulating layer.
According to another embodiment of this invention, additional adhesive layers can be coated on the first surface 200A or the second surface 200B of the flexible circuit board 200 of the 3D package configurations 2100, 2100′ and 2100″ to fasten the folded flexible circuit board structures 1610, 1610′ and 1610″ vertically stacked on the lead frame 60.
Embodiment 9Please refer to
This present Embodiment 9 discloses a 3D configuration 2200 as shown in
The flexible circuit boards 200 of this present Embodiment 9 comprises a first semiconductor die 110 bonded to the first die bonding zone, and a plurality of second semiconductor dies including 120A, 120B and 120C respectively bonded to each of the second die bonding zones. However, the flexible circuit board 200 according to other embodiments of this invention can alternatively comprise more than one first semiconductor dies 110 bonded to the first die bonding zone, and more than one second semiconductor dies 120A, 120B, and 120C bonded to each of the second die bonding zones, if necessary.
As shown in
Alternatively, as shown in
Alternatively, as shown in
The first semiconductor die 110 and the second semiconductor dies 120A, 120B and 120C of the 3D package configurations 2200, 2200′ and 2200″ can respectively be for example but not limited to a CPU die, a GPU die, a DSP die, a MPU die, a MCU die, a DRAM die, a SRAM die, a Standard Logic IC die, an ASIC die for a special application, a sensing die with a specific sensing function, or a driving IC die.
The first die bonding pads 131, the second die bonding pads 132 and the lead frame bonding pads 136 of the 3D package configurations 2200, 2200′ and 2200″ are respectively for example but not limited to solder balls or metallic bumps formed by a material selected from one of the group consisting of tin, tin alloys including tin/copper alloy, tin/ITO alloy, tin/silver alloy, tin/bismuth alloy and tin/lead alloy, and conductive polymers.
The material for the flexible insulating substrate 220 of the 3D package configurations 2200, 2200′ and 2200″ can be selected from for example but not limited to one of the group consisting of Polyester resin, Polyimide (PI), Modified Polyimide (MPI), Covalent Organic Framework (COF), Liquid Photo-Imageable (LPI), Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and flexible epoxy bonded fiber-glass board, or combinations thereof.
The material for the circuit 240 of the 3D package configurations 2200, 2200′ and 2200″ is selected from for example but not limited to one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof.
The above-mentioned 3D package configurations 2200, 2200′ and 2200″, wherein the circuit 240 of the flexible circuit board 200 can be a single-layered circuit or a multiple-layered circuit, and the insulating layer 260 overlaying the circuit 240 can also be a single-layered insulating layer or a multiple-layered insulating layer.
According to another embodiment of this invention, additional adhesive layers can be coated on the first surface 200A or the second surface 200B of the flexible circuit board 200 of the 3D package configurations 2200, 2200′ and 2200″ to fasten the folded flexible circuit board structures 1710, 1710′ and 1710″ vertically stacked on the lead frame 60.
Embodiment 10Please refer to
This present Embodiment 10 discloses a 3D package configuration 2300 as shown in
The flexible circuit boards 200 of this present Embodiment 10 comprises a first semiconductor die 110 bonded to the first die bonding zone, and a plurality of second semiconductor dies including 120A, 120B, 120C and 120D respectively bonded to each of the second die bonding zones. However, the flexible circuit board 200 according to other embodiments of this invention can alternatively comprise more than one first semiconductor dies 110 bonded to the first die bonding zone, and more than one second semiconductor dies 120A, 120B, 120C and 120D bonded to each of the second die bonding zones, if necessary.
As shown in
Alternatively, as shown in
Alternatively, as shown in
The first semiconductor die 110 and the second semiconductor dies 120A, 120B, 120C and 120D of the 3D package configurations 2300, 2300′ and 2300″ can respectively be for example but not limited to a CPU die, a GPU die, a DSP die, a MPU die, a MCU die, a DRAM die, a SRAM die, a Standard Logic IC die, an ASIC die for a special application, a sensing die with a specific sensing function, or a driving IC die.
The first die bonding pads 131, the second die bonding pads 132 and the lead frame bonding pads 136 of the 3D package configurations 2300, 2300′ and 2300″ are respectively for example but not limited to solder balls or metallic bumps formed by a material selected from one of the group consisting of tin, tin alloys including tin/copper alloy, tin/ITO alloy, tin/silver alloy, tin/bismuth alloy and tin/lead alloy, and conductive polymers.
The material for the flexible insulating substrate 220 of the 3D package configurations 2300, 2300′ and 2300″ can be selected from for example but not limited to one of the group consisting of Polyester resin, Polyimide (PI), Modified Polyimide (MPI), Covalent Organic Framework (COF), Liquid Photo-Imageable (LPI), Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and flexible epoxy bonded fiber-glass board, or combinations thereof.
The material for the circuit 240 and the antenna circuit 240′ of the 3D package configurations 2300, 2300′ and 2300″ is selected from for example but not limited to one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof.
The above-mentioned 3D package configurations 2300, 2300′ and 2300″, wherein the circuit 240 and the antenna circuit 240′ of the flexible circuit board 200 can be a single-layered circuit or a multiple-layered circuit, and the insulating layer 260 overlaying the circuit 240 and the antenna circuit 240′ can also be a single-layered insulating layer or a multiple-layered insulating layer.
According to another embodiment of this invention, additional adhesive layers can be coated on the first surface 200A or the second surface 200B of the flexible circuit board 200 of the 3D package configurations 2300, 2300′ and 2300″ to fasten the folded flexible circuit board structures 1810, 1810′ and 1810″ vertically stacked on the lead frame 60.
Embodiment 11Please refer to
This present Embodiment 11 discloses a 3D package configuration 2400 as shown in
The flexible circuit boards 200 of this present Embodiment 11 comprises a first semiconductor die 110 bonded to the first die bonding zone, and a plurality of second semiconductor dies including 120A, 120B, 120C and 120D respectively bonded to each of the second die bonding zones. However, the flexible circuit board 200 according to other embodiments of this invention can alternatively comprise more than one first semiconductor dies 110 bonded to the first die bonding zone, and more than one second semiconductor dies 120A, 120B, 120C and 120D be bonded to each of the second die bonding zones, if necessary.
As shown in
Alternatively, as shown in
Alternatively, as shown in
The first semiconductor die 110 and the second semiconductor dies 120A, 120B, 120C and 120D of the 3D package configurations 2400, 2400′ and 2400″ can respectively be for example but not limited to a CPU die, a GPU die, a DSP die, a MPU die, a MCU die, a DRAM die, a SRAM die, a Standard Logic IC die, an ASIC die for a special application, a sensing die with a specific sensing function, or a driving IC die.
The first die bonding pads 131, the second die bonding pads 132 and the lead frame bonding pads 136 of the 3D package configurations 2400, 2400′ and 2400″ are respectively for example but not limited to solder balls or metallic bumps formed by a material selected from one of the group consisting of tin, tin alloys including tin/copper alloy, tin/ITO alloy, tin/silver alloy, tin/bismuth alloy and tin/lead alloy, and conductive polymers.
The material for the flexible insulating substrate 220 of the 3D package configurations 2400, 2400′ and 2400″ can be selected from for example but not limited to one of the group consisting of Polyester resin, Polyimide (PI), Modified Polyimide (MPI), Covalent Organic Framework (COF), Liquid Photo-Imageable (LPI), Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and flexible epoxy bonded fiber-glass board, or combinations thereof.
The material for the circuit 240 and the antenna circuit 240′ of the 3D package configurations 2400, 2400′ and 2400″ is selected from for example but not limited to one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof.
The above-mentioned 3D package configurations 2400, 2400′ and 2400″, wherein the circuit 240 and the antenna circuit 240′ of the flexible circuit board 200 can be a single-layered circuit or a multiple-layered circuit, and the insulating layer 260 overlaying the circuit 240 and the antenna circuit 240′ can also be a single-layered insulating layer or a multiple-layered insulating layer.
According to another embodiment of this invention, additional adhesive layers can be coated on the first surface 200A or the second surface 200B of the flexible circuit board 200 of the 3D package configurations 2400, 2400′ and 2400″ to fasten the folded flexible circuit board structures 1850, 1850′ and 1850″ vertically stacked on the lead frame 60.
Embodiment 12Please refer to
The present Embodiment 12 discloses a 3D package configuration 2500 as shown in
As shown in
Alternatively, as shown in
Alternatively, as shown in
The first semiconductor die 110 and the second semiconductor dies 120A, 120B, 120C and 120D of the 3D package configurations 2500, 2500′ and 2500″ can respectively be for example but not limited to a CPU die, a GPU die, a DSP die, a MPU die, a MCU die, a DRAM die, a SRAM die, a Standard Logic IC die, an ASIC die for a special application, a sensing die with a specific sensing function, or a driving IC die.
The first die bonding pads 131, the second die bonding pads 132 and the lead frame bonding pads 136 of the 3D package configurations 2500, 2500′ and 2500″ are respectively for example but not limited to solder balls or metallic bumps formed by a material selected from one of the group consisting of tin, tin alloys including tin/copper alloy, tin/ITO alloy, tin/silver alloy, tin/bismuth alloy and tin/lead alloy, and conductive polymers.
The material for the flexible insulating substrate 220 of the 3D package configurations 2500, 2500′ and 2500″ can be selected from for example but not limited to one of the group consisting of Polyester resin, Polyimide (PI), Modified Polyimide (MPI), Covalent Organic Framework (COF), Liquid Photo-Imageable (LPI), Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and flexible epoxy bonded fiber-glass board, or combinations thereof.
The material for the circuit 240 and the antenna circuit 240′ of the 3D package configurations 2500, 2500′ and 2500″ is selected from for example but not limited to one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof.
The above-mentioned 3D package configurations 2500, 2500′ and 2500″, wherein the circuit 240 and the antenna circuit 240′ of the flexible circuit board 200 can be a single-layered circuit or a multiple-layered circuit, and the insulating layer 260 overlaying the circuit 240 and the antenna circuit 240′ can also be a single-layered insulating layer or a multiple-layered insulating layer.
According to another embodiment of this invention, additional adhesive layers can be coated on the first surface 200A or the second surface 200B of the flexible circuit board 200 of the 3D package configurations 2500, 2500′ and 2500″ to fasten the folded flexible circuit board structures 1910, 1910′ and 1910″ vertically stacked on the lead frame 60.
Embodiment 13Please refer to
This present Embodiment 13 discloses a 3D package configuration 2600 as shown in
Moreover, the second semiconductor die 120B bonded to one of the second chip bonding regions adjacent to a terminal of the flexible circuit board 200 was a tel-communication chip, and the antenna region as shown in
As shown in
Alternatively, As shown in
Alternatively, As shown in
The first semiconductor die 110 and the second semiconductor dies 120A, 120B, 120C and 120D of the 3D package configurations 2600, 2600′ and 2600″ can respectively be for example but not limited to a CPU die, a GPU die, a DSP die, a MPU die, a MCU die, a DRAM die, a SRAM die, a Standard Logic IC die, an ASIC die for a special application, a sensing die with a specific sensing function, or a driving IC die.
The first die bonding pads 131, the second die bonding pads 132 and the lead frame bonding pads 136 of the 3D package configurations 2600, 2600′ and 2600″ are respectively for example but not limited to solder balls or metallic bumps formed by a material selected from one of the group consisting of tin, tin alloys including tin/copper alloy, tin/ITO alloy, tin/silver alloy, tin/bismuth alloy and tin/lead alloy, and conductive polymers.
The material for the flexible insulating substrate 220 of the 3D package configurations 2600, 2600′ and 2600″ can be selected from for example but not limited to one of the group consisting of Polyester resin, Polyimide (PI), Modified Polyimide (MPI), Covalent Organic Framework (COF), Liquid Photo-Imageable (LPI), Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and flexible epoxy bonded fiber-glass board, or combinations thereof.
The material for the circuit 240 and the antenna circuit 240′ of the 3D package configurations 2600, 2600′ and 2600″ is selected from for example but not limited to one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof.
The above-mentioned 3D package configurations 2600, 2600′ and 2600″, wherein the circuit 240 and the antenna circuit 240′ of the flexible circuit board 200 can be a single-layered circuit or a multiple-layered circuit, and the insulating layer 260 overlaying the circuit 240 can also be a single-layered insulating layer or a multiple-layered insulating layer.
According to another embodiment of this invention, additional adhesive layers can be coated on the first surface 200A or the second surface 200B of the flexible circuit board 200 of the 3D package configurations 2600, 2600′ and 2600″ to fasten the folded flexible circuit board structures 1950, 1950′ and 1950″ vertically stacked on the lead frame 60.
As described in the above Embodiments, a novel 3D package configuration can be obtained by stacking a plurality of semiconductor package units or a folded flexible circuit board structure on a lead frame and electrically connected therewith based on the foldable characteristics of the flexible circuit board, and the high temperature resistance of the flexible circuit board which is suitable for insulating layer process, metal layer process, photolithography process, etching and development process, to make conventional semiconductor dies such as CPU dies, GPU dies, DRAM dies, SRAM dies, tel-communication dies, standard logic IC dies, ASIC dies, various sensing IC dies, various driving IC and other semiconductor dies with various functions be bonded on one die and/or two side of a flexible circuit board and electrically connected therewith in advance.
Although particular embodiments have been shown and described, it should be understood that the above discussion is not intended to limit the present invention to these embodiments. Persons skilled in the art will understand that various changes and modifications may be made without departing from the scope of the present invention as literally and equivalently covered by the following claims.
Claims
1. A 3D package configuration, comprising: wherein, the first surface of the folded flexible circuit board comprises a plurality of first bonding pads electrically connected to the circuit, and the bottom surface of the semiconductor die is bonded to the first surface and electrically connected to the folded flexible circuit board through the first bonding pads, and the second surface and the flexible insulating substrate of the folded flexible circuit board corresponding to the top surface of the semiconductor die respectively comprise a plurality of second bonding pads and a plurality of first conductive holes electrically connected to the circuit, and the second surface and the flexible insulating substrate of the folded flexible circuit board corresponding to the bottom surface of the semiconductor die respectively comprise a plurality of third bonding pads and a plurality of second conductive holes electrically connected to the circuit, and each of the third bonding pads is electrically connected to the circuit through one of the second conductive holes; wherein, the semiconductor package units are vertically and sequentially stacked to interconnect with each other by bonding the third bonding pads of one of the semiconductor package unit to the second bonding pads of another adjacent one of the semiconductor package units, and the bottommost one of the semiconductor package units is directly bonded to the lead frame and electrically connected therewith through the third bonding pads.
- a lead frame; and
- a plurality of semiconductor package units vertically stacked on the lead frame in sequence, wherein the semiconductor package units are electrically connected to each other and electrically connected therewith, and each of the semiconductor package units comprises: a semiconductor die with a top surface and a bottom surface opposite to each other, and a plurality of side surfaces adjacent to the top surface and the bottom surface; and a folded flexible circuit board with a first surface and a second surface opposite to each other, wherein the bottom surface of the semiconductor die is bonded to the first surface and electrically connected to the folded flexible circuit board, and the first surface of the folded flexible circuit board is attached onto the top surface, the bottom surface and one of the side surfaces of the semiconductor die; wherein the folded flexible circuit board comprises: a flexible insulating substrate; a circuit formed on a surface of the flexible insulating substrate; and an insulating layer overlaying the circuit
2. (canceled)
3. The 3D package configuration as claimed in claim 1, wherein the material of the flexible insulating substrate is selected from one of the group consisting of Polyester resin, Polyimide (PI), Modified Polyimide (MPI), Covalent Organic Framework (COF), Liquid Photo-Imageable (LPI), Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and flexible epoxy bonded fiber-glass board, or combinations thereof
4. The 3D package configuration as claimed in claim 1, wherein the material of the circuit is selected from one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof.
5. The 3D package configuration as claimed in claim 1, wherein one of the semiconductor package units comprises a high power consuming semiconductor die.
6. The 3D package configuration as claimed in claim 5, further comprising a heat dissipating mechanism, wherein the heat dissipating mechanism is sandwiched between the top surface of the high power consuming semiconductor die and first surface of the folded flexible circuit board attached on the top surface of the high power consuming semiconductor die.
7. A 3D package configuration, comprising: wherein, the at least one second semiconductor die is vertically stacked above the at least one first semiconductor die by folding the flexible circuit board to form the folded flexible circuit board structure vertically stacked on the lead frame and electrically connected therewith through lead frame bonding pads.
- a lead frame; and
- a folded flexible circuit board structure vertically stacked on the lead frame and electrically connected therewith, comprising: a flexible circuit board with a first surface and a second surface opposite to each other, wherein the flexible circuit board having a first die bonding zone formed on the first surface and at least one second die bonding zone formed on the first surface and/or the second surface; at least one first semiconductor die bonded to the first die bonding zone and electrically connected to the flexible circuit board; and at least one second semiconductor die bonded to the at least one second die bonding zone and electrically connected to the flexible circuit board;
8. The 3D package configuration as claimed in claim 7, comprising a plurality of second semiconductor dies spaced with each other, and a plurality of second die bonding zones formed on the first surface and/or the second surface of the flexible circuit board, wherein each of the second semiconductor dies bonded on each of the second semiconductor die bonding zones and electrically connected to the flexible circuit board through each of the second die bonding pads in each of the second die bonding zones, and the second semiconductor die are vertically and sequentially stacked above the at least one first semiconductor die by folding the flexible circuit board, wherein the first die bonding zone overlaps with the second die bonding zones.
9. The 3D package configuration as claimed in claim 8, wherein the second die bonding zones are concurrently formed on the first surface of the flexible circuit board or concurrently formed on the second surface of the flexible circuit board.
10. The 3D package configuration as claimed in claim 8, wherein the second die bonding zones are alternatively formed on the first surface and the second surface of the flexible circuit board.
11. The 3D package configuration as claimed in claim 7, wherein the flexible circuit board comprises: wherein, the first die bonding zone comprises a plurality of first die bonding pads electrically connected to the circuit to make the first semiconductor die electrically connected to the circuit through the first die bonding pads, and the at least one second die bonding zone comprises a plurality of second die bonding pads electrically connected to the circuit to make the at least one second semiconductor die electrically connected to the circuit through the second die bonding pads, and a plurality of lead frame bonding pads under the first die bonding zone are formed on the second surface of the flexible circuit board, and each of the lead frame bonding pads is electrically connected to each of the first die bonding pads corresponding thereof through a conductive hole.
- a flexible insulating substrate;
- a circuit formed on a surface of the flexible insulating substrate; and
- an insulating layer overlaying the circuit;
12. The 3D package configuration as claimed in claim 11, wherein the material of the flexible insulating substrate is selected from one of the group consisting of Polyester resin, Polyimide (PI), Modified Polyimide (MPI), Covalent Organic Framework (COF), Liquid Photo-Imageable (LPI), Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and flexible epoxy bonded fiber-glass board, or combinations thereof
13. The 3D package configuration as claimed in claim 11, wherein the material of the circuit is selected from one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof
14. The 3D package configuration as claimed in claim 11, wherein one of the second semiconductor dies bonded to one of the second chip bonding regions adjacent to a terminal of the flexible circuit board is a tel-communication chip, and an antenna region is formed between the terminal of the flexible circuit board and the tel-communication chip, wherein the antenna region comprises an integrated antenna circuit formed on the insulating substrate of the flexible circuit board and overlayed by the insulating layer of the flexible circuit board, and the tel-communication chip is electrically connected to the integrated antenna circuit through the second chip bonding pads.
15. The 3D package configuration as claimed in claim 14, wherein the material of the integrated antenna circuit is selected from one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof
16. The 3D package configuration as claimed in claim 7, wherein one of the at least one first semiconductor die is a high power consuming semiconductor die.
17. The 3D package configuration as claimed in claim 16, further comprising a heat dissipating mechanism, wherein the heat dissipating mechanism is sandwiched between the top surface of the at least one first semiconductor die and the folded flexible circuit board of the folded flexible circuit board structure.
18. A 3D package configuration, comprising: wherein, the at least one third semiconductor die and the at least one second semiconductor die are alternatively vertically stacked above the at least one first semiconductor die by folding the first flexible circuit board and the second flexible circuit board to make the first die bonding zone, the at least one second die bonding zone and the at least one third die bonding zone overlap with each other to form the folded flexible circuit board structure, and a plurality of lead frame bonding pads under the first die bonding zone are formed on the third surface of the second flexible circuit board, and each of the lead frame bonding pads is electrically connected to each of the first die bonding pads corresponding thereof through a conductive hole; wherein, the folded flexible circuit board structure is vertically stacked on the lead frame and electrically connected therewith through the lead frame bonding pads.
- a lead frame; and
- a folded flexible circuit board structure vertically stacked on the lead frame and electrically connected therewith, comprising: a first flexible circuit board with a first surface and a second surface opposite to each other, wherein the first flexible circuit board includes a first die bonding zone and at least one second die bonding zone formed on the first surface; at least one first semiconductor die bonded to the first die bonding zone and electrically connected to the first flexible circuit board; at least one second semiconductor die bonded to the at least one second die bonding zone and electrically connected to the first flexible circuit board; a second flexible circuit board with a third surface and a fourth surface opposite to each other, wherein the second flexible circuit board includes at least one third die bonding zone formed on the third surface; and at least one third semiconductor die bonded to the at least one third die bonding zone and electrically connected to the second flexible circuit board;
19. The 3D package configuration as claimed in claim 18, comprising a plurality of second semiconductor dies spaced with each other, and a plurality of second chip bonding regions formed on the first surface of the first flexible circuit board, wherein each of the second semiconductor dies is bonded to each of the second chip bonding region and electrically connected to the first flexible circuit board through a second bonding pad in each of the second chip bonding region.
20. The 3D package configuration as claimed in claim 18, comprising a plurality of third semiconductor dies spaced with each other, and a plurality of third chip bonding regions formed on the third surface of the second flexible circuit board, wherein each of the third semiconductor dies is bonded to one of the third chip bonding regions and electrically connected to the second flexible circuit board through a third bonding pad in each of the third bonding regions.
21. The 3D package configuration as claimed in claim 18, wherein the first flexible circuit board comprises a plurality of first bonding pads and a plurality of second bonding pads respectively formed on the second surface corresponding to the first die bonding zone and the at least one second die bonding zone, and the second flexible circuit board comprises a plurality of third bonding pads formed on the fourth surface corresponding to the at least one third die bonding zone, and the first flexible circuit is joined with the second flexible circuit board to generate a foldable flexible circuit board by bonding the first bonding pads and the second pads formed on the second surface of the first flexible circuit board to the third bonding pads formed on the fourth surface of the second flexible circuit board.
22. The 3D package configuration as claimed in claim 18, wherein the first flexible circuit board comprises: wherein, the first die bonding zone comprises a plurality of first bonding pads electrically connected to the first circuit to make the at least one first semiconductor die electrically connected to the first circuit through the first bonding pads, and the at least one second die bonding zone comprises a plurality of second die bonding pads electrically connected to the first circuit to make the at least one second semiconductor die electrically connected to the first circuit through the second die bonding pads.
- a first flexible insulating substrate;
- a first circuit formed on a surface of the first flexible insulating substrate; and
- a first insulating layer overlaying the first circuit;
23. The 3D package configuration as claimed in claim 22, wherein the material of the first flexible insulating substrate is selected from one of the group consisting of Polyester resin, Polyimide (PI), Modified Polyimide (MPI), Covalent Organic Framework (COF), Liquid Photo-Imageable (LPI), Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and flexible epoxy bonded fiber-glass board, or combinations thereof.
24. The 3D package configuration as claimed in claim 22, wherein the material of the first circuit is selected from one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof.
25. The 3D package configuration as claimed in claim 18, wherein the second flexible circuit board comprises: wherein, the at least one third die bonding zone is arranged to interlace with the first die bonding zone and the least one second die bonding zone, and the at least one third die bonding zone comprises a plurality of third bonding pads electrically connected to the second circuit to make the at least one third semiconductor die electrically connected to the second circuit through the third bonding pads.
- a second flexible insulating substrate;
- a second circuit formed on a surface of the second flexible insulating substrate; and
- a second insulating layer overlaying the second circuit;
26. The 3D package configuration as claimed in claim 25, wherein the material of the second flexible insulating substrate is selected from one of the group consisting of Polyester resin, Polyimide (PI), Modified Polyimide (MPI), Covalent Organic Framework (COF), Liquid Photo-Imageable (LPI), Liquid Crystal Polymer (LCP), Polytetrafluoroethylene (PTFE) and flexible epoxy bonded fiber-glass board, or combinations thereof.
27. The 3D package configuration as claimed in claim 25, wherein the material of the second circuit is selected from one of the group consisting of copper, copper alloy, tinned copper, tin alloy, aluminum, aluminum alloys, gold and silver, or combinations thereof.
28. The 3D package configuration as claimed in claim 18, wherein the at least one first semiconductor die is a high power consuming semiconductor die.
29. The 3D package configuration as claimed in claim 28, further comprising a heat dissipating mechanism, wherein the heat dissipating mechanism is sandwiched between the top surface of the at least one first semiconductor die and the folded first flexible circuit board of the folded flexible circuit board structure.
Type: Application
Filed: Jan 26, 2021
Publication Date: Jun 23, 2022
Inventors: Tung-Po Sung (Taoyuan), Chang-Cheng Lo (Taoyuan)
Application Number: 17/158,080