TECHNOLOGIES FOR MOUNTING DISPLAY DRIVER INTEGRATED CIRCUIT CHIPS ON DISPLAY PANELS
A display panel includes a plastic substrate and a first inner lead bonding (ILB) electrode on the plastic substrate. The first ILB electrode includes a first bonding segment, a second bonding segment, and a first connection segment. The first bonding segment is extended in a first direction oblique to a vertical direction of the display panel. The first connection segment is configured to provide an electrical connection between the first bonding segment and the second bonding segment. The first bonding segment is configured to be bonded to a first display driver integrated circuit (DDIC) chip, and the second bonding segment is configured to be bonded to a second DDIC chip configured differently from the first DDIC chip.
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The disclosed technology generally relates to technologies for mounting display driver integrated circuit (DDIC) chips on display panels.
BACKGROUNDA display module may include a display panel and a DDIC chip mounted on the display panel. In typical implementations, electrodes are disposed on the display panel, and bumps of the DDIC chip are bonded to the electrodes to achieve electrical connections between the display panel and the DDIC chip. The electrodes disposed on the display panel are designed to match the layout of the bumps of the DDIC chip.
SUMMARYThis summary is provided to introduce in a simplified form a selection of concepts that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.
In one or more embodiments, a display panel is provided. The display panel includes a plastic substrate and a first inner lead bonding (ILB) electrode on the plastic substrate. The first ILB electrode includes a first bonding segment, a second bonding segment, and a first connection segment. The first bonding segment is extended in a first direction oblique to a vertical direction of the display panel. The first connection segment is configured to provide an electrical connection between the first bonding segment and the second bonding segment. The first bonding segment is configured to be bonded to a first display driver integrated circuit (DDIC) chip, and the second bonding segment is configured to be bonded to a second DDIC chip configured differently from the first DDIC chip.
In one or more embodiments, a method for preparing display modules is provided. The method includes preparing a first display panel and a second display panel of the same configuration. A respective one of the first display panel and the second display panel includes a plastic substrate and a first ILB electrode on the plastic substrate. The first ILB electrode includes a first bonding segment, a second bonding segment, and a first connection segment. The first bonding segment is extended in a first direction oblique to a vertical direction of the respective one of the first display panel and the second display panel. The first connection segment is configured to provide an electrical connection between the first bonding segment and the second bonding segment. The method further includes bonding a first bump of a first DDIC chip to the first bonding segment of the first display panel. The method further includes bonding a second bump of a second DDIC chip to the second bonding segment of the second display panel. The second DDIC chip is configured differently from the first DDIC chip.
In one or more embodiments, a display module is provided. The display module includes a display panel and a product DDIC chip bonded on the display panel. The display panel includes a plastic substrate and a first ILB electrode on the plastic substrate. The first ILB electrode includes a first bonding segment, a second bonding segment, and a first connection segment. The first bonding segment is extended in a first direction oblique to a vertical direction of the display panel. The first connection segment is configured to provide an electrical connection between the first bonding segment and the second bonding segment. The first bonding segment is configured to be bonded to a first DDIC chip, and the second bonding segment is configured to be bonded to a second DDIC chip configured differently from the first DDIC chip. A bump of the product DDIC chip is bonded to a selected one of the first bonding segment and the second bonding segment.
Other aspects of the embodiments will be apparent from the following description and the appended claims.
So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments, and are therefore not to be considered limiting of inventive scope, as the disclosure may admit to other equally effective embodiments.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized in other embodiments without specific recitation. Suffixes may be attached to reference numerals for distinguishing identical elements from each other. The drawings referred to herein should not be understood as being drawn to scale unless specifically noted. Also, the drawings are often simplified and details or components omitted for clarity of presentation and explanation. The drawings and discussion serve to explain principles discussed below, where like designations denote like elements.
DETAILED DESCRIPTIONThe following detailed description is merely exemplary in nature and is not intended to limit the disclosure or the application and uses of the disclosure. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding background, summary, or the following detailed description.
A display module may include a display panel and a display driver integrated circuit (DDIC) chip configured to drive the display panel. It is noted that the DDIC chip referred herein may be configured to provide one or more other functionalities in addition to the driving of the display panel. For example, the DDIC chip may be configured to process resulting signals received from sensor electrodes disposed in or over the display panel for capacitive proximity sensing.
The DDIC chip may be mounted or bonded on the display panel with a surface mount technology. In one implementation, bumps of the DDIC chip are bonded to corresponding electrodes disposed on the display panel to achieve electrical connections between the DDIC chip and the display panel.
In recent years, flexible or foldable display panels have become popular. One approach to make a display panel flexible is to use a plastic substrate on which display elements (e.g., organic light emitting diodes (OLED) and liquid crystal (LC) cells) are disposed. The surface mount technology for mounting integrated circuits on plastic substrates is often referred to as chip-on-plastic (COP) technology.
One issue may be compatibility between display panels and DDIC chips. To achieve electrical connections between a display panel and a DDIC chip, the display panel is dedicatedly designed to match the layout of the bumps of the DDIC chip. This may make the display panel incompatible to a differently-configured DDIC chip. Conventionally, a display panel is dedicatedly designed for each DDIC chip product, undesirably increasing the cost of the display module.
Another issue may be increased thermal expansion of the plastic substrate during the mounting process. A plastic substrate exhibits a larger thermal expansion than a DDIC chip, which usually includes a silicon substrate, when the plastic substrate is heated during the mounting process. The increased thermal expansion of the plastic substrate may cause larger displacements of the electrodes on the display panel to be bonded to the bumps of the DDIC chip, making it difficult to align the bumps of the DDIC chip with the electrodes on the display panel.
The present disclosure provides various techniques for providing compatibility to multiple DDIC chip products for a display panel including a plastic substrate while mitigating an effect of heat expansion of the plastic substrate. In one or more embodiments, a display panel includes a plastic substrate and a first inner lead bonding (ILB) electrode on the plastic substrate. The first ILB electrode includes a first bonding segment, a second bonding segment, and a first connection segment. The bonding segment referred herein may be a portion of an ILB electrode, the portion being configured to be bonded a bump of a DDIC chip. The first bonding segment is configured to be bonded to a first DDIC chip, and the second bonding segment is configured to be bonded to a second DDIC chip configured differently from the first DDIC chip. The first bonding segment is extended in a first direction oblique to a vertical direction of the display panel. The first connection segment is configured to provide an electrical connection between the first bonding segment and the second bonding segment. The first connection segment may be extended in a second direction different from the first direction. The second bonding segment may be extended in the first direction as with the first bonding segment. The ILB electrode arrangement in which the first and/or second bonding segments extended in the direction oblique to the vertical direction of the display panel may facilitate aligning the bump of the first or second DDIC chip to the ILB electrode in mounting the first or second DDIC chip on the display panel.
The display panel 100 includes a display region 140 in which a desired image is displayed under the control of the DDIC chip 200.
Referring back to
Referring to
The DDIC chip 200A further include two alignment marks 210A and 212A used to place the DDIC chip 200A at the desired position of the driver mounting region 160 of the display panel 100 during the mounting process. In the illustrated embodiments, the array of the output bumps 204A is positioned between the alignment marks 210A and 212A. The array of the output bumps 204A is positioned closer to the alignment marks 210A and 212A than the array of input bumps 202A. Further, the array of the output bumps 206A is located near the alignment mark 210A, and the array of the output bumps 208A is located near the alignment mark 212A. Numeral 214A denotes the center line of the DDIC chip 200A defined to extend in the vertical direction to pass the center of the DDIC chip 200A.
Referring to
The driver mounting region 160 further includes output lead bonding electrodes 104, 106, and 108 configured to be bonded to the output bumps 204A, 206A, 208A of the DDIC chip 200A and the output bumps 204B, 206B, 208B of the DDIC chip 200B. The output lead bonding electrodes 104, 106, and 108 are also formed on the plastic substrate 120. In various implementation, at least part of the output lead bonding electrodes 104 are electrically connected to the data lines 132 with routing traces (not illustrated), and at least part of the output lead bonding electrodes 106 and 108 are electrically connected to the scan driver circuitry configured to drive the scan lines 134 with routing traces (not illustrated).
The driver mounting region 160 further includes two alignment marks 110 and 112 used to achieve alignment of the DDIC chip 200A or 200B to the driver mounting region 160 during the mounting process. When the DDIC chip 200A is mounted on the driver mounting region 160, the position of the DDIC chip 200A is adjusted such that the alignment marks 210A and 212A of the DDIC chip 200A are aligned with the alignment marks 110 and 112 of the driver mounting region 160. Correspondingly, when the DDIC chip 200B is mounted on the driver mounting region 160, the position of the DDIC chip 200B is adjusted such that the alignment marks 210B and 212B of the DDIC chip 200B are aligned with the alignment marks 110 and 112. In other embodiments, three or more alignment marks may be disposed in the driver mounting region 160. In such embodiments, the same number of the alignment marks may be disposed on the DDIC chips 200A and 200B.
Numeral 114 denotes a vertical reference line defined for the driver mounting region 160. When the alignment marks 210A and 212A of the DDIC chip 200A are aligned with the alignment marks 110 and 112 of the driver mounting region 160, the center line 214A of the DDIC chip 200A is also aligned with the vertical reference line 114. Correspondingly, when the alignment marks 210B and 212B of the DDIC chip 200B are aligned with the alignment marks 110 and 112 of the driver mounting region 160, the center line 214B of the DDIC chip 200B is also aligned with the vertical reference line 114.
In the embodiments illustrated in
One issue in mounting a DDIC chip 200A or 200B on the display panel 100 may be heat expansion of the plastic substrate 120 during the mounting process. In embodiments where anisotropic conductive films (ACF) are used to bond the DDIC chip 200A or 200B on the display panel 100, for example, the plastic substrate 120 of the display panel 100 is heated during the bonding. As the plastic substrate 120 often exhibits a large heat expansion, the difference in the heat expansion between the plastic substrate 120 and the DDIC chip 200A or 200B (which generally includes a silicon substrate) may make it difficult to align bumps on the DDIC chip 200A or 200B with desired electrodes on the plastic substrate.
In one or more embodiments, the layout of the input bumps 202A and 202B of the DDIC chip 200A and 200B and the layout of the ILB electrodes 102 of the display panel 100 are designed to mitigate the effect of the heat expansion difference.
Referring to
Referring to
In one or more embodiments, the acute angle formed between the vertical reference line 114 and the direction in which each first bonding segment 122 is extended is identical to the acute angle formed between the center line 214A and the direction in which the corresponding input bump 202A is extended. For the configurations illustrated in
The layouts illustrated in
The above-described discussion also applies to the input bumps 202B of the DDIC chip 200B and the second bonding segments 124 of the ILB electrodes 102 of the display panel 100. In one or more embodiments, the acute angles formed between the center line 214B of the DDIC chip 200B and the directions in which the input bumps 202B increase as the distance from the center line 214B increases. The acute angles formed between the vertical reference line 114 and the directions in which the second bonding segments 124 are extended increase as the distance from the vertical reference line 114 increases. The acute angle formed between the vertical reference line 114 and the direction in which each first bonding segment 122 is extended is identical to the acute angle formed between the center line 214B and the direction in which the corresponding input bump 202B is extended. The difference in the displacement between the second bonding segments 124 and the input bumps 202B of the DDIC chip 200B are absorbed by adjusting the position of the DDIC chip 200B in the vertical direction of the display panel 100.
The driver mounting region 360 is further configured such that a DDIC chip 200C illustrated in
Referring back to
With respect to an ILB electrode 302 other than the ILB electrode 302 positioned aligned with the vertical reference line 114, the first bonding segment 322 is extended in a first direction oblique to the vertical direction of the display panel 100, where the vertical direction is illustrated as the y-axis direction in
Method 1500 of
At step 1502, a first display panel and a second display panel of the same configuration are prepared. A respective one of the first display panel and the second display panel includes a plastic substrate (e.g., the plastic substrate 120 illustrated in
At step 1504, a first bump of a first DDIC chip (e.g., the DDIC chip 200A illustrated in
While many embodiments have been described, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope. Accordingly, the scope of the invention should be limited only by the attached claims.
Claims
1. A display panel, comprising:
- a plastic substrate; and
- a first inner lead bonding (ILB) electrode on the plastic substrate,
- wherein the first ILB electrode comprises: a first bonding segment extended in a first direction oblique to a vertical direction of the display panel, a second bonding segment, and a first connection segment configured to provide an electrical connection between the first bonding segment and the second bonding segment,
- wherein the first bonding segment is configured to be bonded to a first display driver integrated circuit (DDIC) chip, and
- wherein the second bonding segment is configured to be bonded to a second DDIC chip configured differently from the first DDIC chip.
2. The display panel of claim 1, wherein the first connection segment is extended in a second direction different from the first direction.
3. The display panel of claim 1, wherein the second bonding segment is extended in the first direction.
4. The display panel of claim 1, further comprising a second ILB electrode formed on the plastic substrate,
- wherein the second ILB electrode comprises: a third bonding segment extended in a third direction different from the first direction, a fourth bonding segment, and a second connection segment configured to provide an electrical connection between the third bonding segment and the fourth bonding segment,
- wherein the third bonding segment is configured to be bonded to the first DDIC chip, and
- wherein the fourth bonding segment is configured to be bonded to the second DDIC chip.
5. The display panel of claim 4, wherein the fourth bonding segment is extended in the third direction.
6. The display panel of claim 4, wherein the first ILB electrode is positioned further than the second ILB electrode from a vertical reference line defined to extend in the vertical direction of the display panel,
- wherein the vertical reference line is aligned with a first center line of the first DDIC chip when the first DDIC chip is bonded to the display panel, and
- wherein a first acute angle formed between the vertical reference line and the first direction in which the first bonding segment is extended is larger than a second acute angle formed between the vertical reference line and the third direction in which the third bonding segment is extended.
7. The display panel of claim 1, further comprising an alignment mark adapted to both the first DDIC chip and the second DDIC chip.
8. The display panel of claim 7, wherein the second bonding segment is positioned in the vertical direction of the display panel with respect to the first bonding segment and further than the first bonding segment from the alignment mark.
9. The display panel of claim 7, further comprising a bonding electrode on the plastic substrate, the bonding electrode being positioned closer to the alignment mark than the first ILB electrode and configured to be bonded to both the first DDIC chip and the second DDIC chip.
10. A method, comprising:
- preparing a first display panel and a second display panel of a same configuration, a respective one of the first display panel and the second display panel comprising: a plastic substrate; and a first ILB electrode on the plastic substrate, the first ILB electrode comprising: a first bonding segment extended in a first direction oblique to a vertical direction of the respective one of the first display panel and the second display panel; a second bonding segment; and a first connection segment configured to provide an electrical connection between the first bonding segment and the second bonding segment,
- bonding a first bump of a first DDIC chip to the first bonding segment of the first display panel; and
- bonding a second bump of a second DDIC chip to the second bonding segment of the second display panel, the second DDIC chip being configured differently from the first DDIC chip.
11. The method of claim 10, wherein the first connection segment is extended in a second direction different from the first direction.
12. The method of claim 10, wherein the second bonding segment is extended in the first direction.
13. The method of claim 10, wherein each of the first display panel and the second display panel further comprises an alignment mark,
- wherein, in each of the first display panel and the second display panel, the second bonding segment is positioned further than the first bonding segment from the alignment mark.
14. The method of claim 13, wherein the second DDIC chip comprises a frame memory configured to store image data for an entire frame image.
15. The method of claim 14, wherein the first DDIC chip does not comprise any memory capable of storing image data for an entire frame image.
16. The method of claim 13, wherein the first DDIC chip is designed with a first design rule,
- wherein the second DDIC chip is designed with a second design rule different from the first design rule.
17. The method of claim 16, the first design rule offers a higher integration density than the second design rule.
18. The method of claim 10, wherein, further comprising a second ILB electrode formed on the plastic substrate,
- wherein the second ILB electrode comprises: a third bonding segment extended in a third direction different from the first direction; a fourth bonding segment; and a second connection segment configured to provide an electrical connection between the third bonding segment and the fourth bonding segment,
- wherein the method further comprising: bonding a third bump of the first DDIC chip to the third bonding segment of the first display panel; and bonding a fourth bump of the second DDIC chip to the fourth bonding segment of the second display panel.
19. The method of claim 18, wherein the first ILB electrode is positioned further than the second ILB electrode from a vertical reference line defined to extend in the vertical direction of the respective one of the first display panel and the second display panel,
- wherein the vertical reference line is aligned with a first center line of the first DDIC chip when the first DDIC chip is bonded to the first display panel, and
- wherein a first acute angle formed between the vertical reference line and the first direction in which the first bonding segment is extended is larger than a second acute angle formed between the vertical reference line and the third direction in which the third bonding segment is extended.
20. A display module, comprising:
- a display panel; and
- a product DDIC chip bonded on the display panel,
- wherein the display panel comprises: a plastic substrate; and a first ILB electrode on the plastic substrate,
- wherein the first ILB electrode comprises: a first bonding segment extended in a first direction oblique to a vertical direction of the display panel; a second bonding segment; and a first connection segment configured to provide an electrical connection between the first bonding segment and the second bonding segment,
- wherein the first bonding segment is configured to be bonded to a first DDIC chip, and
- wherein the second bonding segment is configured to be bonded to a second DDIC chip configured differently from the first DDIC chip,
- wherein a bump of the product DDIC chip is bonded to a selected one of the first bonding segment and the second bonding segment.
Type: Application
Filed: Feb 19, 2021
Publication Date: Aug 25, 2022
Applicant: Synaptics Incorporated (San Jose, CA)
Inventors: Toshifumi Ogata (Tokyo), Atsushi Maruyama (Tokyo), Goro Sakamaki (Tokyo)
Application Number: 17/180,577