DIE-GROUP PACKAGE HAVING A DEEP TRENCH DEVICE
A method of forming a package device includes providing a carrier substrate, forming a trench in a front side of the carrier substrate, and bonding a semiconductor die in the trench. The method also includes thinning a back side of the carrier substrate based on a target thickness to obtain a thinned carrier substrate. The method further includes providing a first die group and bonding the thinned carrier substrate to the first die group to form a height-adjusted first die group.
The present application claims priority to U.S. Provisional Patent Application 63/189,110, filed on May 15, 2021, and entitled “SOIC CARRY WAFER EMBED VOLTAGE STABILIZER,” the entire disclosure of which is incorporated herein by reference.
TECHNICAL FIELDThe present disclosure relates to a multi-chip package having a voltage stabilization device.
BACKGROUNDSemiconductor dies can be electrically connected with other circuitry in a package substrate. The package substrate provides for electrical connection to other circuitry on a printed circuit board. Semiconductor dies can have different functions and are difficult to be processed using the same semiconductor processing techniques; so they are manufactured separately. A large multi-functional device having high performance can be obtained by assembling multiple dies into the device. The multiple dies can be stacked together to form die groups, and the die groups can be mounted to the package substrate.
The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrary increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Prepositions, such as “on” and “side” (as in “sidewall”) are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. The term “horizontal” is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above, i.e., perpendicular to the surface of a substrate. The terms “first,” “second,” “third,” and “fourth” may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
There are many packaging technologies to house the semiconductors such as the 2D fan-out (chip-first) IC integration, 2D flip chip IC integration, PoP (package-on-package), SiP (system-in-package) or heterogeneous integration, 2D fan-out (chip-last) IC integration, 2.1D flip chip IC integration, 2.1D flip chip IC integration with bridges, 2.1D fan-out IC integration with bridges, 2.3D fan-out (chip-first) IC integration, 2.3D flip chip IC integration, 2.3D fan-out (chip-last) IC integration, 2.5D (solder bump) IC integration, 2.5D (μbump) IC integration, μthump 3D IC integration, μbump chiplets 3D IC integration, bumpless 3D IC integration, bumpless chiplets 3D IC integration, SoIC and/or any other packaging technologies. It should be understood that various embodiments disclosed herein, although described and illustrated in a context of a specific semiconductor packaging technology, are not intended to limit the present disclosure only to that packaging technology. One skilled in the art would understand those embodiments may be applied in other semiconductor technologies in accordance with principles, concepts, motivations, and/or insights provided by the present disclosure.
System on integrated chip (SoIC) is a recent development in advanced packaging technologies. SoIC technology integrates both homogeneous and heterogeneous chiplets into a single System-on-Chip (SoC)-like chip with a smaller footprint and thinner profile, which can be holistically integrated into advanced WLSI (aka CoWoS® service and InFO). From external appearance, the newly integrated chip is just like a general SoC chip yet embedded with desired and heterogeneously integrated functionalities. SoIC realizes 3D chiplets integration with additional advantages in performance, power and form factor. Among many other features, the SoIC features ultra-high-density-vertical stacking for high performance, low power, and reduced RLC (resistance-inductance-capacitance). SoIC integrates active and passive chips into a new integrated-SoC system to achieve better form factor and performance. US Patent Publication #20200168527, entitled “SoIC chip architecture,” provides some descriptions of some example SoIC structures. US Patent Publication #20200168527 is incorporated by reference in its entirety. Another example of SoICTM can be found at https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC.htm, which is also incorporated by reference in the present disclosure in its entirety.
Various embodiments relate to multi-chip devices having stacked chips disposed on a base structure. As used herein, chips and dies are used interchangeably and refer to pieces of a semiconductor wafer, to which a semiconductor manufacturing process has been performed, formed by separating the semiconductor wafer into individual dies. A chip or die can include a processed semiconductor circuit having a same hardware layout or different hardware layouts, same functions or different functions. In general, a chip or dies has a substrate, a plurality of metal lines, a plurality of dielectric layers interposed between the metal lines, a plurality of vias electrically connecting the metal lines, and active and/or passive devices. The dies can be assembled together to be a multi-chip device or a die group. As used herein, a chip or die can also refer to an integrated circuit including a circuit configured to process and/or store data. Examples of a chip, die, or integrated circuit include a field programmable gate array (e.g., FPGA), a processing unit, e.g., a graphics processing unit (GPU) or a central processing unit (CPU), an application specific integrated circuit (ASIC), memory devices (e.g., memory controller, memory), and the like.
In accordance with the present disclosure, a die-group package having an embedded deep trench capacitor (DTC) is provided. In various embodiments, the die-group package includes a carrier substrate disposed on a first die group, a second die group, a base die group having the first die group and the second die group disposed thereon, and any other components (if any). In those embodiments, the first die group and the second die group have a height difference, and a carrier substrate is disposed on the first die group to more or less compensate that height difference. In those embodiments, the DTC is embedded in the carrier substrate and is connected to the first die group through one or more interconnects in the first group. In this way, a form factor of the die-group package is improved because the DTC and carrier substrate occupy a same space rather than two different spaces in the die-group package.
In accordance with the present disclosure, a method for fabricating a die-group package having an embedded DTC is provided. In various embodiments, the method includes etching a DTC space within a carrier substrate, growing a liner in the space, fusion bonding a DTC die in the DTC space, filling one or more gaps within the DTC space, planarizing the DTC space, hybrid bonding the carrier substrate onto a first die group of the die group structure, planarizing the carrier substrate to make a combined height of the first die group and the carrier substrate more or less the same as a second die group of the die-group structure.
Dies and Die Groups in Accordance with the Present Disclosure
In this section, an example individual die structure, an example stacked die structure in a die group, and an example wafer-on-wafer configuration having the example stacked die structure are provided to illustrate some embodiments where the present disclosure may be applied. It should be understood that the examples shown in this section are merely illustrative for understanding how the present disclosure may be applied in those examples. Thus, these examples should not be construed as being intended to limit the present disclosure. One skilled in the art will understand the present disclosure may be applied in other semiconductor packaging technologies wherever appropriate.
An Example Individual Die Structure in Accordance with the Present Disclosure
An Example Stacked Die Structure in Accordance with the Present Disclosure
As can be seen, in this example, the stacked dies in the stacked die structure 210 are bonded to each other through bonding members 214. In some implementations, the bonding members 214 include hybrid bonding films. However, this is not intended to be limiting. It is understood that the bonding members 214, in accordance with the present disclosure, are not limited to hybrid bonding films. For example, it is contemplated that the bonding members 214 may include micro bumps, solder balls, metal pads, and/or any other suitable bonding structures.
As also can be seen, each of the stacked dies 211, 212, and 213 includes a substrate 201, an active region 202 formed on a surface of the substrate 201, a plurality of dielectric layers 203, a plurality of metal lines and a plurality of vias 204 formed in the dielectric layers 203, and a passivation layer 207 on a top inter-metal layer 206. In an embodiment, a stacked die can also include passive devices, such as resistors, capacitors, inductors, and the like. The substrate 201 can be a semiconductor substrate or a non-semiconductor substrate. For example, the substrate 201 may include a bulk silicon substrate. In some embodiments, the substrate 201 may include an elementary semiconductor, such as silicon or germanium in a crystalline structure, a compound semiconductor, e.g., silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, or combinations thereof. Possible substrate 201 may also include a semiconductor-on-insulator (SOI) substrate. In an embodiment, the substrate 201 is a silicon layer of an SOI substrate. The substrate 201 can include various doped regions depending on design requirements, e.g., n-type wells or p-type wells. The doped regions are doped with p-type dopants, e.g., boron, n-type dopants, e.g., phosphorous or arsenic, or combinations thereof. The active region 102 may include transistors. The dielectric layers 203 may include interlayer dielectric (ILD) and intermetal dielectric (TMD) layers. The ILD and IMD layers may be low-k dielectric layers which have dielectric constants (k values) smaller than a predetermined value, e.g., about 3.9, smaller than about 3.0, smaller than 2.5 in some embodiments. In some other embodiments, the dielectric layers 203 may include non-low-k dielectric materials having dielectric constants equal to or greater than 3.9. The metal lines and vias may include copper, aluminum, nickel, tungsten, or alloys thereof.
In this example, the die group 20 includes through silicon vias (TSVs) or through oxide vias (TOVs) 208 configured to electrically connect the metal lines in the stacked dies 211, 212, and 213 with each other. In an implementation, an individual TSV/TOV 208 may include copper, aluminum, tungsten, alloys thereof, and/or any other suitable materials. TSV/TOVs 208 are arranged in this example to facilitate electronic communication between and among stacked dies 211, 212 and 213. However, it is understood that in some other semiconductor packaging technologies where the present disclosure applies, TSV/TOVs may not be present and thus the TSV/TOVs 208 shown in this example shall not be construed as being intended to limit the present disclosure.
In this example, each of the stacked dies 211, 212, and 213 also includes a side metal interconnect structure 209 on a sidewall of the stack dies. The side metal interconnect structure 209 may include one or more metal wirings extending through an exposed surface of the plurality of dielectric layers 203. The side metal interconnect structure 209 may be formed at the same time as the metal layers and exposed to the side surface of the die group 20 after the different dies 211, 212, and 213 have been bonded together and the side surface is polished by a chemical mechanical polishing (CMP) process.
In some embodiments, the die group 20 can be formed by bonding a plurality of wafers together using fusion bonding, eutectic bonding, metal-to-metal bonding, hybrid bonding processes, and the like. A fusion bonding includes bonding an oxide layer of a wafer to an oxide layer of another wafer. In an embodiment, the oxide layer can include silicon oxide. In an eutectic bonding process, two eutectic materials are placed together, and are applied with a specific pressure and temperature to melt the eutectic materials. In the metal-to-metal bonding process, two metal pads are placed together, and a pressure and high temperature are provided to the metal pads to bond them together. In the hybrid bonding process, the metal pads of the two wafers are bonded together under high pressure and temperature, and the oxide surfaces of the two wafers are bonded at the same time.
In some embodiments, each wafer may include a plurality of dies, such as semiconductor devices of
In some embodiments, the dies are electrically coupled to each other by through substrate vias (TSVs) and through oxide vias (TOVs) 308. In some embodiments, the die group 30 also includes a bonding layer 317 including an oxide material, e.g., silicon oxide. In some embodiments, the bonding layer 317 may include a plurality of bonding films and electrical connectors 309 having a plurality of solder regions. In some embodiments, the electrical connectors 309 include copper posts, solder caps, and/or electrically conductive bumps 310 configured to electrically coupled to other electronic circuits on a printed circuit board or other substrates. In some embodiments, the die group 30 includes a plurality of semiconductor dies or chips similar to those of
In some embodiments, the dies are bonded to each other by a hybrid bonding process. In an embodiment, the first die 301a has a first bonding surface formed on its upper surface including a first bonding dielectric layer 315a and a first conductive contact structure 316a. The second die 301b has a second bonding surface formed on a bottom of its substrate, the second bonding surface includes a second bonding dielectric layer 315b and a conductive contact structure 316b. In an embodiment, the first and second conductive contact structures 316a, 316b may be electrically coupled to the interconnect structure 303. In another embodiment, the first and second conductive contact structures 316a, 316b may not be electrically coupled to the interconnect structure 303. In an embodiment, the first die 301a and the second die 301b are directly hybrid bonded together, such that the first and second conductive contact structures 316a, 316b are bonded together, and the first and second bonding dielectric layers 315a, 315b are bonded together. In an embodiment, the first and second bonding dielectric layers 315a, 315b each include silicon oxide, and the first and second conductive contact structures 316a, 316b each include copper.
In an embodiment, the dies also include a seal ring 320 configured to stop cracks generated by stress during the bonding processes and/or the singulation. The seal ring 320 is also configured to prevent water, moisture, and other pollutant from entering the dies. In an embodiment, the seal ring 320 includes copper configured to suppress electromagnetic noise. In an embodiment, the first die 301a may include a bonding dielectric layer 330 configured to be bonded to a carrier substrate by fusion bonding.
Uneven Stacking of Die GroupsIn various embodiments, due to a design choice, a functional requirement, and/or any other consideration, two die groups stacked on a base die group in a die group structure have different heights. The difference of their heights, in some embodiments, may exceed a threshold and cause potential warpage or crack in the base die group.
In some embodiments, the die group 40 also includes a plurality of conductive features 402 extending through the dies 401a to 401e and electrically coupled to a plurality of conductive bonding structures 403 disposed between the dies 401a, 401b, 401c, 401d, and 401e to electrically bond them together. The conductive features 402 are configured as through-substrate vias (TSVs) to electrically connect the dies with each other. In an embodiment, the conductive bonding structures 403 include tiny solder bumps, such as controlled collapse chip connection (C4) bumps or ball grid array (BGA) bumps and pillars formed on an upper surface of a die using various process steps. In some embodiments, the die group 40 also includes a bonding structure 405 formed on a surface of the BEOL structure of the die 401a and configured to bond the die group 40 to a substrate 410. The die group 40 is flipped over and mounted on the substrate 410. In some embodiments, the die group 40 also includes a molding compound layer 411 that encapsulates the dies 401a, 401b, 401c, 401d, and 401e. The molding compound layer 411 includes an epoxy-based resin or other suitable material. In some embodiments, the molding compound layer 411 fills the air gaps between the dies 401a, 401b, 401c, 401d, and 401e and surrounds the conductive bonding structures 403 and 405.
In some embodiments, the first die group 501 includes a plurality of dies stacked with other through hybrid bonding. In those embodiments, the second die group 502 includes a plurality of dies stacked onto each other through metal-to-metal bonding. In one implementation, the first die group 501 is the die group 30 shown and described with reference to
In an embodiment, the first die group 501 also includes a second die 501b having a substrate 511s, a FEOL structure 511f formed on the substrate 511s, a BEOL structure 511b formed on the FEOL structure 511f, a dielectric layer 512d formed on a surface of the BEOL structure 512b, and a bonding structure 512b in the dielectric layer 512d. In an embodiment, second die 501b is bonded to the first die 501a by hybrid bonding, i.e., a metal surface of the bonding structure 512b of the second die 501b is bonded to a metal surface of a bonding structure 511b in a dielectric layer 511d disposed on a lower surface of the first die 501a, and the surfaces of the dielectric layers 512d and 511d are bonded together.
In some embodiments, the first die group 501 and the second die group 502 are bump bonded to the substrate 500. The substrate 500, the first die group 501, and the second die group 502 may have different coefficients of thermal expansion (CTEs). The different CTEs will induce thermal stress when the temperature in the package device 50 changes.
Referring back to
As also can be seen in
In some embodiments, for disposing the dummy wafer 540, a height difference between the first die group 501 and the second die group 502 is determined, and the dummy wafer 540 is provided on first die group 501 according to the determined height difference. This may include thinning the dummy wafer 540 based on the height difference to obtain a thinned dummy wafer 540, and mounting the thinned dummy wafer 540 to the first die group 501 to form a height-adjusted first die group 501 having a combined height (501T+540T) within a height range of the second die group. In an embodiment, the combined height (501T+540T) is within 10% (plus or minus) of the height 502T of the second die group.
Embedded DTC in a Carrier Substrate in a Die-Group PackageIn some embodiments, for saving space in a die-group package, a deep-trench capacitor (DTC) device, such as a capacitor device used in a voltage stabilizer, is embedded in a carrier substrate disposed on a die group of the die-group package.
In some embodiments, the carrier substrate 604 is a blank carrier substrate without any electronic components formed thereon. The carrier substrate may include glass, ceramic, silicon, silicon oxide, and the like; the air gap is completely encapsulated in the dielectric material to prevent residual moisture and pollutants from entering or remaining in the air gap during and after the forming process. The dielectric material can include a low-k dielectric material.
In an embodiment, the lower surface of the carrier substrate is planarized to adjust the thickness 604T prior to being bonded to the upper surface of the first die group. In an embodiment, the bonding of the carrier substrate to the first die group includes fusion bonding. In an exemplary embodiment, the fusion bonding includes pressing the carrier substrate and the first die group against each other and performing an annealing process to cause the carrier substrate and the first die group to be bonded together due to atomic attraction forces. In an embodiment, the annealing process is performed at a temperature in a range from 500° C. to 1200° C.
As can be seen, in this example, the DTC device 605 is embedded in a carrier substrate 604. As also can be seen, a height 604T of dummy wafer 604 is combined with a height of first die group 501 to be more or less the same as a height 502T of the second die group 502. That is, the combined height 604T+501T is more or less than the height of 502T. In some embodiments, the combined height 604T+501T is within 10% of the height 502T, plus or minus. It is also illustrated in
The deep trench capacitor (DTC) device 62 is often fabricated as a stand-alone die and packaged with a circuit that requires capacitors, such as illustrated in
In some embodiments, the device embedded in the carrier wafer is not limited to DTC. Another semiconductor die can be bonded in the trench of the carrier substrate. For example, the semiconductor die can be silicon logic die, processor die, or memory die. The semiconductor die can also be an optical light source or sensor, or a mechanical sensor in a micro-electro-mechanical system (MEMS) die, or the like. In some embodiments, the semiconductor die is bonded in the trench in the carrier substrate using silicon fusion bonding between a substrate of the semiconductor die and the carrier substrate without using of intermediate adhesives.
Referring to
At 702, a patterned etch process is carried out to form a trench 810 in the carrier substrate 840, as shown in
At step 703, a DTC die 820 is bonded to the carrier substrate 840 in the trench 810, as shown in
At step 704, a gap fill and planarization process is carried out to form a gap fill material in the gaps between the DTC die and the carrier substrate 840.
At step 705, the thickness of carrier substrate 840 is reduced by a polishing or etching process at the backside or second surface 802 of the carrier substrate. As described below with reference to the flowchart in
At step 706, the thinned carrier substrate 840 including the embedded DTC 820 is bonded to a die group 850.
The first die group 850 may be similar to the die group 30 of
Referring to
The first die group 910 may be similar to the die group 30 of
In an embodiment, the second die group 920 includes a first die 920a, a second die 920b, a third die 920c, and a fourth die 920d bonded to each other through conductive bonding structures 913. In an embodiment, the first, second, third, and fourth dies are electrically and mechanically connected to a plurality of conductive bonding structures 913. The second die group 920 also includes a molding compound layer 915 that encapsulates the dies 920a through 920d and fills air gaps between the dies.
The first die group 910 and the second die group 920 may have different heights (thickness) and CTEs. When the first die group and the second die group are encapsulated in a molding compound, the height difference between the first and second die groups may induce uneven top stress to the die group that has a smaller height. The inventor has discovered that molding stress can cause warpage and delamination of the first die group when the height difference is greater than a certain percentage height range of the second die group. The inventor provided herein a solution by mounting a carrier substrate 930 on an upper surface of the first die group 910 to compensate for the height difference, thereby reducing the uneven top stress of the first die group.
Referring to
In an embodiment, the carrier substrate 930 has a height or thickness that is characterized by a height or thickness difference between the first and second die groups. In an embodiment, the first die group has a first thickness, the second die group has a second thickness, and the sum of the thickness of the carrier substrate and the first thickness of the first die group is equal to or greater than the second thickness of the second die group. The carrier substrate 930 and the first die group 910 are hybrid bonded together. In some embodiments, the carrier substrate 930 may include a glass substrate, quartz, resin, or silicon substrate. In some embodiments, the carrier substrate 930 may be attached to a top surface of the first passivation layer using an adhesion layer. The carrier substrate can relieve mechanical and thermal stress applied to the first die group. The carrier substrate can support the die package from being warped. A fabrication process of the carrier substrate including the encapsulated air gap and the thickness adjustment has been described with reference to
Referring still to
Referring back to
In some embodiments, a package device comprising a base substrate. A first die group includes a first set of one or more dies. The first die group is bonded to the base substrate, and the first die group includes a voltage stabilizer circuit. A second die group, including a second set of one or more dies, is bonded to the base substrate. The height of the second die group is greater than the height of the first die group. A carrier substrate is bonded to the first die group and includes a trench and a deep trench capacitor (DTC) die bonded within the trench. The DTC die is coupled to the voltage stabilizer circuit in the first die group. A combined height of the first die group and the carrier substrate is within 30% of the height of the second die group.
In some embodiments, a semiconductor device includes a package substrate. A first die group and a second die group are bonded onto the package substrate. The first die group is characterized by a first thickness, and the second die group is characterized by a second thickness. The semiconductor device also includes a carrier substrate bonded on the first die group. The carrier substrate includes a trench with a semiconductor die bonded therein. The carrier substrate is characterized by a third thickness that is determined based a difference between the first thickness and the second thickness.
In some embodiments, a method of forming a package device includes providing a carrier substrate, forming a trench in a front side of the carrier substrate, and bonding a semiconductor die in the trench. The method also includes thinning a back side of the carrier substrate based on a target thickness to obtain a thinned carrier substrate. The method further includes providing a first die group and bonding the thinned carrier substrate to the first die group to form a height-adjusted first die group.
The foregoing merely outlines features of embodiments of the disclosure. Various modifications and alternatives to the described embodiments will be apparent to those skilled in the art in view of the teachings herein. Those skilled in the art will appreciate that equivalent constructions do not depart from the scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A package device comprising:
- a base substrate;
- a first die group comprising a first set of one or more dies, the first die group being bonded to the base substrate, the first die group including a voltage stabilizer circuit;
- a second die group comprising a second set of one or more dies, the second die group bonded to the base substrate, wherein the height of the second die group is greater than the height of the first die group; and
- a carrier substrate bonded to the first die group, the carrier substrate comprising a trench and a deep trench capacitor (DTC) die bonded within the trench, the DTC die being coupled to the voltage stabilizer circuit in the first die group;
- wherein a combined height of the first die group and the carrier substrate is within 30% of the height of the second die group.
2. The package device of claim 1, wherein the DTC die comprises:
- a deep trench capacitor structure disposed at a bottom surface of the trench in the carrier substrate; and
- an interconnect structure over the deep trench capacitor structure and coupled to the deep trench capacitor structure.
3. The package device of claim 2, wherein the interconnect structure in the DTC die is coupled to the voltage stabilizer circuit through a trans-silicon-via (TSV) in a substrate in the first die group.
4. The package device of claim 2, wherein the voltage stabilizer circuit comprises a switched capacitor regulator.
5. The package device of claim 1, wherein the first die group is characterized by a first thickness, the second die group is characterized by a second thickness, the carrier substrate is characterized by a third thickness, wherein a sum of the first thickness and the third thickness is equal to or greater than the second thickness.
6. The package device of claim 1, wherein the first die group comprises a first die and a second die that are bonded to each other by hybrid bonding.
7. The package device of claim 1, wherein the carrier substrate is bonded to the first die group by hybrid bonding.
8. A semiconductor device comprising:
- a package substrate;
- a first die group bonded onto the package substrate, the first die group characterized by a first thickness;
- a second die group bonded onto the package substrate, the second die group characterized by a second thickness; and
- a carrier substrate bonded on the first die group, the carrier substrate including a trench with a semiconductor die bonded therein, wherein the carrier substrate is characterized by a third thickness that is determined based a difference between the first thickness and the second thickness.
9. The semiconductor device of claim 8, wherein the semiconductor die comprises a deep trench capacitor (DTC) die.
10. The semiconductor device of claim 9, wherein the DTC die comprises:
- a deep trench capacitor structure disposed at a bottom surface of the trench in the carrier substrate; and
- an interconnect structure over the deep trench capacitor structure and coupled to the deep trench capacitor structure.
11. The semiconductor device of claim 10, wherein the first die group comprises a voltage stabilizer circuit.
12. The semiconductor device of claim 11, wherein the interconnect structure in the DTC die is coupled to the voltage stabilizer circuit through a trans-silicon-via (TSV) in a substrate in the first die group.
13. The semiconductor device of claim 8, wherein the semiconductor die is bonded in the trench in the carrier substrate using silicon fusion bonding between a substrate of the semiconductor die and the carrier substrate.
14. A method of forming a package device comprising:
- providing a carrier substrate;
- forming a trench in a front side of the carrier substrate;
- bonding a semiconductor die in the trench;
- thinning a back side of the carrier substrate based on a target thickness to obtain a thinned carrier substrate;
- providing a first die group; and
- bonding the thinned carrier substrate to the first die group to form a height-adjusted first die group.
15. The method of claim 14, wherein bonding a semiconductor die in the trench comprises:
- forming a capacitor structure in a semiconductor substrate;
- forming a conductive interconnect structure on the capacitor structure;
- thinning the semiconductor substrate from a back side; and
- bonding the semiconductor substrate in the trench of the carrier substrate.
16. The method of claim 15, wherein the capacitor structure comprises a deep trench capacitor (DTC) device; and the capacitor structure is coupled to a voltage stabilizer circuit in the first die group.
17. The method of claim 14, further comprising:
- providing a second die group;
- determining a height difference between the first die group and the second die group; and
- setting the target thickness of the carrier substrate based on the determined height difference between the first die group and the second die group.
18. The method of claim 17, further comprising:
- mounting the height-adjusted first die group and the second die group to a package substrate; and
- forming a molding material on the package substrate covering the height-adjusted first die group and the second die group, wherein the molding material comprises a cavity between the height-adjusted first die group and the second die group.
19. The method of claim 17, wherein:
- the first die group is characterized by a first height;
- the second die group is characterized by a second height;
- the thinned carrier substrate is characterized by a third height; and
- a sum of the first height and the third height is equal to or greater than the second height.
20. The method of claim 16, wherein mounting the thinned carrier substrate to the first die group comprises hybrid bonding.
Type: Application
Filed: Mar 21, 2022
Publication Date: Nov 17, 2022
Inventor: JEN-YUAN CHANG (Hsinchu)
Application Number: 17/700,447