SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING SAME
Embodiments relate to the field of semiconductors, and provide a semiconductor structure and a method for fabricating the same. The semiconductor structure includes a first wafer and a second wafer. A surface of the first wafer has a first electrode plate, a first dielectric layer and a first dummy pad stacked in sequence to constitute a capacitor; and the surface of the first wafer further has a first functional pad, and the first functional pad and the first dummy pad are arranged on a same layer. The second wafer is bonded to the first wafer, and a surface of the second wafer has a second dummy pad and a second functional pad arranged on a same layer. The first dummy pad is bonded to the second dummy pad, and the first functional pad is bonded to the second functional pad.
This application is a continuation of PCT/CN2022/107694, filed on Jul. 25, 2022, which claims priority to Chinese Patent Application No. 202210804053.3 titled “SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING SAME” and filed on Jul. 7, 2022, the entire contents of which are incorporated herein by reference.
TECHNICAL FIELDEmbodiments of the present disclosure relate to the field of semiconductors, and more particularly, to a semiconductor structure and a method for fabricating the same.
BACKGROUNDHybrid Bonding is a technology that allows pads of two wafers to directly contact to produce molecular bonding. The Hybrid Bonding can provide higher interconnection density, smaller and simpler circuits, larger bandwidth, and lower power consumption, so it is widely used in the field of chip packaging.
However, space utilization of wafers using the Hybrid Bonding is not high.
SUMMARYEmbodiments of the present disclosure provide a semiconductor structure and a method for fabricating the same, which are at least beneficial to improving space utilization of a wafer.
According to some embodiments of the present disclosure, one aspect of the embodiments of the present disclosure provides a semiconductor structure. The semiconductor structure includes a first wafer and a second wafer. A surface of the first wafer has a first electrode plate, a first dielectric layer and a first dummy pad stacked in sequence to constitute a capacitor; and the surface of the first wafer further has a first functional pad, and the first functional pad and the first dummy pad are arranged on a same layer. The second wafer is bonded to the first wafer, and a surface of the second wafer has a second dummy pad and a second functional pad arranged on a same layer. The first dummy pad is bonded to the second dummy pad, and the first functional pad is bonded to the second functional pad.
According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a method for fabricating the semiconductor structure. The method includes: providing a first wafer; forming, on a surface of the first wafer, a first electrode plate, a first dielectric layer and a first dummy pad stacked in sequence to constitute a capacitor; and forming a first functional pad on the surface of the first wafer, where the first functional pad and the first dummy pad are arranged on a same layer; providing a second wafer; forming, on a surface of the second wafer, a second dummy pad and a second functional pad arranged on a same layer; and bonding the first dummy pad to the second dummy pad, and bonding the first functional pad to the second functional pad, such that the first wafer is bonded to the second wafer.
The accompanying drawings herein are incorporated in and constitute a part of this specification, illustrate embodiments conforming to the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. Apparently, the accompanying drawings in the following description show merely some embodiments of the present disclosure, and persons of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative efforts.
Referring to
Embodiments of the present disclosure provide a semiconductor structure, which includes a first wafer and a second wafer bonded to each other. A surface of the first wafer has a first electrode plate and a first dielectric layer, where the first electrode plate and the first dielectric layer constitute a capacitor together with a first dummy pad of the first wafer. The capacitor may replace component capacitors in the first wafer and the second wafer, thereby improving space utilization of the wafer.
The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. However, a person of ordinary skill in the art may understand that in the embodiments of the present disclosure, many technical details are put forward such that a reader may better understand the present disclosure. However, the technical solutions requested to be protected by the embodiments of the present disclosure may also be implemented even without these technical details or various variations and modifications based on the following embodiments.
As shown in
The semiconductor structure will be described in detail below with reference to the accompanying drawings.
First of all, it is to be noted that the semiconductor structure may be a chip, such as a memory chip. For example, the memory chip may be a dynamic random access memory (DRAM).
Referring to
The first dummy pad 11, the first functional pad 12, the second dummy pad 21 and the second functional pad 22 may have same material such as metal, which may be, for example, copper, gold, or aluminum, etc. A material of the first dielectric layer 16 may be Si3N4, SiO2, SiCN, HfO, or ZrO, etc. A material of the first electrode plate 17 may be the same as that of the pad. For example, both the material of the first electrode plate 17 and the material of the pad are copper.
The first electrode plate 17 is positioned on the surface of the first wafer 1, which mainly includes following two cases. The surface of the first wafer 1 is a plane, and the first electrode plate 17 is directly formed on the surface of the first wafer 1; or the surface of the first wafer 1 is further provided with a groove 5 (referring to
It is to be noted that the capacitor C constituted of the first dummy pad 11, the first dielectric layer 16 and the first electrode plate 17 may expand capacitances of the element capacitors or replace the element capacitors, such that it is advantageous to improving performance of the semiconductor structure, and improving the space utilization of the surface of the wafer. In some other embodiments, the capacitor C may also be used as a passive device in a circuit other than the first wafer 1 and the second wafer 2. Because the capacitor C is packaged with the first wafer 1 and the second wafer 2, this is advantageous to improving integration of package.
An area of the pad and an area of the first electrode plate 17 will be described below. It is worth noting that the area refers to an area of an orthographic projection of the pad and the first electrode plate 17 on an upper surface of the first wafer 1.
In some embodiments, referring to
In some embodiments, referring to
In some embodiments, referring to
For example, the area of the first dummy pad 11 ranges from 0.01 um2 to 100 um2, such as 1 um2, 50 um2 or 80 um2. The area of the second dummy pad 21 ranges from 0.01 um2 to 100 um2, such as 3 um2, 20 um2 or 60 um2. The area of the first functional pad 12 ranges from 0.01 um2 to 100 um2, such as 7 um2, 40 um2 or 90 um2. The area of the second functional pad 22 ranges from 0.01 um2 to 100 um2, such as 8 um2, 35 um2 or 78 um2. When the area of the first dummy pad 11, the area of the second dummy pad 21, the area of the first functional pad 12 and the area of the second functional pad 22 are within the above range, it is beneficial to improve a bonding strength, which can provide more sufficient space to the first surface dielectric layer 3 and a second surface dielectric layer 4, to ensure a better effect of isolation between the pads.
Referring to
Referring to
In some other embodiments, the capacitor C may not be connected to the second wiring layer 25. That is, the second dummy pad 21 or the first dummy pad 11 may also be electrically connected to an external component other than the first wafer 1 and the second wafer 2 through a connecting structure such as a wire, to connect the capacitor C to an circuit in the external component. Similarly, the capacitor C also may not be connected to the first wiring layer 15. That is, the capacitor C may be connected to one of the first wiring layer 15 and the second wiring layer 25.
Referring to
The capacitor C will be described in detail below.
Referring to
Referring to
Referring to
Hereinafter, a connection relationship between the plurality of capacitors C will be described in detail below by taking an example where the capacitors C are the first capacitors C1.
In some embodiments, the plurality of capacitors C may be independent of each other.
That is, referring to
In some other embodiments, the plurality of capacitors C may also be connected in parallel with each other. That is, the semiconductor structure includes at least one capacitor bank C0, and the same capacitor bank C0 includes a plurality of capacitors C connected in parallel. Referring to
First of all, it is to be noted that
In Example I, referring to
In some embodiments, referring to
In some other embodiments, referring to
In some other embodiments, referring to
With continued reference to
In Example 2, referring to
It is to be noted that the semiconductor structure further includes a fourth conductive part (not shown in the figure), where the fourth conductive part may be connected to the plurality of second conductive parts 251, such that the first dummy pads 11 of the plurality of capacitors C are conducted to each other. In this way, a parallel connection of the plurality of capacitors C may be achieved.
It is worth noting that, in some embodiments, the capacitor C is only constituted of the first dielectric layer 16, the first electrode plate 17, and the first dummy pad 11. In some other embodiments, referring to
In some embodiments, referring to
With continued reference to
In some other embodiments, the second electrode plate 27 may be connected to the second wiring layer 25 through the third conductive plug 23, and the first dummy pad 11 may be electrically connected to the first wiring layer 15 through the first conductive plug 13. In some embodiments, the electrode plate constituted of the second dummy pads 21 and the first dummy pads 11 may not be electrically connected to the first wiring layer 15 or the second wiring layer 25, but may be connected to the circuit of the external component through a connection structure such as a wire.
To sum up, in the semiconductor structure provided by the embodiments of the present disclosure, the first electrode plate 17 and the first dielectric layer 16 are additionally provided. The first electrode plate 17 and the first dielectric layer 16 constitute, together with the first dummy pad 11, the capacitor C, which may replace element capacitors in a chip, thereby reducing an overall size of the chip while maintaining performance of the chip. The increased capacitor C may be freely used by the first wafer 1 and the second wafer 2. In addition, the plurality of capacitors C may be connected in parallel to expand the capacitance of the capacitor. In addition, the plurality of capacitors C may be connected in parallel to form an annular structure, and may also form multiple independent arrays respectively.
As shown in
The method for fabricating the semiconductor structure provided by yet another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.
Referring to
In some embodiments, a metal layer is deposited on the entire surface to serve as an initial first wiring layer, and the initial first wiring layer is patterned to form a plurality of mutually insulated first conductive parts 151 to constitute the first wiring layer 15. The first wafer 1 is etched to form vias exposing the first wiring layer 15, and metal is deposited in the vias to form the first conductive plug 13 and the second conductive plug 14.
Referring to
Referring to
With continued reference to
Referring to
With continued reference to
So far, based on
Referring to
With continued reference to
To sum up, in the embodiments of the present disclosure, before forming the first dummy pad 11, the first electrode plate 17 and the first dielectric layer 16 are formed in the first wafer 1, thereby the capacitor C is formed. The capacitor C may replace the element capacitor in the first wafer 1 or the second wafer 2, or may be configured to increase the capacitance of the element capacitor. In this way, the space utilization of the surface of wafer can be improved.
In the description of this specification, reference to the description of the terms “some embodiments”, “for example”, etc. means that a particular feature, structure, material or characteristic described in connection with this embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms throughout this specification are not necessarily referring to the same embodiment or example. Furthermore, the features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, without contradiction, those skilled in the art may combine different embodiments or examples described in the specification and features of different embodiments or examples.
Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above-mentioned embodiments are exemplary and should not be construed as limiting the present disclosure. Those of ordinary skill in the art may make changes, modifications, replacements and variations to the above embodiments without departing from the scope of the present disclosure. Therefore, all changes or embellishments made according to the claims and the specification of the present disclosure shall still fall within the scope covered by the patent of the present disclosure.
Claims
1. A semiconductor structure, comprising:
- a first wafer, a surface of the first wafer having a first electrode plate, a first dielectric layer and a first dummy pad stacked in sequence to constitute a capacitor; and the surface of the first wafer further having a first functional pad, and the first functional pad and the first dummy pad being arranged on a same layer; and
- a second wafer bonded to the first wafer, a surface of the second wafer having a second dummy pad and a second functional pad arranged on a same layer; the first dummy pad being bonded to the second dummy pad, and the first functional pad being bonded to the second functional pad.
2. The semiconductor structure according to claim 1, wherein the first wafer is internally provided with a first wiring layer, a first conductive plug and a second conductive plug, the first conductive plug being positioned between the first electrode plate and the first wiring layer and being connected to the first electrode plate and the first wiring layer, and the second conductive plug being positioned between the first wiring layer and the first functional pad and being connected to the first wiring layer and the first functional pad; and
- wherein the second wafer is internally provided with a second wiring layer, a third conductive plug and a fourth conductive plug, the third conductive plug being positioned between the second wiring layer and the second dummy pad and being connected to the second wiring layer and the second dummy pad, and the fourth conductive plug being positioned between the second wiring layer and the second functional pad and being connected to the second wiring layer and the second functional pad.
3. The semiconductor structure according to claim 2, wherein the semiconductor structure comprises at least one capacitor bank, the same capacitor bank comprising a plurality of capacitors in parallel.
4. The semiconductor structure according to claim 3, wherein there are a plurality of first electrode plates and a plurality of first dummy pads, and the plurality of first electrode plates are arranged in one-to-one correspondence to the plurality of first dummy pads.
5. The semiconductor structure according to claim 3, wherein there is one first electrode plate and a plurality of first dummy pads, and the plurality of first dummy pads are arranged opposite to the one first electrode plate.
6. The semiconductor structure according to claim 3, wherein the plurality of first dummy pads of the plurality of capacitors in the same capacitor bank surround one or more of the first functional pads; and the plurality of second dummy pads of the plurality of capacitors in the same capacitor bank surround one or more of the second functional pads.
7. The semiconductor structure according to claim 3, wherein there are a plurality of capacitor banks, and the plurality of capacitors in the same capacitor bank are arranged in a same direction.
8. The semiconductor structure according to claim 7, wherein the plurality of capacitor banks are arranged in parallel, and the first functional pad and the second functional pad are both positioned between adjacent two of the plurality of capacitor banks.
9. The semiconductor structure according to claim 1, wherein an area of the first electrode plate is greater than or equal to an area of the first dummy pad.
10. The semiconductor structure according to claim 1, wherein an area of the first dummy pad is greater than or equal to an area of the second dummy pad.
11. The semiconductor structure according to claim 1, wherein an area of the first dummy pad is equal to an area of the first functional pad, and an area of the second dummy pad is equal to an area of the second functional pad.
12. The semiconductor structure according to claim 11, wherein the area of the first dummy pad is 0.01 um2 to 100 um2, the area of the second dummy pad being 0.01 um2 to 100 um2, the area of the first functional pad being 0.01 um2 to 100 um2, and the area of the second functional pad being 0.01 um2 to 100 um2.
13. The semiconductor structure according to claim 1, wherein the surface of the second wafer further has a second electrode plate, a second dielectric layer and a second connection layer; the second electrode plate, the second dielectric layer and the second dummy pad are sequentially stacked on the surface of the second wafer; and the second connection layer is connected to the second electrode plate and is spaced apart from the second dummy pad;
- the surface of the first wafer further has a first connection layer, the first connection layer being further connected to the first electrode plate and being spaced apart from the first dummy pad; and
- the first connection layer is connected to the second connection layer, both the first connection layer and the second connection layer extending in a direction perpendicular to an upper surface of the first wafer.
14. A method for fabricating a semiconductor structure, comprising:
- providing a first wafer;
- forming, on a surface of the first wafer, a first electrode plate, a first dielectric layer and a first dummy pad stacked in sequence to constitute a capacitor; and forming a first functional pad on the surface of the first wafer, the first functional pad and the first dummy pad being arranged on a same layer;
- providing a second wafer;
- forming, on a surface of the second wafer, a second dummy pad and a second functional pad arranged on a same layer; and
- bonding the first dummy pad to the second dummy pad, and bonding the first functional pad to the second functional pad, such that the first wafer is bonded to the second wafer.
15. The method for fabricating the semiconductor structure according to claim 14, wherein before forming the first electrode plate, the method further comprises:
- forming a first wiring layer in the first wafer;
- forming, in the first wafer, a first conductive plug and a second conductive plug connected to the first wiring layer;
- forming the capacitor comprises:
- removing the first wafer by a part of thickness to form a groove in the first wafer, the groove being positioned directly above the first conductive plug;
- forming a first electrode plate in the groove, the first electrode plate being connected to the first conductive plug;
- forming a first dielectric layer in the groove, the first dielectric layer further covering the first electrode plate;
- forming a first surface dielectric layer on the surface of the first wafer; and
- forming a first dummy pad and a first functional pad in the first surface dielectric layer, the first dummy pad being positioned directly above the first electrode plate, and the first functional pad being connected to the second conductive plug.
Type: Application
Filed: Sep 6, 2022
Publication Date: Dec 29, 2022
Inventor: LING-YI CHUANG (Hefei)
Application Number: 17/903,060