MULTI-STACKING CARRIER STRUCTURE AND METHOD FOR FABRICATING THE SAME
A multi-stacking carrier structure includes an etch stop layer; a first tier comprising a first passivation layer positioned on the etch stop layer, a first insulating layer positioned on the first passivation layer, and a first via positioned along the first passivation layer and the first insulating layer; a second tier positioned on the first tier and comprising a second passivation layer positioned on the first insulating layer, a second insulating layer positioned on the second passivation layer, and a second via positioned along the second passivation layer and the second insulating layer, and electrically connected to the first via; and a third tier positioned on the second tier and comprising a third passivation layer positioned on the second insulating layer, a third insulating layer positioned on the third passivation layer, and a third via positioned along the third passivation layer and the third insulating layer.
The present disclosure relates to a semiconductor structure and a method for fabricating the semiconductor device, and more particularly, to a multi-stacking carrier structure and a method for fabricating the semiconductor device with the multi-stacking carrier structure.
DISCUSSION OF THE BACKGROUNDSemiconductor devices are used in a variety of electronic applications, such as personal computers, cellular telephones, digital cameras, and other electronic equipment. The dimensions of semiconductor devices are continuously being scaled down to meet the increasing demand of computing ability. However, a variety of issues arise during the scaling-down process, and such issues are continuously increasing. Therefore, challenges remain in achieving improved quality, yield, performance, and reliability and reduced complexity.
This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.
SUMMARYOne aspect of the present disclosure provides a semiconductor device including a substrate; an inter-dielectric layer positioned on the substrate; a conductive pad positioned in the inter-dielectric layer; and a multi-stacking carrier structure comprising a first tier comprising a first passivation layer positioned on the inter-dielectric layer, a first insulating layer positioned on the first passivation layer, and a first via positioned along the first passivation layer and the first insulating layer, and electrically connected to the conductive pad; a second tier positioned on the first tier and comprising a second passivation layer positioned on the first insulating layer, a second insulating layer positioned on the second passivation layer, and a second via positioned along the second passivation layer and the second insulating layer, and electrically connected to the first via; and a third tier positioned on the second tier and comprising a third passivation layer positioned on the second insulating layer, a third insulating layer positioned on the third passivation layer, and a third via positioned along the third passivation layer and the third insulating layer, and electrically connected to the second via.
Another aspect of the present disclosure provides a multi-stacking carrier structure including an etch stop layer; a first tier comprising a first passivation layer positioned on the etch stop layer, a first insulating layer positioned on the first passivation layer, and a first via positioned along the first passivation layer and the first insulating layer; a second tier positioned on the first tier and comprising a second passivation layer positioned on the first insulating layer, a second insulating layer positioned on the second passivation layer, and a second via positioned along the second passivation layer and the second insulating layer, and electrically connected to the first via; and a third tier positioned on the second tier and comprising a third passivation layer positioned on the second insulating layer, a third insulating layer positioned on the third passivation layer, and a third via positioned along the third passivation layer and the third insulating layer, and electrically connected to the second via.
Another aspect of the present disclosure provides a method for fabricating a semiconductor device including providing a substrate; forming an inter-dielectric layer on the substrate; forming a conductive pad in the inter-dielectric layer; forming a first tier on the inter-dielectric layer, wherein the first tier comprises a first passivation layer on the inter-dielectric layer, a first insulating layer on the first passivation layer, and a first via along the first passivation layer and the first insulating layer, and electrically connected to the conductive pad; forming a second tier on the first tier, wherein the second tier comprises a second passivation layer on the first insulating layer, a second insulating layer on the second passivation layer, and a second via along the second passivation layer and the second insulating layer, and electrically connected to the first via; and forming a third tier on the second tier, wherein the third tier comprises a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer, and a third via along the third passivation layer and the third insulating layer, and electrically connected to the second via. The first tier, the second tier, and the third tier together configure a multi-stacking carrier structure.
Another aspect of the present disclosure provides a method for fabricating a semiconductor device including providing a sacrificial carrier; temporarily attaching an etch stop layer on the sacrificial carrier; forming a multi-stacking carrier structure on the etch stop layer, wherein the multi-stacking carrier structure comprises a first tier on the etch stop layer, a second tier on the first tier, and a third tier on the second tier; providing a substrate; forming an inter-dielectric layer on the substrate; forming a conductive pad in the inter-dielectric layer; flipping the multi-stacking carrier structure and bonding the multi-stacking carrier structure onto the inter-dielectric layer; detaching the sacrificial carrier from the etch stop layer; and thinning the substrate.
Due to the design of the semiconductor device of the present disclosure, the multi-stacking carrier structure may serve as a temporary carrier to assist a thinning process of the substrate. Therefore, no carrier is needed during the thinning process of the substrate. As a result, the cost of fabricating of the semiconductor device may be reduced. In addition, after the thinning process, the multi-stacking carrier structure may provide an electrical path connecting to device elements of the semiconductor device. As a result, the performance of the semiconductor device may be easily analyzed in the presence of the multi-stacking carrier structure.
The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
It should be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly connected to or coupled to another element or layer, or intervening elements or layers may be present.
It should be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. Unless indicated otherwise, these terms are only used to distinguish one element from another element. Thus, for example, a first element, a first component or a first section discussed below could be termed a second element, a second component or a second section without departing from the teachings of the present disclosure.
Unless the context indicates otherwise, terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to reflect this meaning. For example, items described as “substantially the same,” “substantially equal,” or “substantially planar,” may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.
In the present disclosure, a semiconductor device generally means a device which can function by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the category of the semiconductor device.
It should be noted that, in the description of the present disclosure, above (or up) corresponds to the direction of the arrow of the direction Z, and below (or down) corresponds to the opposite direction of the arrow of the direction Z.
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In some embodiments, the thickness TO of the substrate 101 may be less than about 200 μm, less than about 50 μm, or less than about 10 μm. For example, the thickness TO of the substrate 101 may be about 3 μm.
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It should be noted that, in the description of present disclosure, the term “about” modifying the quantity of an ingredient, component, or reactant of the present disclosure employed refers to variation in the numerical quantity that can occur, for example, through typical measuring and liquid handling procedures used for making concentrates or solutions. Furthermore, variation can occur from inadvertent error in measuring procedures, differences in the manufacture, source, or purity of the ingredients employed to make the compositions or carry out the methods, and the like. In one aspect, the term “about” means within 10% of the reported numerical value. In another aspect, the term “about” means within 5% of the reported numerical value. Yet, in another aspect, the term “about” means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value.
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In some embodiments, the plurality of device elements and the plurality of conductive features may together configure functional units of the semiconductor device 1A. A functional unit, in the description of the present disclosure, generally refers to functionally related circuitry that has been partitioned for functional purposes into a distinct unit. In some embodiments, functional units may be typically highly complex circuits such as processor cores, memory controllers, or accelerator units. In some other embodiments, the complexity and functionality of a functional unit may be more or less complex.
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For brevity, clarity, and convenience of description, only one first via 215 is described.
In some embodiments, the sidewall 215SW of the first via 215 may be tapered. The width W0 of the bottom surface 215BS of the first via 215 may be less than the width W1 of the top surface 215TS of the first via 215. In some embodiments, the first via 215 may include a filler layer FL, a seed layer SL, an adhesion layer AL, a barrier layer BL, and an isolation layer IL.
It should be noted that, in the description of the present disclosure, a surface of an element (or a feature) located at the highest vertical level along the dimension Z is referred to as a top surface of the element (or the feature). A surface of an element (or a feature) located at the lowest vertical level along the dimension Z is referred to as a bottom surface of the element (or the feature).
It should be noted that, in the description of the present disclosure, a “width” refers to a size of an element (e.g., a layer, plug, trench, hole, opening, etc.) in a cross-sectional perspective measured from a side surface to an opposite surface of the element. The term “thickness” may substitute for “width” where indicated.
The filler layer FL may be disposed along the first insulating layer 213 and the first passivation layer 211, and disposed on the conductive pad 105. In some embodiments, the filler layer FL may have an aspect ratio between about 1:2 and about 1:35 or between about 1:10 and about 1:25. The filler layer FL may be formed of, for example, doped polysilicon, tungsten, copper, carbon nanotube, or solder alloy.
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In some embodiments, the adhesion layer AL may have a U-shaped cross-sectional profile. The adhesion layer AL may be disposed between the seed layer SL and the first insulating layer 213, between the seed layer SL and the first passivation layer 211, and between the seed layer SL and the conductive pad 105. The seed layer SL may be formed of, for example, titanium, tantalum, titanium tungsten, or manganese nitride. The seed layer SL may improve an adhesion between the seed layer SL and the barrier layer BL.
In some embodiments, the barrier layer BL may have a U-shaped cross-sectional profile. The barrier layer BL may be between the adhesion layer AL and the first insulating layer 213, between the adhesion layer AL and the first passivation layer 211, and between the adhesion layer AL and the conductive pad 105. The barrier layer BL may be formed of, for example, tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride, or tantalum nitride/tantalum bilayer. The barrier layer BL may inhibit diffusion of the conductive materials of the filler layer FL into the first insulating layer 213, the first passivation layer 211, or the inter-dielectric layer 103.
In some embodiments, the isolation layer IL may be disposed between the barrier layer BL and the first insulating layer 213, and between the barrier layer BL and the first passivation layer 211. In some embodiments, the isolation layer IL may be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, or tetra-ethyl ortho-silicate. The isolation layer IL may have a thickness between about 50 nm and about 200 nm. In some embodiments, the isolation layer IL may be formed of, for example, parylene, epoxy, or poly(p-xylene). The isolation layer IL may have a thickness between about 1 μm and about 5 μm. The isolation layer IL may ensure the filler layer FL is electrically isolated in the first insulating layer 213 and the first passivation layer 211.
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It should be noted that, in the description of present disclosure, the number of the tiers of the multi-stacking carrier structure 200 is for illustration purpose only. In other words, the number of the tiers of the multi-stacking carrier structure 200 may be greater than or less than five.
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It should be noted that, in the description of the present disclosure, silicon oxynitride refers to a substance which contains silicon, nitrogen, and oxygen and in which a proportion of oxygen is greater than that of nitrogen. Silicon nitride oxide refers to a substance which contains silicon, oxygen, and nitrogen and in which a proportion of nitrogen is greater than that of oxygen.
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The multi-stacking carrier structure 200 may serve as a temporary carrier during a thinning process of the substrate 101. With the assistance of the multi-stacking carrier structure 200, the performance of the semiconductor device 1A including the substrate 101 less than 10 μm can be analyzed. In contrast, a conventional semiconductor device including a substrate less than 10 μm is covered by a carrier so that the performance thereof may not be analyzed easily.
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It should be noted that, in the description of the present disclosure, the terms “forming,” “formed” and “form” may mean and include any method of creating, building, patterning, implanting, or depositing an element, a dopant or a material. Examples of forming methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusing, depositing, growing, implantation, photolithography, dry etching, and wet etching.
It should be noted that, in the description of the present disclosure, the functions or steps noted herein may occur in an order different from the order noted in the figures. For example, two figures shown in succession may in fact be executed substantially concurrently or may sometimes be executed in a reversed order, depending upon the functionalities or steps involved.
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The greater width of the second pattern opening 520O may be transferred to the second via opening 225O and then inherited by the second vias 225. The greater width of the second vias 225 may provide a larger tolerance window for subsequent photolithography process (e.g., photolithography process for the third via 235). As a result, the yield of the semiconductor device 1A may be improved.
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It should be noted that the third via 235 seems deviated from the second via 225 along the direction Z to emphasis the benefit of larger tolerance window of a photolithography process gained be the wider width of the second via 225. That is, even the alignment of the photolithography process is shifted, the vias 225, 235 can still electrically connect properly.
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In some embodiments, before a thinning process of the substrate 101, the thickness ratio of the thickness TL of the multi-stacking carrier structure 200 to the thickness T0 of the substrate 101 may be between about 5:7 and about 1:1, or between about 1:1 and about 7:5.
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In the semiconductor device 1B, the plurality of redistribution layers 205 may be formed on the plurality of fifth vias 255, respectively and correspondingly. In some embodiments, the formation of the plurality of redistribution layers 205 may include forming one or more insulation layers (i.e., the top passivation layer 203) using any suitable method (e.g., a spin-on coating technique, sputtering, and the like) and forming conductive features (i.e., the plurality of redistribution layers 205) in the insulation layers. The formation of the conductive features may include patterning the insulation layers (e.g., using photolithography and/or etching processes) and forming conductive features in the patterned insulation layers (e.g., by depositing a seed layer, using a mask layer to define the shape of the conductive features, and using an electroless/electrochemical plating process). For example, the plurality of first top openings 203O may define the pattern of the plurality of redistribution layers 205. The plurality of redistribution layers 205 may be formed in the plurality of first top openings 203O.
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In the semiconductor device 1D, the etch stop layer 207 may be completely removed. A top passivation layer 203 may be formed on the first tier 210 with a procedure similar to that illustrated in
One aspect of the present disclosure provides a semiconductor device including a substrate; an inter-dielectric layer positioned on the substrate; a conductive pad positioned in the inter-dielectric layer; and a multi-stacking carrier structure comprising a first tier comprising a first passivation layer positioned on the inter-dielectric layer, a first insulating layer positioned on the first passivation layer, and a first via positioned along the first passivation layer and the first insulating layer, and electrically connected to the conductive pad; a second tier positioned on the first tier and comprising a second passivation layer positioned on the first insulating layer, a second insulating layer positioned on the second passivation layer, and a second via positioned along the second passivation layer and the second insulating layer, and electrically connected to the first via; and a third tier positioned on the second tier and comprising a third passivation layer positioned on the second insulating layer, a third insulating layer positioned on the third passivation layer, and a third via positioned along the third passivation layer and the third insulating layer, and electrically connected to the second via.
Another aspect of the present disclosure provides a multi-stacking carrier structure including an etch stop layer; a first tier comprising a first passivation layer positioned on the etch stop layer, a first insulating layer positioned on the first passivation layer, and a first via positioned along the first passivation layer and the first insulating layer; a second tier positioned on the first tier and comprising a second passivation layer positioned on the first insulating layer, a second insulating layer positioned on the second passivation layer, and a second via positioned along the second passivation layer and the second insulating layer, and electrically connected to the first via; and a third tier positioned on the second tier and comprising a third passivation layer positioned on the second insulating layer, a third insulating layer positioned on the third passivation layer, and a third via positioned along the third passivation layer and the third insulating layer, and electrically connected to the second via.
Another aspect of the present disclosure provides a method for fabricating a semiconductor device including providing a substrate; forming an inter-dielectric layer on the substrate; forming a conductive pad in the inter-dielectric layer; forming a first tier on the inter-dielectric layer, wherein the first tier comprises a first passivation layer on the inter-dielectric layer, a first insulating layer on the first passivation layer, and a first via along the first passivation layer and the first insulating layer, and electrically connected to the conductive pad; forming a second tier on the first tier, wherein the second tier comprises a second passivation layer on the first insulating layer, a second insulating layer on the second passivation layer, and a second via along the second passivation layer and the second insulating layer, and electrically connected to the first via; and forming a third tier on the second tier, wherein the third tier comprises a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer, and a third via along the third passivation layer and the third insulating layer, and electrically connected to the second via. The first tier, the second tier, and the third tier together configure a multi-stacking carrier structure.
Another aspect of the present disclosure provides a method for fabricating a semiconductor device including providing a sacrificial carrier; temporarily attaching an etch stop layer on the sacrificial carrier; forming a multi-stacking carrier structure on the etch stop layer, wherein the multi-stacking carrier structure comprises a first tier on the etch stop layer, a second tier on the first tier, and a third tier on the second tier; providing a substrate; forming an inter-dielectric layer on the substrate; forming a conductive pad in the inter-dielectric layer; flipping the multi-stacking carrier structure and bonding the multi-stacking carrier structure onto the inter-dielectric layer; detaching the sacrificial carrier from the etch stop layer; and thinning the substrate.
Due to the design of the semiconductor device of the present disclosure, the multi-stacking carrier structure 200 may serve as a temporary carrier to assist a thinning process of the substrate 101. Therefore, no carrier is needed during the thinning process of the substrate 101. As a result, the cost of fabricating of the semiconductor device 1A may be reduced. In addition, after the thinning process, the multi-stacking carrier structure 200 may provide an electrical path connecting to device elements of the semiconductor device 1A. As a result, the performance of the semiconductor device 1A may be easily analyzed in the presence of the multi-stacking carrier structure 200.
Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, and steps.
Claims
1. A multi-stacking carrier structure, comprising:
- an etch stop layer;
- a first tier comprising a first passivation layer positioned on the etch stop layer, a first insulating layer positioned on the first passivation layer, and a first via positioned along the first passivation layer and the first insulating layer;
- a second tier positioned on the first tier and comprising a second passivation layer positioned on the first insulating layer, a second insulating layer positioned on the second passivation layer, and a second via positioned along the second passivation layer and the second insulating layer, and electrically connected to the first via; and
- a third tier positioned on the second tier and comprising a third passivation layer positioned on the second insulating layer, a third insulating layer positioned on the third passivation layer, and a third via positioned along the third passivation layer and the third insulating layer, and electrically connected to the second via.
2. The multi-stacking carrier structure of claim 1, wherein a thickness of the multi-stacking carrier structure is greater than about 500 micrometers.
3. The multi-stacking carrier structure of claim 1, wherein a thickness of the first insulating layer is less than about 200 micrometers.
4. The multi-stacking carrier structure of claim 1, wherein a thickness of the first passivation layer is between about 1 micrometer and about 2 micrometers.
5. The multi-stacking carrier structure of claim 1, wherein a width of a top surface of the first via is less than a width of a top surface of the second via.
6. The multi-stacking carrier structure of claim 1, wherein a width of a top surface of the second via is less than a width of a top surface of the third via.
7. A method for fabricating a semiconductor device, comprising:
- providing a substrate;
- forming an inter-dielectric layer on the substrate;
- forming a conductive pad in the inter-dielectric layer;
- forming a first tier on the inter-dielectric layer, wherein the first tier comprises a first passivation layer on the inter-dielectric layer, a first insulating layer on the first passivation layer, and a first via along the first passivation layer and the first insulating layer, and electrically connected to the conductive pad;
- forming a second tier on the first tier, wherein the second tier comprises a second passivation layer on the first insulating layer, a second insulating layer on the second passivation layer, and a second via along the second passivation layer and the second insulating layer, and electrically connected to the first via; and
- forming a third tier on the second tier, wherein the third tier comprises a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer, and a third via along the third passivation layer and the third insulating layer, and electrically connected to the second via;
- wherein the first tier, the second tier, and the third tier together configure a multi-stacking carrier structure.
8. The method for fabricating the semiconductor device of claim 7, wherein forming the first tier on the inter-dielectric layer comprising:
- forming the first passivation layer on the inter-dielectric layer;
- forming the first insulating layer on the first passivation layer;
- forming a first mask layer on the first insulating layer and comprising a first pattern opening;
- forming a first via opening along the first insulating layer and the first passivation layer to expose the conductive pad;
- removing the first mask layer; and
- forming the first via in the first via opening.
9. The method for fabricating the semiconductor device of claim 8, further comprising forming a top passivation layer on the third tier.
10. The method for fabricating the semiconductor device of claim 9, wherein the first passivation layer comprises an oxide material, the first insulating layer comprises an oxide material, and an oxide bonding process is performed to form the first insulating layer on the first passivation layer.
11. The method for fabricating the semiconductor device of claim 10, wherein an oxide etch process is performed to form the first via opening along the first insulating layer and the first passivation layer.
12. The method for fabricating the semiconductor device of claim 11, wherein a width of the first pattern opening is greater than a width of the conductive pad.
13. The method for fabricating the semiconductor device of claim 12, further comprising forming a redistribution layer on the third via.
14. A method for fabricating a semiconductor device, comprising:
- providing a sacrificial carrier;
- temporarily attaching an etch stop layer on the sacrificial carrier;
- forming a multi-stacking carrier structure on the etch stop layer, wherein the multi-stacking carrier structure comprises: a first tier on the etch stop layer; a second tier on the first tier; and a third tier on the second tier;
- providing a substrate;
- forming an inter-dielectric layer on the substrate;
- forming a conductive pad in the inter-dielectric layer;
- flipping the multi-stacking carrier structure and bonding the multi-stacking carrier structure onto the inter-dielectric layer;
- detaching the sacrificial carrier from the etch stop layer; and
- thinning the substrate.
15. The method for fabricating the semiconductor device of claim 14, wherein forming the multi-stacking carrier structure comprising:
- forming the first tier on the etch stop layer, wherein the first tier comprises a first insulating layer on the first insulating layer and a first via along the first insulating layer and on the etch stop layer;
- forming a second tier on the first tier, wherein the second tier comprises a second passivation layer on the first insulating layer, a second insulating layer on the second passivation layer, and a second via along the second passivation layer and the second insulating layer; and
- forming a third tier on the second tier, wherein the third tier comprises a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer, and a third via along the third passivation layer and the third insulating layer.
16. The method for fabricating the semiconductor device of claim 15, wherein a sidewall of the first via is tapered and a width of a top surface of the first via is less than a width of a bottom surface of the first via.
Type: Application
Filed: Dec 23, 2021
Publication Date: Jun 29, 2023
Patent Grant number: 12165968
Inventor: WEI-ZHONG LI (TAOYUAN CITY)
Application Number: 17/560,548