ENHANCED POLYPHASE DIGITAL PRE-DISTORTION STRUCTURE WITH LOW COMPLEXITY IN RADIO TRANSMITTER

Abstract

Systems, methods, apparatuses, and computer program products for an enhanced polyphase digital pre-distortion (DPD) structure in a radio transmitter. A method may include creating a combined pre-distorted component by combining each of the pre-distorted polyphase components. Each of the plurality of pre-distorted polyphase components are single phase dependent. Further, the method may include feeding the combined pre-distorted component to an output filter to form a pre-distorted transmission signal. The method may also include generating an output signal by applying the pre-distorted transmission signal to the power amplifier to generate an output signal.

Description

CROSS

This application claims priority to Finnish patent application 20225668 filed Jul. 14, 2022, the disclosure of which is incorporated herein by reference.

FIELD

Some example embodiments may generally relate to mobile or wireless telecommunication systems, such as Long Term Evolution (LTE) or fifth generation (5G) new radio (NR) access technology, or 5G beyond, or other communications systems. For example, certain example embodiments may relate to apparatuses, systems, and/or methods for an enhanced polyphase digital pre-distortion (DPD) structure in a radio transmitter.

BACKGROUND

Examples of mobile or wireless telecommunication systems may include the Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network (UTRAN), LTE Evolved UTRAN (E-UTRAN), LTE-Advanced (LTE-A), MulteFire, LTE-A Pro, fifth generation (5G) radio access technology or NR access technology, and/or 5G-Advanced. 5G wireless systems refer to the next generation (NG) of radio systems and network architecture. 5G network technology is mostly based on NR technology, but the 5G (or NG) network can also build on E-UTRAN radio. It is estimated that NR may provide bitrates on the order of 10-20 Gbit/s or higher, and may support at least enhanced mobile broadband (eMBB) and ultra-reliable low-latency communication (URLLC) as well as massive machine-type communication (mMTC). NR is expected to deliver extreme broadband and ultra-robust, low-latency connectivity and massive networking to support the IoT.

SUMMARY

In accordance with some example embodiments, a method may include creating a combined pre-distorted component by combining each of a plurality of pre-distorted polyphase components. Each of the plurality of pre-distorted polyphase components are single phase dependent. The method may further include feeding the combined pre-distorted component to an output filter to form a pre-distorted transmission signal. The method may further include generating an output signal by applying the pre-distorted transmission signal to the power amplifier to generate an output signal.

In accordance with certain example embodiments, an apparatus may include means for creating a combined pre-distorted component by combining each of a plurality of pre-distorted polyphase components. Each of the plurality of pre-distorted polyphase components are single phase dependent. The apparatus may further include means for feeding the combined pre-distorted component to an output filter to form a pre-distorted transmission signal. The apparatus may further include means for generating an output signal by applying the pre-distorted transmission signal to the power amplifier to generate an output signal.

In accordance with various example embodiments, a non-transitory computer readable medium may include program instructions that, when executed by an apparatus, cause the apparatus to perform at least a method. The method may include creating a combined pre-distorted component by combining each of a plurality of pre-distorted polyphase components. Each of the plurality of pre-distorted polyphase components are single phase dependent. The method may further include feeding the combined pre-distorted component to an output filter to form a pre-distorted transmission signal. The method may further include generating an output signal by applying the pre-distorted transmission signal to the power amplifier to generate an output signal.

In accordance with some example embodiments, a computer program product may perform a method. The method may include creating a combined pre-distorted component by combining each of a plurality of pre-distorted polyphase components. Each of the plurality of pre-distorted polyphase components are single phase dependent. The method may further include feeding the combined pre-distorted component to an output filter to form a pre-distorted transmission signal. The method may further include generating an output signal by applying the pre-distorted transmission signal to the power amplifier to generate an output signal.

In accordance with certain example embodiments, an apparatus may include at least one processor and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to create a combined pre-distorted component by combining each of a plurality of pre-distorted polyphase components. Each of the plurality of pre-distorted polyphase components are single phase dependent. The at least one memory and instructions, when executed by the at least one processor, may further cause the apparatus at least to feed the combined pre-distorted component to an output filter to form a pre-distorted transmission signal. The at least one memory and instructions, when executed by the at least one processor, may further cause the apparatus at least to generate an output signal by applying the pre-distorted transmission signal to the power amplifier to generate an output signal.

In accordance with various example embodiments, an apparatus may include creating circuitry configured to perform creating a combined pre-distorted component by combining each of a plurality of pre-distorted polyphase components. Each of the plurality of pre-distorted polyphase components are single phase dependent. The apparatus may further include feeding circuitry configured to perform feeding the combined pre-distorted component to an output filter to form a pre-distorted transmission signal. The apparatus may further include generating circuitry configured to perform generating an output signal by applying the pre-distorted transmission signal to the power amplifier to generate an output signal.

BRIEF DESCRIPTION OF THE DRAWINGS

For proper understanding of example embodiments, reference should be made to the accompanying drawings, wherein:

FIG. 1 an example enhanced polyphase digital pre-distortion (EPD) structure that linearizes a power amplifier (PA) over a large bandwidth (BW) with a minimal requirement on a sample rate.

FIG. 2 illustrates an example of a polyphase structure with single phase dependency, according to certain example embodiments.

FIG. 3 illustrates an example system representation of a digital pre-distortion (DPD) with a diagonal S-matrix, according to certain example embodiments.

FIG. 4 illustrates an example polyphase representation of S₁ with basis function filtering, according to certain example embodiments.

FIG. 5 illustrates an example polyphase representation of sub-sampled S-matrix belonging to S₁ with basis function filtering, according to certain example embodiments.

FIG. 6 illustrates another example polyphase representation of sub-sampled S-matrix belonging to S₁ with basis function filtering, according to certain example embodiments.

FIG. 7 illustrates another example polyphase representation of sub-sampled S-matrix S₁ with basis function filtering, according to certain example embodiments.

FIG. 8 illustrates an example polyphase representation of sub-sampled output finite impulse response (FIR) filter, according to certain example embodiments.

FIG. 9 illustrates an example polyphase representation of sub-sampled output FIR filter, according to certain example embodiments.

FIG. 10 illustrates an example DPD block diagram, according to certain example embodiments.

FIG. 11(a) illustrates an example S-matrix for standard polyphase DPD (SPD) and basic EPD, according to certain example embodiments.

FIG. 11(b) illustrates an example S-matrix for sub-sampled S-matrix (SS) EPD, according to certain example embodiments.

FIG. 11(c) illustrates an example S-matrix sub-sampled output filter (SoF) EPD according to certain example embodiments.

FIG. 12 illustrates an example transmission feedback (TX-FB) error spectrum for all four engines in experiment set I, according to certain example embodiments.

FIG. 13(a) illustrates an example S-matrix for SPD and basic EPD, according to certain example embodiments.

FIG. 13(b) illustrates an example S-matrix SS EPD, according to certain example embodiments.

FIG. 13(c) illustrate an example S-matrix for SoF EPD, according to certain example embodiments.

FIG. 14 illustrates an example TX-FB error spectrum for all four engines in experiment set II, according to certain example embodiments.

FIG. 15 illustrates an example flow diagram of a method, according to certain example embodiments.

FIG. 16 illustrates a set of apparatuses, according to certain example embodiments.

DETAILED DESCRIPTION

It will be readily understood that the components of certain example embodiments, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. The following is a detailed description of some example embodiments of systems, methods, apparatuses, and computer program products for an enhanced polyphase DPD (EPD) structure in a radio transmitter. For instance, in some example embodiments, the EPD structure may include sub-sampled output filter.

The features, structures, or characteristics of example embodiments described throughout this specification may be combined in any suitable manner in one or more example embodiments. For example, the usage of the phrases “certain embodiments,” “an example embodiment,” “some embodiments,” or other similar language, throughout this specification refers to the fact that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment. Thus, appearances of the phrases “in certain embodiments,” “an example embodiment,” “in some embodiments,” “in other embodiments,” or other similar language, throughout this specification do not necessarily refer to the same group of embodiments, and the described features, structures, or characteristics may be combined in any suitable manner in one or more example embodiments. Further, the terms “base station”, “cell”, “node”, “gNB”, “network” or other similar language throughout this specification may be used interchangeably.

As used herein, “at least one of the following: <a list of two or more elements>” and “at least one of <a list of two or more elements>” and similar wording, where the list of two or more elements are joined by “and” or “or,” mean at least any one of the elements, or at least any two or more of the elements, or at least all the elements.

FIG. 1 illustrates an example EPD structure 100 that linearizes a power amplifier (PA) over a large bandwidth (BW) with a minimal requirement on a sample rate. In particular, as illustrated in FIG. 1, the EPD structure 100 receives an incoming signal x(k) 101. The incoming signal x(k) is received at multiple polyphase filters 105a, 105b, 105c. Instead of pre-distorting the transmission signal x(k) directly with a single pre-distorter circuitry (e.g., using a single pre-distortion model and with certain pre-distortion model coefficients), the transmission signal x(k) is divided into two or more polyphase components of the transmission signal before pre-distorting. The polyphase components may be given by a polyphase decomposition of the transmission signal x(k).

As illustrated in FIG. 1, the division into polyphase components may be realized using a set of input polyphase filters 105a, 105b, 105c, one for each polyphase component. Division into polyphase components may also be realized using two or more parallel pre-distorters 110a, 110b, 110c, a set of output polyphase filters 115a, 115b, 115c, and a summer 125. In certain example embodiments, each of the input polyphase filters 105a, 105b, 105c, may be finite impulse response (FIR) filters whose impulse response (or response to any finite length input) is of finite duration, settling to zero in finite time.

By performing a polyphase decomposition by feeding the transmission signal to a set of input polyphase filters 105a, 105b, 105c configured in different ways, a set of polyphase signal sharing a first sampling rate may be produced. As the different polyphase component signals have been sampled at different time instances, they may provide different information about the transmission signal. By combining the information carried in the set of signals, the original transmission signal may be reproduced with a second sampling rate where the second sampling rate may be equal to or larger than the first sampling rate. The second sampling rate may also be called a virtual sampling rate as the corresponding sampling is achieved by simulating a signal with a high sampling rate with multiple signals with lower sampling rates. For example, if two polyphase components of the transmission signal are produced by two FIR filters, the two polyphase components may be combined to form a transmission signal with double the sampling rate compared to the sampling rate of the individual polyphase components by taking every other sample from the first polyphase component signal and every other from the second polyphase component signal. Therefore, by performing the polyphase division, the sample rate needed for a system may be reduced with little effect on the overall performance.

After the two or more polyphase components of the transmission signal have been created, these polyphase component signals are fed to two or more parallel pre-distorters 110a, 110b, 110c. As illustrated in FIG. 1, each polyphase component of the transmission signal may be fed to one or more parallel pre-distorters 110a, 110b, 110c of the two or more parallel pre-distorters 110a, 110b, 110c where they may be used to form a signal with an increased number of samples compared to the individual polyphase components. That is, the input signals of each parallel pre-distorter 110a, 110b, 110c may include one more more polyphase components of the transmission signal.

As illustrated in FIG. 1, the input signals of each parallel pre-distorter 110a, 110b, 110c may include all the polyphase components of the transmission signal produced by the input polyphase filters 105a, 105b, 105c. The parallel pre-distorters 110a, 110b, 110c may perform nonlinear memory-based modeling on the polyphase component signals according to predistortion models with predistortion coefficients determined and communicated to the parallel pre-distorter 110a, 110b, 110c by the identification unit 120 to compensate for the nonlinearity of the PA 135.

As further illustrated in FIG. 1, the identification unit 120 may take the transmission signal x(k), the pre-distorted transmission output signal y(k) 127, and the output signal of the PA 135 as its input signals. However, the identification unit 120 may only take as its input the output signal of the PA 135 and one of the transmission signal and the output signal y(k) 127. The identification may be configured unit may be configured to optimize the pre-distortion models and their coefficients based on input signals such that linear response is achieved for the total cascade formed by the polyphase filters, the digital-to-analog converter 130, and the PA 135. For instance, the identification unit 120 may first identify the response of the PA 135 (e.g., a PA model and/or an inverse PA model), and then evaluate what the optimal configuration of the parallel pre-distorters 110a, 110b, 110c would be to compensate for the nonlinearities of the PA 135 response. Determination of the optimal configuration may include selecting a pre-distortion model and a set of pre-distortion parameter values for the model for each of the parallel pre-distorters 110a, 110b, 110c. The pre-distortion models may be described using weighted polynomials, weighted Taylor series, weighted Volterra series, piecewise linear functions, splines, sum of time-shifted relations of an input variable with weights, or any combination of the above-mentioned types.

As also illustrated in FIG. 1, after the two or more polyphase components of the transmission signal have been pre-distorted by the two or more parallel pre-distorters 110a, 110b, 110c, each of the output signals x_pred(k) of the parallel pre-distorters 110a, 110b, 110c are fed to a corresponding polyphase filter 115a, 115b, 115c and filtered again using different (output) filtering coefficients and/or orders. This second set of filters 115a, 115b, 115c may act as recombination filters, performing filtering such that the resulting signals may be summed together by the summer 125. The summer 125 reproduces the original transmission signal x(k) or at least the shape of the original transmission signal x(k) (e.g., the amplitude may be lowered but the shape is re-solved).

In FIG. 1, in the standard configuration, the input polyphase filters 105a, 105b, 105c may create multiple phases of the incoming signal to achieve de facto un-sampling. Additionally, the output polyphase filters 115a, 115b, 115c may achieve two functions at one stroke-one is alias cancellation, and the other is BW restriction. However, in the full-fledged form, the EPD structure 100 may improve the modeling accuracy by unlocking various degrees of freedom. For example, the coefficients for the several phases may be independently identified. Additionally, each phase may have a different S-matrix, which is subject to optimization. Furthermore, the input and output polyphase filters h_poly,in,j, j=0, 1, . . . , I and h_poly,out,j, j=0, 1, . . . , I can be further optimized. These three items may turn a standard polyphase DPD (SPD) engine into an EPD one. However, two out of the three items above may need optimization, which almost invariably involves a limited number of test cases-sometimes just one. The more the parameters are tailor-made for a specific test case, the less generic they are.

Moreover, inherent in any polyphase implementation of DPD (SPD or EPD) may be the myriad of interconnections between the several phases. In one case, when every phase is dependent on all phases, that number may go as high as M². This may be burdensome in terms of hardware (HW) resources, and may not be possible to implement on legacy HW.

As described herein, certain example embodiments may provide a simpler structure that removes the interconnections between the several phases, but still retain the advantages of EPD over SPD in terms of modeling accuracy. Certain example embodiments may also replace the heavy optimization of the original EPD with methodical and direct manipulation of various parameters. As also described herein, the subclass of EPD with only the coefficients for the several phases independently identified may be called basic EPD, which represents the most basic form of EPD without any polyphase filter optimization, and with all phases sharing the same S-matrix.

Certain example embodiments described herein may have various benefits and/or advantages to overcome the disadvantages described above. For example, certain example embodiments may provide an SoF EPD structure that improves the basic EPD without resorting to optimization. Additionally, certain example embodiments are not for any specific carrier configuration and are thus versatile and flexible. Moreover, it is possible to achieve all such improvements with reduced complexity. Thus, certain example embodiments discussed below are directed to improvements in computer-related technology.

From FIG. 1, it can be seen that each DPD polyphase block is dependent upon input signals from all phases, which is true for both SPD and EPD. According to certain example embodiments, the DPD polyphase structure 100 in FIG. 1 may be simplified by severing all interconnections between the several phases so that each DPD polyphase block becomes dependent only on its own phase. This is shown in, for example, FIG. 2, which illustrates an example of a polyphase structure 200 with single phase dependency, according to certain example embodiments. As illustrated in FIG. 2, the polyphase input filters 210a, 210b, 210c receives an input transmission signal x[n] 205. The polyphase input filters E_m 210a, 210b, 210c may be by default, fractional delay filters, and G_m 220a, 220b, 220c represent the polyphase output filters. As illustrated in FIG. 2, the polyphase structure 200 has single phase dependency wherein each parallel pre-distorter 215a, 215b, 215c receives a corresponding output signal from each of the polyphase in put filters 210a, 210b, 210c. The output signals from the parallel pre-distorters 215a, 215b, 215c are filtered again by corresponding polyphase output filters 220a, 220b, 220c, after which the resultant signals are combined and transmitted as a pre-distorted transmission signal y[n] 225.

The basic clock rate of this structure 200 may be f_s/M, the basic sample period may be MT_s. Additionally, the equivalent sample rate through polyphase splitting and combining may be f_s, and the equivalent sample period may be T_s. Here in FIG. 2, f_sT_s=1. In certain example embodiments, this structure 200 may be used either as SPD or EPD, in the sense that the DPD coefficients of the several phases may be identical (as in the case of SPD), or different (as in the case of EPD).

The simplification illustrated in FIG. 2 may define a subclass of polyphase DPD (standard or enhanced), and what it represents is DPD with sub-sampled S-matrix, assuming the polyphase input and output filters remain standard. In certain example embodiments, the polyphase DPD may include a sub-sampled S-matrix because at a higher abstract level, the equivalent S-matrix now has a step size of MT_s due to the severed connections between the phases, making the DPD blocks focus exclusively on the [−f_s/(2M), f_s/(2m)] frequency region.

According to certain example embodiments, discrete linear time invariant (LTI) systems may have representations using, for example, the z-transform. The LTI systems (e.g., z-transform representation) may be useful in the case of multi-rate digital signal processors (DSP) involving polyphase structures. However, in general, DPD being a nonlinear system cannot use this representation. Instead, it may be possible to do so if certain restrictions are imposed such as, for example, on the S-matrix. For instance, it may be assumed S⊂Z×Z is the S-matrix set, and the subset that represents the S-matrix on the diagonal may be as follows:

S₁={(m,n)∈S|m=n}

If the S-matrix belongs to S1, then for each basis function, the nonlinearity may be extricated out completely and used at the input of a discrete LTI system, as illustrated in FIG. 3. For example, with respect to a basis function, based upon un-predistorted TX signal x, a predistortion signal y may be generated by applying a series of functions g₁, g₂, g₃, with coefficients, and summing the outputs, such that y=a₁*g₁(x)+a₂*g₂(x)+a₃*g₃(x)+ . . . . In some example embodiments, g₁, g₂, g₃, . . . may be basis functions since they serve as bases, and coefficients a₁, a₂, a₃, . . . may be identified by DPD.

FIG. 3 illustrates an example system representation of DPD 300 with the diagonal S-matrix S₁, where nonlinearity is extricated and placed at the inputs, according to certain example embodiments. In FIG. 3, the clock rate may be f_s everywhere, and i=0, 1, 2, . . . are indices of the basis functions. Further, x[n] is the desired transmit signal sequence, v_i[n] are signal sequences the sum of which over i form the pre-distortion signal z[n], ϕ_i are the eigen-functions, and H⁽ⁱ⁾(z) represent linear filters, the taps of which may be determined by the S-matrices belonging to S₁, and the coefficients of which are exactly those of the basis functions to be identified.

In various example embodiments, a DPD block may include a group of S-matrix taps, each of which correspond to a series of linear or nonlinear basis functions. For example, 10 taps, each of which has 12 basis functions, would result in a total of 120 basis functions. However, if the S-matrix belongs to S1, these 120 basis functions may be grouped by basis function types, the output of which may be fed through a 10 tap filter. Node 305 may represent one member of such a group, while node 310 may represent the 10 tap filter.

According to certain example embodiments, the enhanced polyphase DPD may operate at a reduced clock rate of f_s/M from input signal throughout to the output signal. To achieve this type of operation, the system representation illustrated in FIG. 3 may be taken, and H⁽ⁱ⁾(z) and G(z) may be decomposed to the polyphase form, as illustrated in FIG. 4. In particular, FIG. 4 illustrates a polyphase decomposition of FIG. 3, according to certain example embodiments. As illustrated in FIG. 4, there is a total of M² interconnections between the M phases.

The simplification exemplified in FIG. 2 may be equivalent to setting H_mⁱ(z^M) to zero for all m≥1, resulting in FIG. 5. FIG. 5 illustrates an example polyphase representation of sub-sampled S-matrix belonging to S₁ 500 with basis function filtering, according to certain example embodiments. Since linear systems may be commutable, H₀ⁱ(z^M) 410a may be moved next to G_m(z^m), where m=0, 1, . . . , M−1 to facilitate the use of Nobel Identity when the output v_i[n] is to be down-sampled by M, as illustrated in FIG. 6. In particular, FIG. 6 illustrates an example polyphase representation of sub-sampled S-matrix belonging to S₁ 600 with basis function filtering, according to certain example embodiments. Finally, as illustrated in FIG. 7, the Noble Identity is used to simplify the filter blocks. Specifically, FIG. 7 illustrates an example polyphase representation of sub-sampled S-matrix S₁ 700 with basis function filtering, according to certain example embodiments.

According to certain example embodiments, the coefficients of H₀ⁱ(z) are to be identified. In SPD, all phases may share the same H₀ⁱ(z). However, the identification should not be performed on a single phase only, as this may have aliases built in while the feedback signal does not. Instead, the identification may be performed by adding all phases for each basis function and each S-matrix tap. In EPD, different phases may have different H₀ⁱ(z), in terms of coefficients at the very least, and in terms of taps in general.

In certain example embodiments, it may be important to observe that for the S-matrix taps that are identical among the several phases, even though their coefficients are identified independently in EPD, no new frequency information is added. If, for example, each phase has the same 10-tap S-matrix, then the overall DPD system may still be a 10-tap system, only for each basis function of each tap, M coefficients are identified, which eventually adds up to only one coefficient (see FIGS. 5-7). This may also be true for generic basic EPD. As discussed herein, the method of EPD with sub-sampled S-matrix may be known as SS EPD.

Examining the structure in FIG. 4, an alternative way of simplification may be achieved. For instance, as illustrated in FIG. 8, in certain example embodiments, rather than sub-sampling the S-matrix, the DPD output FIR filter can be sub-sampled by setting G_m(z^M) to zero for all m≥1. Specifically, FIG. 8 illustrates an example polyphase representation of sub-sampled output FIR filter 800, according to certain example embodiments.

FIG. 9 illustrates an example polyphase representation of sub-sampled output FIR filter 900, according to certain example embodiments. In particular, the transformation illustrated in FIG. 9 is similar to that illustrated in FIG. 7.

As illustrated in FIGS. 8 and 9, the output FIR filter G(z) restricts the DPD linearization BW to f_p, which must be smaller than f_s/M so that the DPD output signal may be downsampled by M without aliasing. From the angle of polyphase filter implementation, for G_m(z), m=0, 1, . . . , M−1 may serve two functions including, for example, alias cancellation, and further DPD linearization BW restriction. According to certain example embodiments, G(z) may be decomposed into the product of two polynomials G(z)=G′(z)G″(z), where G′(z) restricts the BW to f_s/M, and, thus, achieving alias cancellation when the signal is downsampled. Additionally, G″(z) restricts the signal further down to f_p<f_s/M. It is G″(z) that can be downsampled by M since the incoming signal after G′(z) is already bandlimited to f_s/M. In the case of the simplification described above, G′(z) may be absorbed into H⁽ⁱ⁾(z), which is to be identified. This is because, given an alias free feedback (FB) signal with a sample rate of f_s/M, the DPD parameter identification will yield coefficients that naturally restrict the DPD output signal to within f_s/M, thereby relieving the basis function FIR filter G(z) from its alias cancellation function, making it possible to safely downsample G(z) by M. Thus, according to certain example embodiments, the number of DPD output filters may be reduced by M-fold.

In various example embodiments, an M-fold polyphase output filter may be reduced to a single filter, that the interconnections between the several phases can be severed, and that these can be done without losing either the number of S-matrix taps or the resolution thereof.

FIG. 10 illustrates an example DPD block diagram 1000, according to certain example embodiments. In particular, FIG. 10 illustrates a polyphase with sub-sampled output filter. In certain example embodiments, for the DPD block 1000 to function, the DPD coefficients for the several phases may not be identical, and may be independently identified. As previously described, with the basic EPD illustrated in FIG. 1 and the SS EPD illustrated in FIG. 2, by merely identifying the DPD coefficients for the several phases separately, does not increase the number of modeling taps, which results in in an unrefined frequency resolution. In contrast, SoF EPD may increase the number of modeling taps by M-fold. For instance, with reference to FIG. 8, the coefficients of H₀⁽ⁱ⁾, H₁⁽ⁱ⁾, . . . H_(M-1)⁽ⁱ⁾ interleaves each other by design, and together form MN coefficients for this i^th function, where N is the number of taps for each H₀⁽ⁱ⁾, H₁⁽ⁱ⁾, . . . H_(M-1)⁽ⁱ⁾. Additionally, with reference to FIG. 10, the integer nonlinear tap delays in each DPD₀, DPD₁, . . . DPD_M-1 block are shifted by the fractional delay filters E₀, E₁, . . . E_M-1, making it impossible for any two taps between two different phases to be the same, and consequently increasing the total number of taps to MN. Thus, since no two taps between two different phases are the same, it may be possible to improve the numerical condition number of the identification problem.

According to certain example embodiments, it may be possible to verify the results achieved by the SoF EPD. For instance, verification may be achieved between SS EPD and SoF EPD since they share the same model complexity, where the only difference is in the coefficients of the output polyphase filter. However, basic EPD with interconnections between the several phases may be quite different from SS EPD and SoF EPD. For comparison, an S-matrix of the same size with SS EPD may be selected. The basis functions may be kept the same throughout so that the total number of modeling coefficients remain the same. Finally, SPD is added into the comparison as well to provide a reference as it may have the same block diagram representation with basic EPD, but the DPD blocks in the several phases may share the same coefficients. Thus, in total, there may be four engines for comparison.

In certain example embodiments, the device-under-test (DUT) may be a 40 W average power GaN PA designed for C-band (between 3700 MHz and 3980 MHz). A test signal of 2×NR100 may be used side by side with 7.6 dB PAR, and centered at 3800 MHz. The learning algorithm used for all the experiments may be a direct learning algorithm (DLA) with 10 iterations. Two sets of experiments may be performed, wherein one experiment aims at 400 MHz linearization BW, and the other at 800 MHz. The two sets of experiments are summarized in Table 1 below.

TABLE 1
DUT Experimental Summary
Experiment
set	DPD BW	fs	M	Size of S-matrix for each phase
I	400	1966.08	4	8
	MHz	Msps
II	800	166.08	2	10
	MHz	Msps

As illustrated in Table 1, f_s is the effective sample rate of the DPD system, and M is the number of phases. Additionally, the effective sample rate f_s equals the base clock rate of the polyphase system multiplied by M.

In certain example embodiments, within each set, upon the last iteration, several figures of merit may be used to compare the effectiveness of four engines including, for example, mean square error (MSE) between the FB and TX signal, and an adjacent channel leakage ratio (ACLR) of the PA output signal. In certain example embodiments, the MSE between the FB and TX signal may calculate how closely the PA output signal matches the desired transmit signal, and a power spectra of various signals may be plotted for direct visual comparison.

In the first experiment set of Table 1, the base clock rate of the polyphase structure may be set to 491.52 MPs, and the number of phases M may be set to 4. The effective sample rate of the system may be f_s=4×491.52=1966.08 Msps. The DPD linearization BW may be set to 400 MHz, and the effective S-matrices used are illustrated in FIGS. 11(a)-11(c). In particular, FIG. 11(a) illustrates an example S-matrix for SPD and basic EPD, according to certain example embodiments. FIG. 11(b) illustrates an example S-matrix for SS EPD, according to certain example embodiments, and FIG. 11(c) illustrates an example S-matrix SoF EPD according to certain example embodiments. As further illustrated in FIGS. 11(a)-11(c), the corresponding effective clock rate f_s is 4×491.52=1966.08 Msps, and the effective step size is T_s=1/f. In FIG. 11(a), since the step size is T_s, interconnections between the several phases may be required, which is contrary to the case of FIGS. 11(b) and 11(c).

In certain example embodiments, the step size of the delay in FIG. 11(a) is T_s, the step size of the delay in FIG. 11(b) is 4T_s, and the steps size of the delay for each phase in FIG. 11(c) is 4T_s, but the overall step size achieved in FIG. 11(c) is T_s. The S-matrices illustrated in FIGS. 11(a)-11(c) are called effective because they are the S-matrices at f_s when the details of polyphase implementation are abstracted out. Here, the benefit of SoF EPD may be visible as it increases the number of S-matrix taps by M-fold, fully taking advantage of and consequently fully justifying the independent identification of DPD coefficients in several phases.

Table 2 compares the MSE and ACLR of SPD, basic EPD, SS EPD, and SoF EPD (i.e., engines).

TABLE 2
Experiment set I result comparison.
Engine	MSE (dB)	ACLR Lower (dBC)	ACLR Upper (dBC)
SPD	−34.15	−46.21	−46.50
Basic EPD	−41.27	−46.61	−46.15
SS EPD	−36.56	−39.51	−40.28
SoF EPD	−43.19	−48.60	−50.00

As shown in FIG. 12, it can be seen that SoF EPD outperforms all other engines in all figures of merit. This agrees with the theoretical analysis and shows the power of SoF EPD. Additionally, it can be seen that basic EPD has much better MSE than SPD, but the ACLR values thereof are comparable. Thus, the difference in MSE lies mostly underneath the carrier. This is illustrated in FIG. 12, where the spectra of the error signal are plotted for all four engines. In particular, FIG. 12 illustrates an example TX-FB error spectrum for all four engines in experiment set I, according to certain example embodiments. In certain example embodiments, each engine may run a base clock rate of 491.52 Msps, and each engine may have four phases.

In the second experiment set of Table 1, the base clock rate of the polyphase structure may be set to 983.04 Msps, and the number of phases M may be set to 2. Thus, the effective sample rate of the system is f_s=2×983.04=1966.08 Msps. Additionally, the DPD linearization BW is set to 800 MHz, and the effective S-matrices used are illustrated in FIGS. 13(a)-13(c). In particular, FIG. 13(a) illustrates an example S-matrix for SPD and basic EPD, according to certain example embodiments. FIG. 13(b) illustrates an example S-matrix SS EPD, according to certain example embodiments. FIG. 13(c) illustrate an example S-matrix for SoF EPD, according to certain example embodiments. The step size of the delay in FIG. 13(a) is T_s, the step size of the delay in FIG. 13(b) is 2T_s, and the steps size of the delay for each phase in FIG. 13(c) is 2T_s, but the overall step size achieved in FIG. 13(c) is T_s.

As illustrated in FIGS. 13(a)-13(c), the effective clock rate f_s is 2×983.04=1966.08 Msps, and the effective step size is T_s=1/f_s. In FIG. 13(a), since the step size is T_s, interconnections between the several phases may be required. This is contrary to the cases illustrated in FIGS. 13(b) and 13(c).

Table 3 compares the MSE and ACLR of all four engines. As seen in Table 3, SoF EPD outperforms all other engines in all figures of merit.

TABLE 3
Experiment set II result comparison.
Engine	MSE (dB)	ACLR Lower (dBC)	ACLR Upper (dBC)
SPD	−38.55	−47.24	−46.69
Basic EPD	−40.24	−47.24	−47.14
SS EPD	−39.53	−47.23	−46.87
SoF EPD	−41.24	−48.91	−50.36

FIG. 14 illustrates an example TX-FB error spectrum for all four engines in experiment set II, according to certain example embodiments. In the example of FIG. 14, each engine may run a base clock rate of 983.04 Msps, and each engine may have two phases. As illustrated in FIG. 14, SoF EPD outperforms all other engines in all figures of merit. SoF EPD also outperforms basic EPD visibly without running any optimizer, and with a significantly less complex structure. Moreover, SoF DPD is not dependent on the exact carrier configuration, making it generic. The only change in carrier that prompts a change in SoF DPD configuration may be instantaneous BW (IBW), based on which M, and the output filter BW can be increased or decreased.

FIG. 15 illustrates an example flow diagram of a method, according to certain example embodiments. In an example embodiment, the method of FIG. 15 may be performed by a network entity, or a group of multiple network elements in a 3GPP system, such as LTE or 5G-NR. For instance, in an example embodiment, the method of FIG. 15 may be performed by a radio transmitter similar to one of apparatuses 10 or 20 illustrated in FIG. 16.

According to certain example embodiments, the method of FIG. 15 may include, at 1500, receiving, at a radio transmitter, a transmission signal for linearization of a power amplifier. The method may also include, at 1505, dividing the transmission signal into a plurality of polyphase components via a plurality of polyphase input filters of the radio transmitter. The method may further include at 1510, pre-distorting each of the plurality of polyphase components by feeding each of the plurality of polyphase components to a respective digital pre-distortion circuit. In addition, the method may include, at 1515, creating a combined pre-distorted component by combining each of the pre-distorted polyphase components. Further, the method may include, at 1520, feeding the combined pre-distorted component to an output filter (Go) to form a pre-distorted transmission signal. The method may also include, at 1525, applying the pre-distorted transmission signal to the power amplifier to generate an output signal.

FIG. 16 illustrates a set of apparatuses 10 and 20 according to certain example embodiments. In certain example embodiments, apparatuses 10 and may be elements in a communications network or associated with such a network. For example, apparatus 10 may be radio transmitter of a UE, BS, or other similar radio communication computer device, and apparatus 20 may be a network (i.e., gNB).

In some example embodiments, apparatuses 10 and 20 may include one or more processors, one or more computer-readable storage medium (for example, memory, storage, or the like), one or more radio access components (for example, a modem, a transceiver, or the like), and/or a user interface. In some example embodiments, apparatuses 10 and 20 may be configured to operate using one or more radio access technologies, such as GSM, LTE, LTE-A, NR, 5G, WLAN, WiFi, NB-IoT, Bluetooth, NFC, MulteFire, and/or any other radio access technologies. It should be noted that one of ordinary skill in the art would understand that apparatuses 10 and 20 may include components or features not shown in FIG. 16.

As illustrated in the example of FIG. 16, apparatuses 10 and 20 may include or be coupled to a processors 12 and 22 for processing information and executing instructions or operations. Processors 12 and 22 may be any type of general or specific purpose processor. In fact, processors 12 and 22 may include one or more of general-purpose computers, special purpose computers, microprocessors, DSPs, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), and processors based on a multi-core processor architecture, as examples. While a single processors 12 and 22 is shown in FIG. 16, multiple processors may be utilized according to other example embodiments. For example, it should be understood that, in certain example embodiments, apparatuses 10 and 20 may include two or more processors that may form a multiprocessor system (e.g., in this case processors 12 may represent a multiprocessor) that may support multiprocessing. According to certain example embodiments, the multiprocessor system may be tightly coupled or loosely coupled (e.g., to form a computer cluster).

Processors 12 and 22 may perform functions associated with the operation of apparatuses 10 and 20 including, as some examples, precoding of antenna gain/phase parameters, encoding and decoding of individual bits forming a communication message, formatting of information, and overall control of the apparatuses 10 and 20, including processes and examples illustrated in FIGS. 1-15.

Apparatuses 10 and 20 may further include or be coupled to a memories 14 and 24 (internal or external), which may be respectively coupled to processors 12 and 24 for storing information and instructions that may be executed by processors 12 and 24. Memories 14 and 24 may be one or more memories and of any type suitable to the local application environment, and may be implemented using any suitable volatile or nonvolatile data storage technology such as a semiconductor-based memory device, a magnetic memory device and system, an optical memory device and system, fixed memory, and/or removable memory. For example, memories 14 and 24 can be comprised of any combination of random access memory (RAM), read only memory (ROM), static storage such as a magnetic or optical disk, hard disk drive (HDD), or any other type of non-transitory machine or computer readable media. The instructions stored in memories 14 and 24 may include program instructions or computer program code that, when executed by processors 12 and 22, enable the apparatuses 10 and 20 to perform tasks as described herein.

In certain example embodiments, apparatuses 10 and 20 may further include or be coupled to (internal or external) a drive or port that is configured to accept and read an external computer readable storage medium, such as an optical disc, USB drive, flash drive, or any other storage medium. For example, the external computer readable storage medium may store a computer program or software for execution by processors 12 and 22 and/or apparatuses 10 and 20 to perform any of the methods and examples illustrated in FIGS. 1-15.

In some example embodiments, apparatuses 10 and 20 may also include or be coupled to one or more antennas 15 and 25 for receiving a downlink signal and for transmitting via an UL from apparatuses 10 and 20. Apparatuses 10 and 20 may further include a transceivers 18 and 28 configured to transmit and receive information. The transceivers 18 and 28 may also include a radio interface (e.g., a modem) coupled to the antennas 15 and 25. The radio interface may correspond to a plurality of radio access technologies including one or more of GSM, LTE, LTE-A, 5G, NR, WLAN, NB-IoT, Bluetooth, BT-LE, NFC, RFID, UWB, and the like. The radio interface may include other components, such as filters, converters (for example, digital-to-analog converters and the like), symbol demappers, signal shaping components, an Inverse Fast Fourier Transform (IFFT) module, and the like, to process symbols, such as OFDMA symbols, carried by a downlink or an UL.

For instance, transceivers 18 and 28 may be configured to modulate information on to a carrier waveform for transmission by the antennas 15 and 25 and demodulate information received via the antenna 15 and 25 for further processing by other elements of apparatuses 10 and 20. In other example embodiments, transceivers 18 and 28 may be capable of transmitting and receiving signals or data directly. Additionally or alternatively, in some example embodiments, apparatus 10 may include an input and/or output device (I/O device). In certain example embodiments, apparatuses 10 and 20 may further include a user interface, such as a graphical user interface or touchscreen.

In certain example embodiments, memories 14 and 34 store software modules that provide functionality when executed by processors 12 and 22. The modules may include, for example, an operating system that provides operating system functionality for apparatuses 10 and 20. The memory may also store one or more functional modules, such as an application or program, to provide additional functionality for apparatuses 10 and 20. The components of apparatuses 10 and 20 may be implemented in hardware, or as any suitable combination of hardware and software. According to certain example embodiments, apparatuses 10 and 20 may optionally be configured to communicate each other (in any combination) via a wireless or wired communication links 70 according to any radio access technology, such as NR.

According to certain example embodiments, processors 12 and 22 and memories 14 and 24 may be included in or may form a part of processing circuitry or control circuitry. In addition, in some example embodiments, transceivers 18 and 28 may be included in or may form a part of transceiving circuitry.

For instance, in certain example embodiments, apparatus 10 may be controlled by memory 14 and processor 12 to receive, at a radio transmitter of the apparatus, a transmission signal for linearization of a power amplifier. Apparatus 10 may also be controlled by memory 14 and processor 12 to divide the transmission signal into a plurality of polyphase components via a plurality of polyphase input filters of the radio transmitter. Apparatus 10 may further be controlled by memory 14 and processor 12 to pre-distort each of the plurality of polyphase components by feeding each of the plurality of polyphase components to a respective digital pre-distortion circuit. In addition, apparatus 10 may be controlled by memory 14 and processor 12 to create a combined pre-distorted component by combining each of the pre-distorted polyphase components. Further, apparatus 10 may be controlled by memory 14 and processor 12 to feed the combined pre-distorted component to an output filter to form a pre-distorted transmission signal. Apparatus 10 may also be controlled by memory 14 and processor 12 to generate an output signal by applying the pre-distorted transmission signal to the power amplifier.

In some example embodiments, an apparatus (e.g., apparatus 10 and/or apparatus 20) may include means for performing a method, a process, or any of the variants discussed herein. Examples of the means may include one or more processors, memory, controllers, transmitters, receivers, and/or computer program code for causing the performance of the operations.

Certain example embodiments may be directed to an apparatus that includes means for performing any of the methods described herein including, for example, means for receiving, at a radio transmitter of the apparatus, a transmission signal for linearization of a power amplifier. The apparatus may also include means for dividing the transmission signal into a plurality of polyphase components via a plurality of polyphase input filters of the radio transmitter. The apparatus may further include means for pre-distorting each of the plurality of polyphase components by feeding each of the plurality of polyphase components to a respective digital pre-distortion circuit. In addition, the apparatus may include means for creating a combined pre-distorted component by combining each of the pre-distorted polyphase components. Further, the apparatus may include means for feeding the combined pre-distorted component to an output filter to form a pre-distorted transmission signal. The apparatus may also include means for generating an output signal by applying the pre-distorted transmission signal to the power amplifier to generate an output signal.

A computer program product may include one or more computer-executable components which, when the program is run, are configured to carry out some example embodiments. The one or more computer-executable components may be at least one software code or portions of it. Modifications and configurations required for implementing functionality of certain example embodiments may be performed as routine(s), which may be implemented as added or updated software routine(s). Software routine(s) may be downloaded into the apparatus.

As an example, software or a computer program code or portions of it may be in a source code form, object code form, or in some intermediate form, and it may be stored in some sort of carrier, distribution medium, or computer readable medium, which may be any entity or device capable of carrying the program. Such carriers may include a record medium, computer memory, read-only memory, photoelectrical and/or electrical carrier signal, telecommunications signal, and software distribution package, for example. Depending on the processing power needed, the computer program may be executed in a single electronic digital computer or it may be distributed amongst a number of computers. The computer readable medium or computer readable storage medium may be a non-transitory medium.

In other example embodiments, the functionality may be performed by hardware or circuitry included in an apparatus (e.g., apparatus 10 or apparatus 20), for example through the use of an application specific integrated circuit (ASIC), a programmable gate array (PGA), a field programmable gate array (FPGA), or any other combination of hardware and software. In yet another example embodiment, the functionality may be implemented as a signal, a non-tangible means that can be carried by an electromagnetic signal downloaded from the Internet or other network.

According to certain example embodiments, an apparatus, such as a node, device, or a corresponding component, may be configured as circuitry, a computer or a microprocessor, such as single-chip computer element, or as a chipset, including at least a memory for providing storage capacity used for arithmetic operation and an operation processor for executing the arithmetic operation.

One having ordinary skill in the art will readily understand that the disclosure as discussed above may be practiced with procedures in a different order, and/or with hardware elements in configurations which are different than those which are disclosed. Therefore, although the disclosure has been described based upon these example embodiments, it would be apparent to those of skill in the art that certain modifications, variations, and alternative constructions would be apparent, while remaining within the spirit and scope of example embodiments. Although the above embodiments refer to 5G NR and LTE technology, the above embodiments may also apply to any other present or future 3GPP technology, such as LTE-advanced, and/or fourth generation (4G) technology.

PARTIAL GLOSSARY

• • 3GPP 3rd Generation Partnership Project
  • 5G 5th Generation
  • 5GCN 5G Core Network
  • 5GS 5G System
  • BB Baseband
  • BS Base Station
  • BW Bandwidth
  • DCI Downlink Control Indicator
  • DL Downlink
  • DPD Digital Pre-Distortion
  • eNB Enhanced Node B
  • EPD Enhanced Polyphase DPD
  • E-UTRAN Evolved UTRAN
  • gNB 5G or Next Generation NodeB
  • LTE Long Term Evolution
  • LTI Linear Time Invariant
  • NR New Radio
  • NW Network
  • PA Power Amplifier
  • RF Radio Frequency
  • RS Reference Signals
  • SoF EPD Enhanced Polyphase DPD with Sub-Sampled Output Filter
  • SPD Standard Polyphase DPD
  • SS Sub-Sampled S-matrix
  • SS EPD Enhanced Polyphase DPD with Sub-Sampled S-matrix
  • UE User Equipment
  • UL Uplink

Claims

1. A method comprising:

creating a combined pre-distorted component by combining each of a plurality of pre-distorted polyphase components, wherein each of the plurality of pre-distorted polyphase components are single phase dependent;

feeding the combined pre-distorted component to an output filter to form a pre-distorted transmission signal; and

generating an output signal by applying the pre-distorted transmission signal to the power amplifier to generate an output signal.

2. An apparatus comprising:

at least one processor; and

at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to

create a combined pre-distorted component by combining each of a plurality of pre-distorted polyphase components, wherein each of the plurality of pre-distorted polyphase components are single phase dependent;

feed the combined pre-distorted component to an output filter to form a pre-distorted transmission signal; and

generate an output signal by applying the pre-distorted transmission signal to the power amplifier to generate an output signal.

3. An apparatus comprising:

means for creating a combined pre-distorted component by combining each of a plurality of pre-distorted polyphase components, wherein each of the plurality of pre-distorted polyphase components are single phase dependent;

means for feeding the combined pre-distorted component to an output filter to form a pre-distorted transmission signal; and

means for generating an output signal by applying the pre-distorted transmission signal to the power amplifier to generate an output signal.