POWER EFFICIENT LOAD CURRENT DERIVED SWITCH TIMING OF SWITCHING RESONANT TOPOLOGY

Abstract

Systems, devices, and methods are discussed relating to plasma sources using load current switch timing of zero volt switching resonant topology.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a continuation-in-part (CIP) of U.S. patent application Ser. No. 17/558,527 entitled “Load Current Derived Switch Timing of Switching Resonant Topology”, and filed Dec. 21, 2021 by Geissler. The entirety of the aforementioned application is incorporated herein by reference for all purposes.

FIELD

Embodiments discussed generally relate to plasma sources, and more particularly to a plasma source using load current switch timing of zero volt switching resonant topology.

BACKGROUND

Generally, plasma sources are driven by RF power supplies connected remotely through 50 Ohm coaxial cables. In these systems the plasma load impedance must be converted to 50 Ohms using an RF matching network. In some cases driving a plasma load is done by a switching power source connected directly to the plasma source through a series matching capacitor. The series matching capacitor cancels the inductive component of the plasma source when driven at the resonant frequency. To achieve this goal, the power source is switched based upon a signal generator circuit that seeks to match a resonant frequency of the plasma load. The signal generator circuit creates a synthetic frequency at which the power source is switched. In particular, the generator circuit uses a controller that receives the resonant frequency of the plasma load. Where the controller determines that the resonant frequency of the plasma load is different from the created synthetic frequency the controller modifies a frequency control that governs the synthetic frequency much like a phase lock loop. Such an approach may operate in theory, however, a high Q circuit makes it highly unstable in environments where the resonant frequency of the plasma load is varying by even small amounts. For example, it may take tens of microseconds to retune the synthetic frequency each time a minor variance in the resonant frequency of the plasma load is detected. Such retuning may be a recurring requirement that can greatly reduce the efficiency of the combination of the switching power source and the plasma load, or even damage switching power source. In addition to the unstable plasma control, the switching devices must be switched just before the resonant current reaches zero to achieve low loss zero voltage switching.

Thus, there exists a need in the art for more advanced approaches, devices and systems for providing switched power to a plasma source.

SUMMARY

Various embodiments discussed generally relate to plasma sources, and more particularly to powering a plasma source using load current switch timing of zero volt switching resonant topology.

This summary provides only a general outline of some embodiments. Many other objects, features, advantages and other embodiments will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings and figures.

BRIEF DESCRIPTION OF THE DRAWINGS

A further understanding of the various embodiments may be realized by reference to the figures which are described in remaining portions of the specification. In the figures, similar reference numerals are used throughout several drawings to refer to similar components. In some instances, a sub-label consisting of a lower-case letter is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components.

FIG. 1 is a block diagram of a power switching circuit configured to drive a resonant load in accordance with some embodiments.

FIG. 2 shows an ideal zero volt switching timing waveform including a resonant load current of the resonant load of FIG. 1 including various other signals of FIG. 1 relative to the resonant load current.

FIG. 3 is a block diagram of another power switching circuit in accordance with various embodiments.

FIG. 4 shows a diode rectifier circuit that may be used in relation to one or more embodiments.

FIG. 5 is a flow diagram showing a method in accordance with some embodiments for providing power to a resonant load.

FIG. 6 is a block diagram of a power switching circuit configured to drive a resonant load at an extended upper frequency in accordance with some embodiments.

FIG. 7 shows an attempt of the power switching circuit of FIG. 1 to perform zero volt switching at an example 2 MHz.

FIG. 8 shows an attempt of the power switching circuit of FIG. 1 to perform zero volt switching at an example 13.5 MHz.

FIG. 9 shows an attempt of the power switching circuit of FIG. 6 to perform zero volt switching at an example 13.5 MHz.

FIG. 10 is a block diagram of another power switching circuit configured to drive a resonant load at an extended upper frequency in accordance with various embodiments.

FIG. 11 is a flow diagram showing a method in accordance with some embodiments for providing power to a resonant load at an extended upper frequency.

DETAILED DESCRIPTION

Various embodiments discussed generally relate to plasma sources, and more particularly to powering a plasma source using load current switch timing of zero volt switching resonant topology.

Some embodiments provide systems, methods, and/or circuits for controlling switching power for a resonant load. The resonant frequency of the resonant load defines the frequency of the switching power eliminating the need for a synthesized frequency generation circuit. As such, the embodiments provide a response to changes in the resonant frequency of the resonant load that is faster than that expected in circuit relying on synthesized frequencies. A timing correction circuit operates to align the transition edges of the switching power devices to the current zero crossings of the resonant load.

In some cases, such direct use of the resonant frequency of the resonant load rather than a synthesized frequency allows stability of zero volt switching over wide frequency changes in the resonant load. Further, the need for a relatively expensive voltage controlled oscillator used to synthesize frequencies is eliminated. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of advantages that may be achieved in relation to different embodiments.

In some embodiments, switching is performed shortly before load current zero crossing. This assures that there is at least some current available during the switch. As used herein, the term “zero voltage switching” or “ZVS” is used in its broadest sense to mean turning off a device when the load current is positive. For very fast switching devices, the current quickly diverts to the internal capacitance of the device while the voltage across the device is still substantially zero. This offers very low switching loss since the energy stored in the device capacitance is recycled to the load in subsequent cycles. This switching prior to the load current zero crossing takes the circuit away from the resonant frequency of the load. At lower frequencies, the switching is done close enough to the zero crossing that it does not make a significant difference in the ability of the circuit to deliver power to the resonant load.

In some embodiments, a current assist inductor is added to aid switching of the resonant load. The current assist inductor, while always operational, supports switching at higher frequencies. In particular, at higher frequencies of load resonance, the previously described process of switching prior to the zero crossing results in a more substantial phase offset from the resonant load resulting in a significant reduction in power supplied to the load. The current assist inductor provides an added current that allows switching close to the resonant zero cross while maintaining complete transitions and ZVS switching.

Various methods described herein may be practiced by connecting one or more hardware circuits together, and/or a combination of one or more hardware circuits and one or more machine-readable storage media containing the code according to the present disclosure with appropriate standard computer hardware to execute the code contained therein. An apparatus for practicing various embodiments of the present disclosure may involve one or more processing resources in concert with one or more dedicated hardware circuits and storage systems containing or having network access to computer program(s) coded in accordance with various methods described herein, and the method steps of the disclosure could be accomplished by modules, routines, subroutines, or subparts of a computer program product.

Other embodiments provide processing systems that include a power switching circuit configured to provide a power signal to a resonant load. The power switching circuit is configured to switch a voltage of the power signal at a frequency of the resonant load, and begins switching the voltage before each zero current crossing of the resonant load. The processing systems further include a current injector circuit configured to add an additional current to a load current controlled by the resonant load at least at each zero current crossing of the resonant load. In some instances of the aforementioned embodiments, the processing system further includes the resonant load.

In some instances of the aforementioned embodiments, the power switching circuit includes: a transition detection circuit configured to detect transitions of the power signal through a level and to provide a corresponding transition output; a timing detection circuit configured to detect a time offset between an edge of the transition output and an edge of the power signal and provide a corresponding timing correction output; a signal generation circuit configured to generate a switch input based at least in part on a combination of the timing correction output and the transition output; and a switching drive circuit configured to change polarity of the power signal based at least in part on the switch input. In some such instances, the transition detection circuit includes a transformer configured to transform the power signal to a transformed power signal. The transition detection circuit may further include a level crossing detection circuit configured to detect a crossing of the transformed power signal through the level. The transition output is a timing signal indicating each occurrence of the crossing of the power signal through the level. A first time period between assertion of a first instance of the transition output and a second instance of the transition output can vary by more than five percent when compared to a second time period between assertion of the second instance of the transition output and a third instance of the transition output. The second instance of the transition output directly follows the first instance of the transition output and the third instance of the transition output directly follows the second instance of the transition output. In some cases, the level is a zero voltage level, and the level crossing detection circuit is a diode rectifier circuit configured to detect each zero voltage crossing.

In some such instances where the timing correction output is a voltage level, the signal generation circuit may further include: a signal ramp generator circuit configured to generate a ramp signal that ramps from a defined level at a constant rate upon assertion of the transition output; a signal ramp comparator circuit configured to assert a switch timing output each time the ramp signal is at least the voltage of voltage level of the timing correction output; and a pulse circuit configured to assert the switch input based at least in part on assertion of the switch timing output.

In various such instances, the switching drive circuit includes: a switch circuit configured to switch between a first driver output and a second driver output based upon the switch input; and a half bridge inverter circuit controlling the power signal based upon the first driver output and the second driver output. In some cases, the current injector circuit includes an inductor connected to the power signal, wherein the inductor provides the additional current to the current of the power signal. In some such cases, the current injector circuit further includes: a first capacitor connected between a first voltage level and a node; a second capacitor connected between a second voltage level and the node; and wherein the inductor is connected between the power signal and the node. In various cases, a size of the first capacitor, a size of the second capacitor, and a size of the inductor are all sufficiently large to fix a voltage at the node at a defined level.

Yet other embodiments provide methods for providing power to a load. The methods include: applying an initial impulse input to a resonant load to cause the resonant load to resonate; providing a power signal to the resonant load, wherein the power signal switches from a first voltage level to a second voltage level at a frequency corresponding to a frequency of the resonant load, and wherein the power signal includes a load current and a voltage controlled by the resonant load; beginning a transition of the power signal from the first voltage level to the second voltage level prior to the voltage of the power signal crossing a zero voltage level; and injecting an additional current, wherein the additional current is added to the load current when the voltage of the power signal crossing a zero voltage level.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without some of these specific details.

Terminology

Brief definitions of terms used throughout this application are given below.

The terms “connected” or “coupled” and related terms, unless clearly stated to the contrary, are used in an operational sense and are not necessarily limited to a direct connection or coupling. Thus, for example, two devices may be coupled directly, or via one or more intermediary circuits or devices. As another example, devices may be coupled in such a way that information can be passed there between, while not sharing any physical connection with one another. Based on the disclosure provided herein, one of ordinary skill in the art will appreciate a variety of ways in which connection or coupling exists in accordance with the aforementioned definition.

If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.

As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.

The phrases “in an embodiment,” “according to one embodiment,” and the like generally mean the particular feature, structure, or characteristic following the phrase is included in at least one embodiment of the present disclosure, and may be included in more than one embodiment of the present disclosure. Importantly, such phrases do not necessarily refer to the same embodiment.

The phrase “processing resource” is used in its broadest sense to mean one or more processors capable of executing instructions. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of processing resources that may be used in relation to a particular embodiments.

Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It will be appreciated by those of ordinary skill in the art that the diagrams, schematics, illustrations, and the like represent conceptual views or processes illustrating systems and methods embodying various aspects of the present disclosure. The functions of the various elements shown in the figures may be provided through the use of dedicated hardware as well as hardware capable of executing associated software and their functions may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic.

Various embodiments provide processing systems that include a load and a power switching circuit. The power switching circuit is configured to provide a power signal to the load, where the power signal transitions through a level based in part upon operation of the load. The power switching circuit includes: a transition detection circuit configured to detect the transitions of the power signal through the level and to provide a corresponding transition output; a timing detection circuit configured to detect a time offset between an edge of the transition output and an edge of the power signal and provide a corresponding timing correction output; a signal generation circuit configured to generate a switch input based at least in part on a combination of the timing correction output and the transition output; and a switching drive circuit configured to change polarity of the power signal based at least in part on the switch input.

In some instances of the aforementioned embodiments, a frequency of the load varies by more than ten percent. In various instances of the aforementioned embodiments, the transition detection circuit includes a transformer configured to transform the power signal to a transformed power signal. In some such instances, the transition detection circuit further includes a level crossing detection circuit configured to detect a crossing of the transformed power signal through the level. The transition output is a timing signal indicating each occurrence of the crossing of the power signal through the level. In some cases, a first time period between assertion of a first instance of the transition output and a second instance of the transition output can vary by more than five percent when compared to a second time period between assertion of the second instance of the transition output and a third instance of the transition output, where the second instance of the transition output directly follows the first instance of the transition output and the third instance of the transition output directly follows the second instance of the transition output. In various cases, the level is a zero level, and the level crossing detection circuit is a diode rectifier circuit configured to detect zero voltage crossings.

In various instances of the aforementioned embodiments, the timing correction output is a voltage level, and the signal generation circuit includes: a signal ramp generator circuit configured to generate a ramp signal that ramps from a defined level at a constant rate upon assertion of the transition output; a signal ramp comparator circuit configured to assert a switch timing output each time the ramp signal is at least the voltage of voltage level of the timing correction output; and a pulse circuit configured to assert the switch input based at least in part on assertion of the switch timing output. In some instances of the aforementioned embodiments, the switching drive circuit includes: a switch circuit configured to switch between a first driver output and a second driver output based upon the switch input; and a half bridge inverter circuit controlling the power signal based upon the first driver output and the second driver output. In some instances of the aforementioned embodiments, the timing detection circuit includes: a voltage comparator circuit configured to assert a power signal timing output each time a voltage of the power signal crosses zero volts; and an edge comparator circuit configured to assert the timing correction output at a voltage level corresponding to a difference in an edge of the power signal and the edge of the transition output. In some cases, the voltage level is: decreased when the edge of the transition output leads the edge of the power signal, and increased when the edge of the transition output lags the edge of the power signal.

Other embodiments provide methods for providing power to a resonant load. The methods include: applying an initial impulse input to the resonant load to cause the resonant load to resonate; providing a power signal to the resonant load, wherein the power signal transitions through a level based in part upon operation of the resonant load; detecting transitions in the power signal through the level; generating a transition output corresponding to the detected transitions through the level; detecting a timing offset between an edge the transition output and an edge of the power signal; generating a timing correction output corresponding to the timing offset; and generating a switch input based at least in part on a combination of the timing correction output and the transition output.

Turning to FIG. 1, a block diagram of a power switching circuit 100 is shown in accordance with some embodiments that drives a resonant load 110. Resonant load 110 is represented as a series of resistance (R), capacitance (C), and inductance (L) that when operating generally resonate at a predicted resonant frequency. However, changes in the operation parameters can cause some variance in the resonant frequency. In some embodiments, resonant load 110 is a plasma chamber used in semiconductor processing and for other purposes. Such a plasma chamber may include, but is not limited to, a chemical vapor deposition chamber, an atomic layer deposition chamber, a capacitive coupled plasma chamber, a plasma etch chamber, a plasma deposition chamber, a plasma enhanced atomic layer deposition chamber, a transformer coupled plasma reactor, or a plasma enhanced chemical vapor deposition chamber as are known in the art. Based upon the disclosed herein, one of ordinary skill in the art will recognize a variety of loads that may be used in place of resonant load 110.

Resonant load 110 is powered by a half bridge inverter circuit 126 that is switched based upon switching signals 123, 125 under control of a switch circuit 102. The switching of switching signals 123, 125 results in switching on a power output 113. Any power switching circuit known in the art may be used in place of half bridge inverter circuit 126. A current transformer 106 is connected to resonant load 110. Current transformer 106 provides a representation of current being transferred to resonant load 110 via an electrical conductor carrying a power output 113. The current being transferred to resonant load 110 exhibits the frequency at which the resonant load is operating, and this same frequency is reflected in a transformer output 119 that is provided to a current zero cross to digital output circuit 108.

Current zero cross to digital output circuit 108 includes a digital circuit that transforms transformer output 119 to a digital zero crossing output 105. Digital zero crossing output 105 switches between two voltage levels compatible with other downstream digital circuitry. As an example, digital zero crossing output 105 switches between 0 Volts and 3.3 Volts. In some embodiments, current zero cross to digital output circuit 108 is a diode rectifier circuit similar to that shown in FIG. 4 below. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuitry that can be used to convert transformer output 119 to a corresponding digital signal exhibiting the same frequency. Further, based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of voltage levels between which digital zero crossing output 105 can be switched in accordance with different embodiments.

A voltage cross level shift and delay circuit 104 is connected to power output 113, and is a voltage sensing circuit configured to sense each time the voltage of power signal 113 crosses ½ bus volts. Each time the voltage of power output 113 crosses ½ bus volts, voltage cross level shift and delay circuit 104 asserts a zero crossing output 117. Zero crossing output 117 is a digital output that switches between two voltage levels compatible with other downstream digital circuitry. As an example, zero crossing output 117 switches between 0 Volts and 3.3 Volts. In some embodiments, voltage cross level shift and delay circuit 104 is a comparator circuit with an output that switches at a desire digital voltage. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuitry that can be used to detect zero voltage crossings and assert a digital output indicating the occurrence of a zero voltage crossing.

Assertion of zero crossing output 117 corresponds to an edge of power output 113 and is provided to a timing comparison circuit 118. Timing comparison circuit 118 compares voltage zero crossing output 117 with current zero crossing output 105 to yield a phase lead output 101 and a phase lag output 103. Timing comparison circuit 118 asserts lag output 103 with a duty cycle or duration corresponding to the lag of voltage zero crossing output 117 to current zero crossing output 105. As an example, in one embodiment, Timing comparison circuit 118 is implemented as an XOR circuit operable to assert whenever there is a mismatch between voltage zero crossing output 117 to current zero crossing output 105. When the mismatch is due to voltage zero crossing output 117 leading current zero crossing output 105, a lead output 101 is asserted for a period corresponding to the mismatch (i.e., the time period that voltage zero crossing output 117 leads current zero crossing output 105; and when the mismatch is due to voltage zero crossing output 117 lagging current zero crossing output 105, lag output 103 is asserted for a period corresponding to the mismatch (i.e., the time period that voltage zero crossing output 117 lags current zero crossing output 105). Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuitry that can be used to generate lead and lag signals based upon two or more inputs.

A timing reference generator circuit 120 receives lead output 101 and lag output 103. Timing reference generator circuit 120 integrates the asserted one of lead output 101 or lag output 103 and provides a delay reference signal 121 corresponding to the amount of lead/lag between digital zero crossing output 105 and zero crossing output 117. Any integration circuit known in the art that is capable of generating a delay signal may be used as timing offset generator circuit 120.

In this embodiment, delay reference signal 121 is a substantially DC voltage that is increased to delay signal 109 (move the transition of power signal 113 to a later point and reduce the lead), or decreased to reduce the delay signal 109 (move the transition of power signal 113 to an earlier point, and thereby reduce any lag). As more fully described below, this voltage level of delay reference signal 121 is used to define a timing signal 109 that modifies the timing of the power signal provided to drive resonant load 110.

Digital zero crossing output 105 is also provided to a signal ramp generator circuit 116. Signal ramp generator circuit 116 provides a ramp signal 107 that increases in voltage at a defined rate from a start point. The start point is either a rising edge of digital zero crossing output 105 (a positive going zero crossing) or a falling edge of digital zero crossing output 105 (a negative going zero crossing). Ramp signal 107 is provided to a signal ramp comparator circuit 114 that compares ramp signal 107 with delay reference signal 121, and asserts timing signal 109 when ramp signal 107 is the same are greater than delay reference signal 121. Signal ramp comparator circuit 114 may be, but is not limited to, a comparator circuit.

Said another way, lead output 101 and lag output 103 tell timing reference generator circuit 120 when the power output 113 is changing polarity with respect to the current crossing. By delaying voltage zero crossing output 117, timing reference generator circuit 120 is thinking the voltage zero crossing points of power output 113 are too late and will compensate by lowering the voltage on delay reference signal 121 such that it will cause signal ramp generator circuit 114 to assert timing signal 109 earlier in the cycle (i.e., lower on each ramp of ramp signal 107). This is how power switching circuit 100 corrects for the delays (comparators, switch select, switch drive, and transistor delays) of various circuitry. In effect, timing signal 109 is asserted early so that the actual voltage zero crossing occurs consistent with (i.e., on time) that needed by resonant load 110.

Timing signal 109 is provided to a switch select and dead band pulse generator circuit 112. Switch select and dead band pulse generator circuit 112 toggles a gate drive signal 111 and applies a constant dead band delay to gate drive signal 111. The added dead band delay is used to tune for zero volt transitions. Gate drive signal 111 is received by switch circuit 102 where it is used to drive switch signals 123, 125, which switch a bus voltage 130. Each time gate drive signal 111 is pulsed, switch circuit 102 reverses which of drive switch signals 123, 125 is asserted.

Various prior power switching circuits use straight forward RF amplifier design techniques based upon synthetic frequency generation circuits which yield process benefits. Such approaches work well in steady state scenarios, however, most resonant loads are not ideal and as such can exhibit significant variations in the resonant frequency of the resonant load. In such RF amplifier based power switching circuits a plasma chamber load will often lose plasma and require a full re-ignition of the plasma chamber, which in some cases is not possible. The embodiments discussed herein resolve such issues by using the resonant frequency of the resonant load directly as it varies, rather than attempting to synthesize a frequency representing the resonant frequency.

Turning to FIG. 2, an ideal zero volt switching timing waveform 200 is shown including power signal 113 of resonant load 110 of FIG. 1 and including various other signals of FIG. 1 relative to power signal 113. As shown, power signal 113 switches a power output between extremes (in this case 240 A and 0 A). Power signal 113 switches at a frequency defined by the load (i.e., the load resonant frequency). Again, this is an ideal zero volt switching timing waveform 200 so the load resonant frequency does not change. However, in non-ideal scenarios, the load resonant frequency can vary significantly and embodiments disclosed herein do not unlock from the varying load resonant frequency and thus provide stable operation over a wide frequency range. In some embodiments, the load resonant frequency varies by more than five (5) percent. In various embodiments, the load resonant frequency varies by more than ten (10) percent. In one or more embodiments, the load resonant frequency varies by more than twenty (20) percent.

As shown, power signal 113 exhibits a number of zero crossings some examples of which are shown as dashed lines 205a, 205b, 205c, 205d, 205e. A transformer receives power signal 113 and produces a corresponding transformer output 119. Transformer output 119 is provided to a current zero cross to digital output circuit that provides a corresponding digital zero crossing output 105. Digital zero crossing output 105 switches between two voltage levels compatible with other downstream digital circuitry (in this case, digital zero crossing output 105 switches between 0 Volts and 3.3 Volts). Each rising edge of digital zero crossing output 105 corresponds to a directly preceding rising edge of transformer output 119, and each falling edge of digital zero crossing output 105 corresponds to a directly preceding falling edge of transformer output 119.

Each rising edge (indicated by dashed lines 210a, 210b, 210c) and each falling edge (indicated by dashed lines 215a, 215b) of digital zero crossing output 105 triggers the start of ramp signal 107 which increases in voltage at a defined rate. Ramp signal 107 is compared with delay reference signal 121 by a signal ramp comparator circuit. The value of delay reference signal 121 may be adjusted by an amount such that it can vary over an adjustment range by a timing reference generator circuit. This adjustment range may be artificially limited to limit the amount of timing adjustment that is applied, or may extend the entire range possible by ramp signal 107. In the depicted embodiment, ramp signal 107 is reset each time its voltage equals that of delay reference signal 121. In other embodiments, ramp signal 107 is reset coincident with each rising and falling edge of digital zero crossing output 105. In this embodiment, each time ramp signal 107 equals digital zero crossing output 105, gate drive signal 111 is toggled causing a switch in power signal 113.

As such, the timing of the zero crossings (i.e., the polarity changes) of power signal 113 is directly connected with the load resonant frequency. This is unlike other approaches where the frequency of the switching is indirectly generated using a frequency generation circuit that is prone to unlocking. This is particularly important in cases where the resonant load is a plasma chamber which will often lose plasma ignition when the frequency of the switching power drifts too far from the resonant frequency of the plasma chamber.

FIG. 3 shows a block diagram of another power switching circuit 300 in accordance with various embodiments. Power switching circuit 300 includes many of the same elements as power switching circuit 100 described above in relation to FIG. 1, except that switch detect and dead band pulse generator circuit 112 and signal ramp comparator circuit 114 are replaced by a processing resource 320 that executes processing resource instructions from a storage medium 340 connected to processing resource 320. Executing the processing resource instructions causes processing resource 320 to provide gate drive signal 111 based upon ramp signal 107 and delay reference signal 121 similar to that discussed above in relation to FIGS. 1-2. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of other functions of circuit elements of power switching circuit 100 that may be implemented by processing resource, and thus eliminated from the circuit.

Turning to FIG. 5, a flow diagram 500 shows a method in accordance with some embodiments for providing power to a resonant load. Following flow diagram 500, an initial impulse input is applied to the resonant load to cause the resonant load to resonate (block 502). In some embodiments, this initial resonation input that may be, for example, an initial switch transition at levels required by the load that can be repeated for load sensing. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of initial resonation inputs that may be used in relation to particular resonant loads. A power signal is provided to the resonant load (block 504). The power signal transitions through a level based in part upon operation of the resonant load. Transitions of the power signal through the level are detected (block 506). A transition output is generated that corresponds to the detected transitions through the level (block 508). A timing offset it detected between an edge the transition output and an edge of the power signal (block 510), and a generating a timing correction output is generated that corresponds to the timing offset (block 512). A switch input is generated based at least in part on a combination of the timing correction output and the transition output (block 514).

Turning to FIG. 6, a block diagram of a power switching circuit 600 is shown in accordance with some embodiments that drives a resonant load 610. Resonant load 610 is represented as a series of resistance (R), capacitance (C), and inductance (L) that when operating generally resonate at a predicted resonant frequency. However, changes in the operation parameters can cause some variance in the resonant frequency. In some embodiments, resonant load 610 is a plasma chamber used in semiconductor processing and for other purposes. Such a plasma chamber may include, but is not limited to, a chemical vapor deposition chamber, an atomic layer deposition chamber, a capacitive coupled plasma chamber, a plasma etch chamber, a plasma deposition chamber, a plasma enhanced atomic layer deposition chamber, a transformer coupled plasma reactor, or a plasma enhanced chemical vapor deposition chamber as are known in the art. Based upon the disclosed herein, one of ordinary skill in the art will recognize a variety of loads that may be used in place of resonant load 610.

Resonant load 610 is powered by a half bridge inverter circuit 626 that is switched based upon switching signals 623, 625 under control of a switch circuit 602. The switching of switching signals 623, 625 results in switching on a power output 613. Any power switching circuit known in the art may be used in place of half bridge inverter circuit 626. A current transformer 606 is connected to resonant load 610. Current transformer 606 provides a representation of current being transferred to resonant load 610 via an electrical conductor carrying a power output 613. The current being transferred to resonant load 610 exhibits the frequency at which the resonant load is operating, and this same frequency is reflected in a transformer output 619 that is provided to a current zero cross to digital output circuit 608.

A non-resonant inductor 696 is in parallel with resonant load 610, and adds current at zero crossing current of resonant load 610. This added current assists in transitioning the node voltage to the opposite voltage rail under zero voltage switching operations. Added non-resonant inductor 696 allows power switching circuit 600 to maintain zero voltage switching at frequencies higher than that achievable by power switching circuit 100 described above in relation to FIG. 1. Non-resonant inductor 696 is connected between a power output 613 from a switch circuit 602, and between a first capacitor 692 and a second capacitor 694. Capacitor 692 is connected to bus voltage 630, and second capacitor 694 is connected to a ground 615. Both first capacitor 692 and second capacitor 694 are larger than the capacitance (C) of resonant load 610. In some embodiments, first capacitor 692 and second capacitor 694 are of sufficient size such that there is no resonance at the junction of first capacitor 692, second capacitor 694, and non-resonant inductor 696. In some embodiments, the size of first capacitor 692 and second capacitor 694 are chosen such that the voltage at the junction of first capacitor 692, second capacitor 694, and non-resonant inductor 696 is one half of bus voltage 630.

A current zero cross to digital output circuit 608 includes a digital circuit that transforms transformer output 619 to a digital zero crossing output 605. Digital zero crossing output 605 switches between two voltage levels compatible with other downstream digital circuitry. As an example, digital zero crossing output 605 switches between 0 Volts and 3.3 Volts. In some embodiments, current zero cross to digital output circuit 608 is a diode rectifier circuit similar to that shown in FIG. 4 above. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuitry that can be used to convert transformer output 619 to a corresponding digital signal exhibiting the same frequency. Further, based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of voltage levels between which digital zero crossing output 605 can be switched in accordance with different embodiments.

A voltage cross level shift and delay circuit 604 is connected to power output 613, and is a voltage sensing circuit configured to sense each time the voltage of power signal 613 crosses ½ bus volts. Each time the voltage of power output 613 crosses ½ bus volts, voltage cross level shift and delay circuit 604 asserts a zero crossing output 617. Zero crossing output 617 is a digital output that switches between two voltage levels compatible with other downstream digital circuitry. As an example, zero crossing output 617 switches between 0 Volts and 3.3 Volts. In some embodiments, voltage cross level shift and delay circuit 604 is a comparator circuit with an output that switches at a desire digital voltage. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuitry that can be used to detect zero voltage crossings and assert a digital output indicating the occurrence of a zero voltage crossing.

Assertion of zero crossing output 617 corresponds to an edge of power output 613 and is provided to a timing comparison circuit 618. Timing comparison circuit 618 compares voltage zero crossing output 617 with current zero crossing output 605 to yield a phase lead output 601 and a phase lag output 603. Timing comparison circuit 618 asserts lag output 603 with a duty cycle or duration corresponding to the lag of voltage zero crossing output 617 to current zero crossing output 605. As an example, in one embodiment, Timing comparison circuit 618 is implemented as an XOR circuit operable to assert whenever there is a mismatch between voltage zero crossing output 617 to current zero crossing output 605. When the mismatch is due to voltage zero crossing output 617 leading current zero crossing output 605, a lead output 601 is asserted for a period corresponding to the mismatch (i.e., the time period that voltage zero crossing output 617 leads current zero crossing output 605; and when the mismatch is due to voltage zero crossing output 617 lagging current zero crossing output 605, lag output 603 is asserted for a period corresponding to the mismatch (i.e., the time period that voltage zero crossing output 617 lags current zero crossing output 605). Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuitry that can be used to generate lead and lag signals based upon two or more inputs.

A timing reference generator circuit 620 receives lead output 601 and lag output 603. Timing reference generator circuit 620 integrates the asserted one of lead output 601 or lag output 603 and provides a delay reference signal 621 corresponding to the amount of lead/lag between digital zero crossing output 605 and zero crossing output 617. Any integration circuit known in the art that is capable of generating a delay signal may be used as timing offset generator circuit 620.

In this embodiment, delay reference signal 621 is a substantially DC voltage that is increased to delay signal 609 (move the transition of power signal 613 to a later point and reduce the lead), or decreased to reduce the delay signal 609 (move the transition of power signal 613 to an earlier point, and thereby reduce any lag). As more fully described below, this voltage level of delay reference signal 621 is used to define a timing signal 609 that modifies the timing of the power signal provided to drive resonant load 610.

Digital zero crossing output 605 is also provided to a signal ramp generator circuit 616. Signal ramp generator circuit 616 provides a ramp signal 607 that increases in voltage at a defined rate from a start point. The start point is either a rising edge of digital zero crossing output 605 (a positive going zero crossing) or a falling edge of digital zero crossing output 605 (a negative going zero crossing). Ramp signal 607 is provided to a signal ramp comparator circuit 614 that compares ramp signal 607 with delay reference signal 621, and asserts timing signal 609 when ramp signal 607 is the same are greater than delay reference signal 621. Signal ramp comparator circuit 614 may be, but is not limited to, a comparator circuit.

Said another way, lead output 601 and lag output 603 tell timing reference generator circuit 620 when the power output 613 is changing polarity with respect to the current crossing. By delaying voltage zero crossing output 617, timing reference generator circuit 620 is thinking the voltage zero crossing points of power output 613 are too late and will compensate by lowering the voltage on delay reference signal 621 such that it will cause signal ramp generator circuit 614 to assert timing signal 609 earlier in the cycle (i.e., lower on each ramp of ramp signal 607). This is how power switching circuit 600 corrects for the delays (comparators, switch select, switch drive, and transistor delays) of various circuitry. In effect, timing signal 609 is asserted early so that the actual voltage zero crossing occurs consistent with (i.e., on time) that needed by resonant load 610.

Timing signal 609 is provided to a switch select and dead band pulse generator circuit 612. Switch select and dead band pulse generator circuit 612 toggles a gate drive signal 611 and applies a constant dead band delay to gate drive signal 611. The added dead band delay is used to tune for zero volt transitions. Gate drive signal 611 is received by switch circuit 602 where it is used to drive switch signals 623, 625, which switch a bus voltage 630. Each time gate drive signal 611 is pulsed, switch circuit 602 reverses which of drive switch signals 623, 625 is asserted.

A difference in operation of power switching circuit 100 and power switching circuit 600 is discussed in relation to FIGS. 7-9. Turning to FIG. 7, a diagram 700 shows an attempt of power switching circuit 100 to perform zero volt switching at an example two (2) MHz is shown. As mentioned, two (2) MHz is an example and the discussion applies to switching at other relatively low frequencies. As shown, power output 113 switches shortly before the zero crossing of a current 710 of resonant load 110 as indicated by vertical dashed lines 705 (e.g., a dashed line 705a, a dashed line 705b, a dashed line 705c, a dashed line 705d, a dashed line 705e). As shown, the switching of power output 113 is substantially ideal with power switching circuit 100 able to track the frequency of resonant load 110, and at the relatively low frequency of two (2) MHz most of the power is being supplied to resonant load 110 and not reflected back to the power bus of power switching circuit 100.

Turning to FIG. 8, a diagram 800 shows an attempt of power switching circuit 100 to perform zero volt switching at an example 13.5 MHz is shown. As mentioned, 13.5 MHz is an example and the discussion applies to other relatively high frequencies. This is similar to that discussed above, except that the frequency of the resonant load is increased to 13.5 MHz. Again, power output 113 switches shortly before the zero crossing of current 710 of resonant load 110 as indicated by vertical dashed lines 705 (e.g., a dashed line 705a, a dashed line 705b, a dashed line 705c, a dashed line 705d, a dashed line 705e). As shown, the switching is no longer ideal as there is a significant, albeit temporary, reversal of the voltage (shown as a voltage reversal 815a, a voltage reversal 815b, a voltage reversal 815c, a voltage reversal 815d, and a voltage reversal 815d) at power output 113. In particular, current 710 of resonant load 110 reaches zero before the transition of power output 113 has finished. This failure to completely transition before current 710 of resonant load 110 crosses zero results in a short reversal in the voltage of power output 613. This reversal is followed by a steep change in the voltage over a period 816 (e.g., a period 816a, a period 816b, a period 816c, a period 816d, a period 816e) where there is a high current to power output 613 to finish the transition. This high current event results in considerable power loss over the periods 816, and thus a reduction in efficiency of power transfer from power switching circuit 100 to resonant load 110.

In contrast, power switching circuit 600 is capable of efficient power transfer to resonant load 610 at higher frequencies through use of additional current supplied by non-resonant inductor 696. Turning to FIG. 9, a diagram 900 shows an attempt of power switching circuit 600 to perform zero volt switching at the example 13.5 MHz. As shown, at the switching times (indicated by vertical dashed lines 705) for power output 613 non-resonant inductor 696 begins providing additional current 996. Additional current 996 is sufficient to assure that power output 613 has fully transitioned before the current of resonant load 610 reaches zero. As such, the voltage reversals discussed above in relation to FIG. 8 do not occur, and the efficiency of power transfer from power switching circuit 600 to resonant load 610 is increased when compared to the efficiency of power switching circuit 100. Additional current 996 from non-resonant inductor 696 causes transition overshoots 915 (e.g., an overshoot 915a, an overshoot 915b, an overshoot 915c, an overshoot 915d, and an overshoot 915e) which do not undermine the transfer of power to resonant load 610. Additional current 996 is not at the resonant frequency of resonant load 610, but rather is a substantially triangular pattern based upon the voltage level of power output 613. In some embodiments, the size of non-resonant inductor 696 is selected to generate a quantity of additional current 996 to bring the phase of power output 616 in phase with resonant load 610.

FIG. 10 shows a block diagram of another power switching circuit 1000 configured to drive resonant load 610 at an extended upper frequency in accordance with various embodiments. Power switching circuit 1000 includes many of the same elements as power switching circuit 600 described above in relation to FIG. 6, except that switch detect and dead band pulse generator circuit 612 and signal ramp comparator circuit 614 are replaced by a processing resource 620 that executes processing resource instructions from a storage medium 1040 connected to processing resource 1020. Executing the processing resource instructions causes processing resource 1020 to provide gate drive signal 611 based upon ramp signal 607 and delay reference signal 621 similar to that discussed above in relation to FIG. 6. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of other functions of circuit elements of power switching circuit 600 that may be implemented by processing resource, and thus eliminated from the circuit.

FIG. 11 is a flow diagram 1100 showing a method in accordance with some embodiments for providing power to a resonant load at an extended upper frequency. Following flow diagram 1100, an initial impulse input is applied to the resonant load to cause the resonant load to resonate (block 1102). In some embodiments, this initial resonation input that may be, for example, an initial switch transition at levels required by the load that can be repeated for load sensing. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of initial resonation inputs that may be used in relation to particular resonant loads. A power signal is provided to the resonant load (block 1104). The power signal switches from a first voltage level to a second voltage level at a frequency corresponding to a frequency of the resonant load. The power signal includes a load current and a voltage controlled by the resonant load.

Transitioning the power signal from the first voltage level to the second voltage level begins prior to the voltage of the power signal crossing a zero voltage level (block 1106). Additional current is added to the load current when the voltage of the power signal crosses a zero voltage level (block 1108).

In conclusion, the present invention provides for novel systems, devices, and methods. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.

Claims

1. A processing system, the system comprising:

a power switching circuit configured to provide a power signal to a resonant load, wherein the power switching circuit is configured to switch a voltage of the power signal at a frequency of the resonant load, and wherein the power switching circuit begins switching the voltage before each zero voltage crossing of the resonant load; and

a current injector circuit configured to add an additional current to a load current controlled by the resonant load at least at each zero voltage crossing of the resonant load.

2. The system of claim 1, wherein the power switching circuit comprises:

a transition detection circuit configured to detect transitions of the power signal through a level and to provide a corresponding transition output;

a timing detection circuit configured to detect a time offset between an edge of the transition output and an edge of the power signal and provide a corresponding timing correction output;

a signal generation circuit configured to generate a switch input based at least in part on a combination of the timing correction output and the transition output; and

a switching drive circuit configured to change polarity of the power signal based at least in part on the switch input.

3. The system of claim 2, wherein the transition detection circuit includes a transformer configured to transform the power signal to a transformed power signal.

4. The system of claim 3, wherein the transition detection circuit further includes:

a level crossing detection circuit configured to detect a crossing of the transformed power signal through the level, and wherein the transition output is a timing signal indicating each occurrence of the crossing of the power signal through the level.

5. The system of claim 4, wherein a first time period between assertion of a first instance of the transition output and a second instance of the transition output can vary by more than five percent when compared to a second time period between assertion of the second instance of the transition output and a third instance of the transition output, wherein the second instance of the transition output directly follows the first instance of the transition output and the third instance of the transition output directly follows the second instance of the transition output.

6. The system of claim 4, wherein the level is a zero current level, and wherein the level crossing detection circuit is a diode rectifier circuit configured to detect each zero current crossing.

7. The system of claim 2, wherein the timing correction output is a voltage level, and wherein the signal generation circuit includes:

a signal ramp generator circuit configured to generate a ramp signal that ramps from a defined level at a constant rate upon assertion of the transition output;

a signal ramp comparator circuit configured to assert a switch timing output each time the ramp signal is at least the voltage of voltage level of the timing correction output; and

a pulse circuit configured to assert the switch input based at least in part on assertion of the switch timing output.

8. The system of claim 2, wherein the switching drive circuit includes:

a switch circuit configured to switch between a first driver output and a second driver output based upon the switch input; and

a half bridge inverter circuit controlling the power signal based upon the first driver output and the second driver output.

9. The system of claim 8, wherein the current injector circuit includes an inductor connected to the power signal, wherein the inductor provides the additional current to the current of the power signal.

10. The system of claim 9, wherein the current injector circuit further includes:

a first capacitor connected between a first voltage level and a node;

a second capacitor connected between a second voltage level and the node; and

wherein the inductor is connected between the power signal and the node.

11. The system of claim 10, wherein a size of the first capacitor, a size of the second capacitor, and a size of the inductor are all sufficiently large to fix a voltage at the node at a defined level.

12. The system of claim 2, wherein the timing detection circuit includes:

a voltage comparator circuit configured to assert a power signal timing output each time a voltage of the power signal crosses zero volts; and

an edge comparator circuit configured to assert the timing correction output at a voltage level corresponding to a difference in an edge of the power signal and the edge of the transition output.

13. The system of claim 10, wherein the voltage level is:

decreased when the edge of the transition output leads the edge of the power signal, and increased when the edge of the transition output lags the edge of the power signal.

14. The system of claim 1, the system further comprising:

the resonant load.

15. The system of claim 1, wherein a frequency of the load varies by more than ten percent.

16. A method for providing power to a load, the method comprising:

applying an initial impulse input to a resonant load to cause the resonant load to resonate;

providing a power signal to the resonant load, wherein the power signal switches from a first voltage level to a second voltage level at a frequency corresponding to a frequency of the resonant load, and wherein the power signal includes a load current and a voltage controlled by the resonant load;

beginning a transition of the power signal from the first voltage level to the second voltage level prior to the voltage of the power signal crossing a zero voltage level; and

injecting an additional current, wherein the additional current is added to the load current when the voltage of the power signal crosses a zero voltage level.

17. The method of claim 16, wherein the additional current is injected only when the voltage of the power signal crossing a zero voltage level.

18. The method of claim 16, wherein injecting the additional current is done by a current injector circuit, wherein the current injector circuit is connected to the power signal, and wherein the inductor provides the additional current to the current of the power signal.

19. The method of claim 18, wherein the current injector circuit further includes:

a first capacitor connected between a first voltage level and a node;

a second capacitor connected between a second voltage level and the node; and

wherein the inductor is connected between the power signal and the node.

20. The method of claim 19, wherein a size of the first capacitor, a size of the second capacitor, and a size of the inductor are all sufficiently large to fix a voltage at the node at a defined level.