Level meter circuit

A level meter circuit for displaying the level of an input signal by the use of a number of light emitting diodes. The circuit has a parallel circuit of a plurality of unit circuits each having a diode circuit and a current control transistor connected in series with the parallel circuit and controlled by the input signal, the level of which is to be displayed. In accordance with the input signal level to be displayed, one or more of the diodes are activated to emit light, thus providing a display of the input signal level.

Skip to: Description  ·  Claims  ·  References Cited  · Patent History  ·  Patent History
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a level meter circuit for displaying the level of an input signal by the use of a number of light emitting diodes.

2. Description of the Prior Art

Therefore there have been proposed various level meter circuits of the type displaying the input level through utilization of a large number of light emitting diodes. One of such conventional level meter circuits has a number of comparators respectively corresponding to the light emitting diodes and a number of reference signal sources respectively corresponding to the comparators. The light emitting diodes are each driven by one of the comparators corresponding thereto. The comparators each compare the output from one of the reference signal sources corresponding thereto and the input signal the level of which is to be displayed. The level of the input signal is displayed by lighting those of the light emitting diodes which correspond in number to the input signal level.

As noted above such a prior art level meter circuit calls for comparators and reference signal sources of the same number as the light emitting diodes used, and hence it has the defects of bulkiness, complexity and expensiveness.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a novel level meter circuit which is free from the abovesaid defects of the prior art.

According to the present invention, the level meter circuit is provided with a parallel circuit of a plurality of unit circuits and current control means, such as a transistor, which is connected in series with the parallel circuit and controlled by the input signal the level of which is to be displayed. The unit circuits each has a diode circuit, which is composed of a plurality of series-connected diodes and current bypass resistors, each connected in parallel with one of the diodes. The unit circuits except one of them are each provided with current detecting means, such as a resistor, which is connected in series with the diode circuit. Further, the unit circuits except another one of them are each provided with current control means, such as a transistor, which is connected in series with the diode circuit and controlled by the current detecting means. In accordance with the input signal level to be displayed, one or more of the diodes are activated to emit light, thus providing a display of the input signal level.

Accordingly, the level meter circuit of the present invention is able to display the input signal level with a simple circuit arrangement and does not require the utilization of numbers of comparators and reference signal sources such as have been employed in the aforementioned conventional level meter circuit. Therefore, the level meter circuit of the present invention has the advantages of small and simple structure and low manufacturing cost.

Other objects, features and advantages of the present invention will become more fully apparent from the following detailed description taken in conjunction with the accompanying drawing.

BRIEF DESCRIPTION OF THE DRAWING

The accompanying drawing is a connection diagram illustrating an embodiment of the level meter circuit of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The illustrated embodiment of the level meter circuit has a parallel circuit 1 of a parallel connection of P unit circuits M.sub.1 to M.sub.P and a main current control circuit 2 connected in series with the parallel circuit 1. The following description will be given on the assumption that P is an odd number for the sake of simplicity. The one end of the series circuit on the side of the parallel circuit 1 is connected to a positive terminal 4 of a power source 3 and the other end on the side of the main current control circuit 2 is connected via the ground to a negative terminal 5 of the power source 3.

The main current control circuit 2 is supplied, via output terminals 7 and 8 of an input signal source 6, with an input signal S the level of which is to be displayed. The main current control circuit 2 is controlled by the input signal S so that a current I.sub.S flowing via the circuit 2 from the power source 3 to the parallel circuit 1 may assume a value (which is identified by the same reference character I.sub.S as the current I.sub.S for the sake of brevity) corresponding to the level (which is identified by V.sub.S). Such a current control circuit 2 may be a known one.

An example of the current control circuit 2 has an NPN type current control transistor 9 of relatively high output impedance. The transistor 9 has its collector connected to one end of the parallel circuit 1 and has it emitter grounded via a resistor 10 and consequently it is connected in series with the parallel circuit 1 via a resistor 10. The input signal source 6 is connected at the one end 7 to the base of the transistor 9 and grounded at the other end 8. The transistor 9 is controlled by the input signal S so that the current I.sub.S flowing therethrough to the parallel circuit 1 may take the value I.sub.S corresponding to the level V.sub.S of the input signal S.

The unit circuit M.sub.i (i=1, 2, . . . P) has a diode circuit G.sub.i.

The unit circuits M.sub.1 to M.sub.(P-1) except the circuit M.sub.P respectively have current detecting circuits F.sub.1 to F.sub.(P-1) which are connected in series with the diode circuits G.sub.1 to G.sub.(P-1), respectively. The current detecting circuits F.sub.1, F.sub.3, F.sub.5, . . . F.sub.(P-2) are respectively connected in series with the diode circuits G.sub.1, G.sub.3, G.sub.5, . . . G.sub.(P-2) on the opposite side from the main current control circuit 2 and the current detecting circuits F.sub.2, F.sub.4, F.sub.6, . . . F.sub.(P-1) are respectively connected in series with the diode circuits G.sub.2, G.sub.4, G.sub.6, . . . G.sub.(P-1) on the side of the main current control circuit 2.

The unit circuits M.sub.2 to M.sub.P, other than that M.sub.1, respectively have current control circuits H.sub.2 to H.sub.P which are connected in series with the diode circuits G.sub.2 to G.sub.P, respectively. The current control circuits H.sub.2, H.sub.4 . . . H.sub.(P-1) are respectively connected in series with the diode circuits G.sub.2, G.sub.4, G.sub.6, . . . G.sub.(P-1) on the opposite side from the main current control circuit 2. The current control circuits H.sub.3, H.sub.5, H.sub.7, . . . H.sub.P are respectively connected in series with the diode circuits G.sub.3, G.sub.5, G.sub.7, . . . G.sub.P on the side of the main current control circuit 2.

The unit circuit M.sub.i has a light emitting diode D.sub.i0 connected in series with the diode circuit G.sub.i. The diode D.sub.10 is connected in series with the diode circuit G.sub.1 on the side of the main current control circuit 2 and the diodes D.sub.30, D.sub.50, D.sub.70, . . . D.sub.P0 are respectively connected in series with the diode circuits G.sub.3, G.sub.5, G.sub.7, . . . G.sub.P on the side of the main current control circuit 2. The diodes D.sub.20, D.sub.40, D.sub.60, D.sub.(P-1)0 are respectively connected in series with the diode circuits G.sub.2, G.sub.4, G.sub.6, . . . G.sub.(P-1) on the opposite from the main current control circuit 2. In this case, the diodes D.sub.10, D.sub.30, D.sub.50, . . . D.sub.P0 have their cathodes on the side of the main current control circuit 2 and the diodes D.sub.20, D.sub.40, D.sub.60, . . . D.sub.(P-1)0 have their anodes on the side of the power source 3.

Accordingly, in the unit circuit M.sub.1 there are connected in series the current detecting circuit F.sub.1, the diode circuit G.sub.1 and the diode D.sub.10 are connected in this order from the side opposite from the main current control circuit 2. Therefore, the current I.sub.1 flows from the power source 3, to the current detecting circuit F.sub.1, the diode circuit G.sub.1 and the diode D.sub.10 as a current which is provided via the unit circuit M.sub.1 to the main current circuit 2. In the unit circuits M.sub.1 to M.sub.(P-1), there are respectively connected in series the the diodes D.sub.10 to D.sub.(P-1)0, the current control circuits H.sub.1 to H.sub.(P-1), the diode circuits G.sub.1 to G.sub.(P-1) and the current detecting circuits F.sub.1 to F.sub.(P-1) in this order from the side opposite from the main current control circuit 2. Therefore, the currents I.sub.1 to I.sub.(P-1) respectively flow from the power source 3 to the diodes D.sub.10 to D.sub.(P-1)0, the current control circuits H.sub.1 to H.sub.(P-1), the diode circuits G.sub.1 to G.sub.(P-1) and the current detecting circuits F.sub.1 to F.sub.(P-1) as currents which are respectively provided via the unit circuits M.sub.1 to M.sub.(P-1) to the main current control circuit 2. In the unit circuit M.sub.p there are connected in series the diode circuit G.sub.P, the current control circuit H.sub.p and the diode D.sub.P0 in this order from the side opposite from the main current control circuit 2. Therefore, the current I.sub.P flows from the power source 3 to the diode circuit G.sub.P, the current control circuit H.sub.P and the diode D.sub.P0 as a current which is provided via the unit circuit M.sub.P to the main current control circuit 2. The current detecting circuits F.sub.1 to F.sub.(P-1) of the unit control circuits M.sub.1 to M.sub.(P-1) detect the value of the currents I.sub.1 to I.sub.(P-1) (which values are respectively identified by the same I.sub.K to I.sub.(P-1) as the current I.sub.1 to I.sub.(P-1) for the sake of simplicity) and respectively provide the detected outputs as control signals B.sub.1 to B.sub.(P-1).

The current control circuits H.sub.2 to H.sub.P of the unit circuits M.sub.2 to M.sub.P are respectively controlled by the control signals B.sub.1 to B.sub.(P-1) from the current detecting circuits F.sub.1 to F.sub.(P-1).

Assume that the level V.sub.S of the input signal S from the input signal source 6 assumes values V.sub.S0, V.sub.S1, V.sub.S2, . . . V.sub.SP. Let it be assumed in this case, that the levels V.sub.S0, V.sub.S1, V.sub.S2, . . . V.sub.SP bear the following relationships:

V.sub.S0 (=0)<V.sub.S1 <V.sub.S2 < . . . <V.sub.S(p-1) <V.sub.SP . . . (1)

.vertline.V.sub.S0 -V.sub.S1 .vertline..congruent..vertline.V.sub.S1 -V.sub.S2 .vertline..congruent. . . . .congruent..vertline.V.sub.S(P-1) -V.sub.SP .vertline..congruent.V.sub.a . . . (2)

Let I.sub.S0, I.sub.S1, I.sub.S2, . . . I.sub.SP represents the levels of the current I.sub.S which flows in the parallel circuit 1 and the current control circuit 2 when the input signal S assumes the levels V.sub.S0, V.sub.S1, V.sub.S2, . . . V.sub.SP, respectively. Assume, in this case, that the levels I.sub.S0, I.sub.S1, I.sub.S2, . . . I.sub.SP bear the following relationships:

I.sub.S0 (=0)<I.sub.S1 <I.sub.S2 < . . . I.sub.S(P-1) <I.sub.SP . . . (3)

I.sub.S0 -I.sub.S1 .vertline..congruent..vertline.I.sub.S1 -I.sub.S2 .vertline..congruent. . . . .vertline.I.sub.S(P-1) -I.sub.SP .vertline..congruent.I.sub.a . . . (4)

Since the unit circuit M.sub.1 has no current control circuit if the level V.sub.S of the input signal S is varied analogously from V.sub.S0 to V.sub.SP, the level of the current I.sub.S undergoes an analogous change from I.sub.S0 (=0) to I.sub.SP.

In the case where the current I.sub.S varies analogously from the level I.sub.SO (=0) to I.sub.S1, the current I.sub.1 flowing in the unit circuit M.sub.1 undergoes an analogous change from the level I.sub.S0 (=0) to I.sub.S1. In this case, however, the current control circuit H.sub.2 of the unit circuit M.sub.2 is not controlled to be operative by the control signal B.sub.1 from the current detecting circuit F.sub.1 of the unit circuit M.sub.1, so that the current I.sub.2 flowing in the unit circuit M.sub.2 remains at the zero level. Therefore, the currents I.sub.3 to I.sub.p of the other unit circuits M.sub.3 to M.sub.p also remain at the zero level. That is, in this case, only the current I.sub.1 of the unit circuit M.sub.1 varies from the level I.sub.S0 to I.sub.S1, while the currents I.sub.2 to I.sub.p of the unit circuits M.sub.2 to M.sub.p remain at the zero level.

When the current I.sub.S varies analogously from the level I.sub.S1 to I.sub.S2, the current I.sub.1 of the unit circuit M.sub.1 is saturated at a level .vertline.I.sub.SO -I.sub.S1 .vertline.=I.sub.a. The control circuit H.sub.2 of the unit circuit M.sub.2 is controlled to be operative by the control signal B.sub.1 which is fed from the current detecting circuit F.sub.1 of the unit circuit M.sub.1 in this case. The current control circuit H.sub.2 produces a great change in the level of the current I.sub.2 in response to a very slight change in the level of the control signal B.sub.1. In consequence, the current I.sub.2 of the unit circuit M.sub.2 varies analogously from the level I.sub.S0 to I.sub.S1. In this case, however, the current control circuit H.sub.3 of the unit circuit M.sub.3 is not controlled to be operative by the control signal B.sub.2 which is derived from the current detecting circuit F.sub.2 in this case, so that the current I.sub.3 of the unit circuit M.sub.3 remains at the zero level. Accordingly, the currents I.sub.4 to I.sub.p of the unit circuits M.sub.4 to M.sub.P are also held at the zero level. As a result of this, the current I.sub.1 of the unit circuit M.sub.1 is saturated substantially at the level I.sub.a and the current I.sub.2 of the unit circuit M.sub.2 undergoes an analogous change from the level I.sub.S0 to I.sub.S1 and the currents I.sub.3 to I.sub.P of the unit circuits M.sub.3 to M.sub.P are retained at the zero level.

In the case where the current I.sub.S changes from the level I.sub.S2 to I.sub.S3, the currents I.sub.1 and I.sub.2 of the unit circuits M.sub.1 and M.sub.2 are saturated substantially at the level I.sub.a. The current control circuits H.sub.3 of the unit circuit M.sub.3 is controlled to be operative by the control signal B.sub.2 from the current detecting circuit F.sub.2 of the unit circuit M.sub.2, causing the current I.sub.3 of the unit circuit M.sub.3 to change analogously from the level I.sub.S0 to I.sub.S1. In this case, however, the current control circuit H.sub.4 of the unit circuit M.sub.4 is not controlled to be operative by the control signal B.sub.3 from the current detecting circuit F.sub.3, so that the current I.sub.4 of the unit circuit M.sub.4 remains at the zero level. Accordingly, the currents I.sub.5 to I.sub.p of the other unit circuits M.sub.5 to M.sub.P also remain at the zero level. As a result of this, the currents I.sub.1 and I.sub.2 of the unit circuits M.sub.1 and M.sub.2 are saturated substantially at the level I.sub.a and the current I.sub.3 of the unit circuit M.sub.3 varies from the level I.sub.S0 to I.sub.S1 and the currents I.sub.4 to I.sub.p of the unit circuits M.sub.4 to M.sub.P are held at the zero level.

In the case where the current I.sub.S similarly undergo analogous changes from the levels I.sub.S3 to I.sub.S4, I.sub.S4 to I.sub.S5 . . . I.sub.S(P-2) to I.sub.S(P-1), the currents I.sub.1 to I.sub.3, I.sub.1 to I.sub.4, . . . I.sub.1 to I.sub.(P-2) of the unit circuits M.sub.1 to M.sub.3, M.sub.1 to M.sub.4 . . . M.sub.1 to M.sub.(P-2) saturated substantially at the level I.sub.a and the currents I.sub.4, I.sub.5 . . . I.sub.(p-1) of the unit circuits M.sub.4, M.sub.5 . . . M.sub.(P-1) vary from the level I.sub.S0 to I.sub.S1 and the currents I.sub.5, I.sub.6 . . . I.sub.(P-1) of the unit circuits M.sub.5, M.sub.6 . . . M.sub.(P-1) remain at the zero level.

In the case where the current I.sub.S varies analogously from the level I.sub.S5 to I.sub.S6, the currents I.sub.1 to I.sub.(P-1) of the unit circuits M.sub.1 to M.sub.(P-1) are saturated substantially at the level I.sub.a and the current I.sub.P of the unit circuit M.sub.P varies from the level I.sub.S0 to I.sub.S1 .

Further, even if the current I.sub.S varies in excess of the level I.sub.SP, the currents I.sub.1 to I.sub.p of the unit circuits M.sub.1 to M.sub.P are saturated substantially at the level I.sub.a.

Specific example of the current detecting circuits F.sub.1 to F.sub.(P-1) of the unit circuits M.sub.1 to M.sub.(P-1) are respectively constituted by resistors R.sub.10 to R.sub.(P-1)0 which are connected in series with the diode circuits G.sub.1 to G.sub.(P-1) of the unit circuits M.sub.1 to M.sub.(P-1), respectively. The current control circuits H.sub.2 H.sub.4, H.sub.6, H.sub.(P-1) have, for example, PNP type current control transistors Q.sub.2, Q.sub.4, Q.sub.6, . . . Q.sub.(P-1) of relatively high output impedance, which respectively have their collectors connected to the diode circuits G.sub.2, G.sub.4, G.sub.6, . . . G.sub.(P-)1 at one end thereof, their emitters connected to the cathodes of the diodes D.sub.20, D.sub.40, D.sub.60, . . . D.sub.(P-1)0 and their bases connected to the resistors R.sub.10, R.sub.30, R.sub.50, . . . R.sub.(P-2)0 of the current detecting circuits F.sub.1, F.sub.3, F.sub.5, . . . F.sub.(P-2) on the side of the diode circuits G.sub.1, G.sub.3, G.sub.5, . . . G.sub.(P-2). The current control circuits H.sub.3, H.sub.5, H.sub.7, . . . H.sub.P have, for example, NPN type current control transistors Q.sub.3, Q.sub.5, Q.sub.7, . . . Q.sub.P of relatively high output impedance, which respectively have their collectors connected to the diode circuits G.sub.3, G.sub.5, G.sub.7, . . . G.sub.P at one end thereof, their emitters connected to the anodes of the diodes D.sub.30, D.sub.50, D.sub.70, . . . D.sub.P0 and their bases connected to the resistors R.sub.20, R.sub.40, R.sub.60, . . . R.sub.(P-1)0 of the current detecting circuits F.sub.2, F.sub.4, F.sub.6, . . . F.sub.(P-1) on the side of the diode circuits G.sub.2, G.sub.4, G.sub.6, . . . G.sub.(P-1). Accordingly, the transistors Q.sub.2 to Q.sub.P are respectively connected in series with the diode circuit G.sub.k and respectively controlled by the voltage drops across the resistors R.sub.10 to R.sub.(P-1)0 of the current detecting circuit F.sub.(k-1). In practice, the resistance values r.sub.10, r.sub.20, . . . r.sub.(P-1)0 of the resistors R.sub.10, R.sub.20, . . . R.sub.(P-1)0 bear the following relationships:

r.sub.10 .congruent.r.sub.20 .congruent. . . . .congruent.r.sub.(P-1)0 . . . (5)

The transistors Q.sub.2, Q.sub.4, . . . Q.sub.(P-1) have the same characteristic and the transistors Q.sub.3, Q.sub.5, . . . Q.sub.p also have the same characteristic.

The diode circuit G.sub.i are provided with plural, N.sub.i, series-connected light emitting diodes D.sub.il`, D.sub.i2, . . . D.sub.iN.sbsb.i and current bypassing resistors R.sub.i1, R.sub.i2, . . . R.sub.iN.sbsb.i connected in parallel with the diodes D.sub.i1, D.sub.i2, . . . D.sub.iN.sbsb.i, respectively. In this case, the resistance values r.sub.i1, r.sub.i2, . . . r.sub.iN.sbsb.i are suitably selected in such a range that they bear the following relationships:

r.sub.i1 <r.sub.i2 < . . . r.sub.iN.sbsb.(i-1) <r.sub.iN.sbsb.i . . . (6)

In practice, the numbers N.sub.1, N.sub.2, . . . N.sub.P are equal to the diodes D.sub.11 to D.sub.1N, D.sub.21 to D.sub.2N.sbsb.2 . . . D.sub.P1 to D.sub.PN.sbsb.P have the same characteristic as the aforesaid diodes D.sub.10 to D.sub.P0. Further, there are the following relationships:

r.sub.11 .congruent.r.sub.21 .congruent. . . . .congruent.r.sub.P1 (7)

r.sub.12 .congruent.r.sub.22 .congruent. . . . .congruent.r.sub.P2

r.sub.13 .congruent.r.sub.23 .congruent. . . . .congruent.r.sub.P3 (7)

In the foregoing, it is described that in the case where the current I.sub.S flowing through the parallel circuit 1 changes analogously from level I.sub.SO (=0) to the level I.sub.S1 as the level V.sub.S of the input signal S varies analogously from V.sub.S0 (=0) to V.sub.S1, the current I.sub.1 of the unit circuit M.sub.1 changes from the level I.sub.S0 to I.sub.S1 but the currents I.sub.2 to I.sub.P of the unit circuits M.sub.2 to M.sub.P remain at the zero level. Consider the case where the input signal S assumes (N.sub.1 +2) levels V.sub.D0 (=I.sub.S0), V.sub.D1, V.sub.D2, . . . V.sub.DN.sbsb.1, V.sub.D(N.sbsb.1.sub.+1) (=V.sub.S1) when the input signal level V.sub.S varies from V.sub.S0 to V.sub.S1. In th is case, let it be assumed that the levels bear the following relationships:

V.sub.D0 (V.sub.S0 =0)<V.sub.D1 < . . . <V.sub.DN.sbsb.1 <V.sub.D (N.sbsb.1.sub.+1) (=V.sub.S1) . . . (8)

.vertline.V.sub.D0 -V.sub.D1 .vertline..congruent..vertline.V.sub.D1 -V.sub.D2 .vertline..congruent. . . . .congruent..vertline.V.sub.D(N.sbsb.1.sub.-1) -V.sub.DN.sbsb.1 .vertline..congruent..vertline.V.sub.DN.sbsb.1 -V.sub.D(N+1) .vertline..congruent.V.sub.b . . . (9)

Let I.sub.D0 (=I.sub.S0 =0), I.sub.D1, I.sub.D2, . . . I.sub.DN.sbsb.1, I.sub.D(N.sbsb.1.sub.+1) (=I.sub.S1) represent the levels of the current I.sub.S when the level V.sub.S of the input signal S assumes the values V.sub.D0, V.sub.D1, . . . V.sub.DN.sbsb.1, V.sub.D(N.sbsb.1.sub.+1) respectively. In this case, the levels of the current I.sub.S bear such relationships as follows:

I.sub.D0 (=I.sub.SO)<I.sub.D1 <I.sub.D2 <. . . <I.sub.DN.sbsb.1 <I.sub.D(N.sbsb.1.sub.+1) (=I.sub.S1) . . . (10)

but let it be assumed that they bear the following relationships:

.vertline.I.sub.D0 -I.sub.D1 .vertline..congruent..vertline.I.sub.D1 -I.sub.D2 .vertline..congruent. . . . .congruent..vertline.I.sub.D(N.sbsb.1.sub.-1) -I.sub.DN.sbsb.1 .vertline..congruent.I.sub.b . . . (11)

When the current I.sub.S undergoes an anlogous change from the level I.sub.DO (=I.sub.SO =0) to the level I.sub.D1, the current I.sub.1 of the unit circuit M.sub.1 varies analogously from the level I.sub.DO (=I.sub.SO =0) to the level I.sub.D1. A current flowing in the diode D.sub.10 of the unit circuit M.sub.1 has the same level as does the current I.sub.1 flowing in the unit circuit M.sub.1. The currents flowing in the diodes D.sub.11, D.sub.12, . . . D.sub.1N.sbsb.1 have lower levels than the current I.sub.1. The currents flowing in the diodes D.sub.11, D.sub.12, . . . D.sub.1N.sbsb.1 become greater in this order. The reason for which such relationship is obtained is that the current bypassing resistors R.sub.11, R.sub.12, . . . R.sub.1N.sbsb.1 having the relationships expressed by the equation (6). When the level of the current I.sub.1 becomes I.sub.D1, the diode D.sub.10 is turned ON or lighted but the other diodes D.sub.11 to D.sub.1N.sbsb.1 remain unlighted. In the case where the level of the current I.sub.S changes analogously from I.sub.D1 to I.sub.D2, the current I.sub.1 also undergoes an analogous change from the level I.sub.D1 to I.sub.D2. In this while the diode D.sub.10 is supplied with a current which varies analogously from the level I.sub.D1 to ID.sub.2 but since the level of this current is higher than the level I.sub.D1, the diode D.sub.10 remains lighted. When the level of the current I.sub.1 becomes I.sub.D2, the diode D.sub.11 is lighted but the other diodees D.sub.12 to D.sub.1N.sbsb.1 remain unlighted. In the case where the current I.sub.S varies analogously from the level I.sub.D2 to I.sub.D3, the current I.sub.1 also varies analogously from the level I.sub.D2 to I.sub.D3. In this while the diodes D.sub.10 and D.sub.11 remain lighted. When the level of the current I.sub.1 becomes I.sub.D3, the diode D.sub.12 is lighted but the other diodes D.sub.13 to D.sub.1N.sbsb.1 are not lighted. Similarly, when the level of the current I.sub.S varies analogously from the levels I.sub.D3 to I.sub.D4, I.sub.D4 to I.sub.D5 . . . I.sub.D(N.sbsb.1.sub.-1) to I.sub.DN.sbsb.1, the current I.sub.1 also varies analogously from the levels I.sub.D3 to I.sub.D4, I.sub.D4 to I.sub.D5 . . . I.sub.D(N.sbsb.1.sub.-1) to I.sub.DN.sbsb.1. In this while the diodes D.sub.12, D.sub.13 . . . D.sub.1(N.sbsb.1.sub.-2) keep on lighting. When the level of the current I.sub.1 becomes I.sub.d4, I.sub.D5 . . . I.sub.DN.sbsb.1, the diodes D.sub.13, D.sub.14 . . . D.sub.1 (N-1) are lighted but the other diodes D.sub.14 to D.sub.1N.sbsb.1, D.sub.15 to D.sub.1N.sbsb.1 . . . D.sub.1N.sbsb.1 remain unlighted. When the level of the current I.sub.1 becomes I.sub.D(N.sbsb.1.sub.+1) (=I.sub.S1), all the diodes D.sub.10 to D.sub.1N.sbsb.1 are lighted.

Consequently, the diodes D.sub.10, D.sub.11, D.sub.12, D.sub.13, . . . D.sub.1N.sbsb.1 of the unit circuit M.sub.1 are sequentially lighted as the level V.sub.S of the input signal S varies analogously from V.sub.S0 to V.sub.S1.

In the above it is described that in the case where the current I.sub.S varies analogously from the level I.sub.S1 to I.sub.S2 as the level V.sub.S of the input signal S from V.sub.S1 to V.sub.S2, the current I.sub.1 is saturated substantially at the level I.sub.1 and the current I.sub.2 of the unit circuit M.sub.2 varies analogously from the level I.sub.S0 to I.sub.S1 and the currents I.sub.3 to I.sub.P of the unit circuits M.sub.3 to M.sub.P remain at the zero level. While the current I.sub.2 of the unit circuit M.sub.2 varies analogously from the level I.sub.S0 to I.sub.S1, all the diodes D.sub.10 to D.sub.1N.sbsb.1 of the unit circuit M.sub.1 keep on lighting. When the current I.sub.2 changes analogously from the level I.sub.S0 to I.sub.S1, the diodes D.sub.20, D.sub.21, D.sub.22, . . . D.sub.2N.sbsb.2 of the unit circuit M.sub.2 are lighted in this order. The reason is as follows: The diodes D.sub.20, D.sub.21, D.sub.22, . . . respectively correspond to the diodes D.sub.10, D.sub.11, D.sub.12, . . . of the unit circuit M.sub.1 ; the resistors R.sub.21, R.sub.22, R.sub.23, . . . respectively correspond to the resistors R.sub.11, R.sub.12, R.sub. 13 . . . of the unit circuit M.sub.1 ; and the analogous variation of the current I.sub.2 of the unit circuit M.sub.2 from the level I.sub.S0 to I.sub.S1 corresponds to the analogous variation of the current I.sub.1 of the unit circuit M.sub.1 from the level I.sub.S0 to I.sub.S1 in the case where the current I.sub.S varies analogously from the level I.sub.S0 to I.sub.S1.

Accordingly, when the level V.sub.S of the input signal S varies analogously from V.sub.S1 to V.sub.S2, the diodes D.sub.20, D.sub.21, D.sub.22, . . . D.sub.2N.sbsb.2 of the unit circuit M.sub.2 are sequentially lighted in this order, with all the diodes D.sub.10 to D.sub.1N.sbsb.1 of the unit circuit M.sub.1 being lighted.

Similarly, when the level V.sub.S of the input signal S varies analogously from V.sub.S3 to V.sub.S4, V.sub.S4 to V.sub.S5 . . . V.sub.S(P-1) to V.sub.SP, the diodes D.sub.30 to D.sub.3N.sbsb.3, D.sub.40 to D.sub.4N.sbsb.4 . . . D.sub.PO to D.sub.PN.sbsb.p of the unit circuits M.sub.3, M.sub.4 . . . M.sub.p are sequentially lighted respectively, with all the diodes (D.sub.10 to D.sub.1N.sbsb.1) to (D.sub.20 to D.sub.2N.sbsb.2), (D.sub.10 to D.sub.1N.sbsb.1) to (D.sub.30 to D.sub.3N.sbsb.3), . . . (D.sub.10 to D.sub.1N.sbsb.1) to (D.sub.(P-1)0 to D.sub.(P-1)N.sbsb.(P-1) of the unit circuits M.sub.1 to M.sub.2, M.sub.1 to M.sub.3, . . . M.sub.1 to M.sub.(P-1) being lighted. When the level V.sub.S of the input signal S exceeds V.sub.SP, all the diodes (D.sub.10 to D.sub.1N.sbsb.1) to (D.sub.P0 to D.sub.PN.sbsb.P) of all the unit circuits M.sub.1 to M.sub.P are lighted.

Therefore, when the level V.sub.S of the input signal S varies analogously from V.sub.S0 (=0) to V.sub.SP or more, the diodes D.sub.10, D.sub.11, D.sub.12, . . . D.sub.1N.sbsb.1, D.sub.20, D.sub.21, D.sub.22, . . . D.sub.2N.sbsb.2, D.sub.30, D.sub.31, . . . D.sub.(P-1)N.sbsb.(P-1), D.sub.P0, D.sub.P1, . . . D.sub.PN.sbsb.P are sequentially lighted in this order. And if the level V.sub.S of the input signal S further varies analogously from V.sub.SP or more to V.sub.S0, the diodes D.sub.PN.sbsb.P, D.sub.PN.sbsb.(P-1), . . . D.sub.P0, D.sub.(P-1)N.sbsb.P-1, D.sub.(P-1)(N.sbsb.p-1.sub.-1), . . . D.sub.(P-1)0, D.sub.(P-2)N.sbsb.(P-2), . . . D.sub.2N.sbsb.2, D.sub.2 (N.sub.1 -1) . . . D.sub.20, D.sub.1N.sbsb.1, D.sub.1(N.sbsb.1.sub.-1), . . . D.sub.11, D.sub. 10 are sequentially turned OFF in this order.

Accordingly, by arranging the diodes D.sub.10, D.sub.11, D.sub.12 , . . D.sub.1N.sbsb.1, D.sub.20, D.sub.21, D.sub.22, . . . D.sub.2N.sbsb.2, D.sub.30, D.sub.31, D.sub.32, . . . D.sub.(P-1)N.sbsb.(P-1) D.sub.P0, D.sub.P1, D.sub.P2 . . . D.sub.PN.sbsb.P in this order, the diodes of the number counted from the beginning of their arrangement corresponding to the level V.sub.S of the input signal S are turned displaying the level V.sub.S of the input signal S.

As has been described in the foregoing, the illustrated level meter circuit of the present invention is provided with the parallel connection circuit 1 of the unit circuits M.sub.1 to M.sub.P and the main current control circuit 2 which is connected in series with the parallel circuit 1 and controlled by the input signal S. The unit circuit M.sub.i has the diode circuit G.sub.i provided with the light emitting diodes D.sub.il to D.sub.iN.sbsb.i and the current bypassing resistors R.sub.il to R.sub.iN.sbsb.i respectively connected in parallel with the diodes D.sub.il to D.sub.iN.sbsb.i and a light emitting diode D.sub.i0 connected in series with the diode circuit G.sub.i ; the unit circuits M.sub.1 to M.sub.(P-1) have respectively the current detecting circuits F.sub.1 to F.sub.(p-1) which are connected in series with the diode circuits G.sub.1 to G.sub.(p-1), respectively; and the unit circuits M.sub.2 to M.sub.P have the current control circuits H.sub.2 to H.sub.P which are connected in series with the diode circuits G.sub.2 to G.sub.p, respectively and controlled by the current detecting circuits F to F.sub.(p-1), respectively. According to the present invention, it is possible to display the level of the input signal S with such a simple circuit arrangement. Accordingly, the level meter circuit of the present invention can be made small, simple and inexpensive. Further, by increasing the number P of the unit circuits M.sub.1 to M.sub.P without increasing the number N.sub.i of the diodes D.sub.il to D.sub.iN.sbsb.i in the diode circuit G.sub.i of the unit circuit M.sub.i, the level of the input signal S can be displayed over a wider range. This means that the diodes are all lighted at the same brightness. Accordingly, there can be produced a visually beautiful display of the level of the input signal S.

The foregoing embodiment should be construed as being merely illustrative of the present invention. For example, in the illustrated arrangement of the level meter circuit of the present invention, the diodes D.sub.20 to D.sub.P0 of the unit circuits M.sub.2 to M.sub.P can be omitted. Also it is possible to leave out the diode D.sub.10 in the unit circuit M.sub.1.

In the foregoing it has been described that as the current I.sub.S flowing in the parallel circuit 1 sequentially increases by the same amount of level, the currents I.sub.2, I.sub.3, . . . I.sub.P respectively flow in the unit circuits M.sub.2, M.sub.3, . . . M.sub.P in a sequential order, and that the currents I.sub.1, I.sub.2, . . . I.sub.P flowing in the unit circuits M.sub.1, M.sub.2, . . . M.sub.P assume the same saturation level. It is also possible, however, that by suitably arranging the current detecting circuits F.sub.1 to F.sub.(P-1) and the current control circuits H.sub.2 to H.sub.P, as the current I.sub.S sequentially increases by an amount of level different from that of the immediately previous current increase, the currents I.sub.2, I.sub.3, . . . I.sub.P respectively flow in the unit circuits M.sub.2, M.sub.3, . . . M.sub.P in a sequential order, and that the currents I.sub.1 , I.sub.2, . . . I.sub.P assume different saturation levels. Further, it has been described in the foregoing that each time the current I.sub.i sequentially increases by the same amount of level, the diodes D.sub.i0, D.sub.i1, . . . D.sub.iN.sbsb.i in the unit circuit M.sub.i are each lighted in a sequential order by suitably selecting the values r.sub.i1 to r.sub.iN.sbsb.1 of the the resistors R.sub.i1 to R.sub.iN.sbsb.1 within the range that satisfies the equation (6). It is also possible, however, that each time the current I.sub.i increases by an amount of level different from that of the immediately previous current increase, the abovesaid diodes are each lighted in a sequential order.

It will be apparent that many modifications and variations may be effected without departing from the scope of the novel concepts of this invention.

Claims

1. A level meter circuit comprising:

a parallel circuit of P unit circuits M.sub.1, M.sub.2,... M.sub.p; and
main current control means connected in series with the parallel circuit and controlled by an input signal the level of which is to be displayed;
wherein the unit circuit M.sub.i (i=1, 2,... P) has a diode circuit G.sub.i, the diode ciruit G.sub.i having N.sub.i series-connected light emitting diodes D.sub.i1, D.sub.i2,... D.sub.iN.sbsb.i and current bypassing resistors R.sub.i1, R.sub.i2,... R.sub.iN.sbsb.i respectively connected in parallel with the light emitting diodes D.sub.i1, D.sub.i2,... D.sub.iN.sbsb.i, and the current bypassing resistors R.sub.i1, R.sub.i2,... R.sub.iN.sbsb.i having smaller resistance values in this order;
wherein the unit circuits M.sub.1 to M.sub.(P-1) respectively have current detecting circuits F.sub.1 to F.sub.(P-1) which are connected in series with the diode circuits G.sub.1 to G.sub.(P-1), respectively; and
wherein the unit circuits M.sub.2 to M.sub.P respectively have current control circuits M.sub.2 to M.sub.P which are connected in series with the diode circuits G.sub.2 to G.sub.P respectively and controlled by the current detecting circuits F.sub.1 to F.sub.(P-1) respectively.

2. A level meter circuit according to claim 1 wherein the unit circuit M.sub.1 has a light emitting diode D.sub.10 connected in series with the diode circuit G.sub.1.

3. A level meter circuit according to claim 1 wherein the main current control means has a current control transistor connected in series with the parallel circuit.

4. A level meter circuit according to claim 1 wherein the unit circuits M.sub.2 to M.sub.P respectively have light emitting diodes D.sub.20 to D.sub.P0 which are connected in series with the diode circuits G.sub.2 to G.sub.P, respectively.

5. A level meter circuit according to claim 1 wherein the current detecting circuits F.sub.1 to F.sub.(P-1) respectively have current detecting resistors R.sub.10 to R.sub.(P-1)0 which are connected in series with the diode circuits G.sub.1 to G.sub.(P-1), respectively.

6. A level meter circuit according to claim 1 wherein the current control circuits H.sub.2 to H.sub.P have current control transistors Q.sub.2 to Q.sub.P which are connected in series with the diodes circuits G.sub.2 to G.sub.P, respectively.

Referenced Cited
U.S. Patent Documents
3818495 June 1974 Sagara et al.
4004220 January 18, 1977 Kerber et al.
4065716 December 27, 1977 O'Brien
4096435 June 20, 1978 Sabe
4166245 August 28, 1979 Roberts
4241342 December 23, 1980 Merriweather
Patent History
Patent number: 4480221
Type: Grant
Filed: Aug 12, 1981
Date of Patent: Oct 30, 1984
Assignee: Trio Kabushkik Kaisha (Tokyo)
Inventor: Kazuo Shozima (Tokyo)
Primary Examiner: Stewart J. Levy
Attorneys: Gerald J. Ferguson, Jr., Joseph J. Baker
Application Number: 6/292,221
Classifications
Current U.S. Class: Using Radiant Energy (324/96); Voltage (340/660)
International Classification: G01R 3100;