Apparatus for generating high power, low energy pulses across the terminals of a large capacity, low impedance battery

Abstract

A signal, in the form of high power, low energy pulses that are generated on cables that are connected directly to the terminals of a low impedance battery, are transmitted between a memory device located on the battery and a data recorder located at the charger end of the battery charging cables. Information transfer between the battery memory device and a charger is done through the battery cables, eliminating the need for special connections. The high power, low energy pulses imposed on the battery cables may be detected at each end of the cables, in spite of the low impedance nature of large lead acid batteries. Pulses are created across the terminals of the battery using a fast acting switch (preferably a FET), a capacitor, and a current limiting resistor connected in series across the cables. When the switch is closed in response to an external command, high power, low energy pulses imposed at one end of the cables are detected at the other end of the cables.

Description

BACKGROUND OF THE INVENTION

This invention relates to a memory and communications device carried on a storage battery for storing and transferring battery identification codes and other data associated with the battery and the vehicle on which the battery is used.

Storage batteries used with battery powered vehicles are typically removed from the vehicle and charged at regular intervals. The storage batteries are multicell units that have an attached pair of cables terminated in a standard connector. The storage batteries are usually removed after a shift of eight hours or less, charged for a period of time, and then allowed to cool for another period of time before being used again. The vehicle may be used continuously, but only after a replacement battery has been installed. Thus, all vehicles and all batteries usually use the same industry standard connector.

Battery data recorders have been installed on storage batteries to maintain a record of charging parameters, such as a battery identification number, the number of times the battery has been charged, the temperature of the battery during each charge, the amount of time the battery has been charged, and other relevant battery charging information. Such prior art battery data recorders are typically installed directly on the battery, and draw their power from the battery itself, but have a non-volatile memory in the event they are disconnected. The information contained in the data recorder is typically downloaded from time to time by connecting a data receiver, or computer, to the data recorder. A special interface cable is used to connect the data recorder to the computer.

In other systems, the charger itself is monitored for the battery charging information. In these systems, however, the battery number is manually recorded each time the battery is connected to the charger.

Clearly, there is a need for a battery monitoring system where battery charging information can be ascertained automatically. Further, there is a need for a system that does not require any special connections to the battery to download any of the stored data.

SUMMARY OF THE INVENTION

In the present invention, a memory device is connected to a storage battery to store the battery identification code and other data associated with the battery, such as charging information. Further, the memory device may be used to record information relating to and sent from the vehicle on which it was used. Information transfer between the battery memory device and the charger, or the vehicle, is done through the battery cables, and therefore no special connections are required.

Information transfer through the battery cables requires the use of special techniques due to the low impedance characteristics of the battery and the inductance of the battery cables. It has been found that even at 500 kHz, an AC sine wave imposed on the battery terminals was attenuated by 99% of its original amplitude. It was discovered, however, that a high power, low energy pulse imposed on the battery leads at one end could be detected at the other end. Accordingly, this invention utilizes this characteristic of the battery in the transfer of information.

Accordingly, it is an object of this invention to provide a method of transmitting data on a pair of cables having a low impedance battery load on one end thereof, the method including the steps of transmitting a data pulse formed from a plurality of short duration pulses whereby each short duration pulse is created by momentarily imposing a high power, low energy pulse at one end of the cables, sensing a change in voltage at the other end of the cables to detect the occurrence of each short duration pulse, applying each detected short duration pulse to a resettable multivibrator having a output pulse width slightly greater than the interval between said short duration pulses, and determining whether the output of the multivibrator is continuous during a predetermined period to indicate the reception of a valid data pulse.

It is a further object of this invention to provide a method of creating high power, low energy pulses by momentarily short circuiting the cables at one end thereof.

It is another object of this invention to provide an interface circuit for use in connection with a battery identification device associated with a battery, said circuit comprising a pair of battery cables connected to a battery, means for generating a plurality of high power, low energy pulses for each data pulse representing a logic "1", and means for converting information stored in said battery identification device into data pulses.

It is still a further object of this invention to provide an apparatus for generating high power, low energy pulses across the terminals of a large capacity battery comprising a fast acting switch, a capacitor, and a current limiting resistor, wherein said switch, capacitor and resistor are connected in series across the terminals of the battery to impose a momentary short circuit at the battery's terminals when said switch is closed.

Other objects and advantages of the invention will be apparent from the following description, the accompanying drawings and the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified perspective view showing the basic components of the invention;

FIG. 2 is a simplified block diagram of a communications module;

FIG. 3 is an electrical schematic of a pulse transmitter;

FIG. 4 is a waveform diagram showing the shape of an output pulse applied to a transmitter filter circuit;

FIG. 5 is a waveform diagram showing the shape of an output pulse on the terminals of a battery;

FIG. 6 is an electrical schematic of alternate embodiment of a pulse transmitter;

FIG. 7 is an electrical schematic of a pulse receiver;

FIG. 8 is a waveform diagram showing the shape of a pulse generated by a circuit similar to FIG. 3 as received;

FIG. 9 is a waveform diagram showing the shape of a pulse after intermediate processing by the circuit of FIG. 7;

FIG. 10 is a waveform diagram showing the output pulse after complete processing by the circuit of FIG. 7;

FIG. 11 is a waveform diagram showing in detail the component pulses and space making up one complete data pulse from the circuit of FIG. 7;

FIG. 12 is a waveform diagram showing critical timing events in the data pulse represented in FIG. 11;

FIG. 13 is a representation of a complete set of data pulses for reading and writing to an EEPROM location;

FIG. 14 is a representation of a complete set of data pulses for reading and writing to a RAM location;

FIGS. 15A-15J together comprise a computer flow chart of a communications routine called BIDCOMM; FIG. 15K is diagram showing how the drawings of FIG. 15 should be arranged;

FIGS. 16A-16D together comprise a computer flow chart of the BIDCOMM communications routine when the command sent is hex .0..0.; FIG. 16E is diagram showing how the drawings of FIG. 16 should be arranged;

FIGS. 17A-17D together comprise a computer flow chart of the BIDCOMM communications routine when the command sent is hex .0.1; FIG. 17E is diagram showing how the drawings of FIG. 17 should be arranged;

FIGS. 18A-18C together comprise a computer flow chart of the BIDCOMM communications routine when the command sent is hex .0.2; FIG. 18D is diagram showing how the drawings of FIG. 18 should be arranged;

FIGS. 19A-19D together comprise a computer flow chart of the BIDCOMM communications routine when the command sent is hex .0.3; FIG. 19E is diagram showing how the drawings of FIG. 19 should be arranged;

FIGS. 20A-20D together comprise a computer flow chart of a communications routine called SPULSE; FIG. 20E is diagram showing how the drawings of FIG. 20 should be arranged;

FIGS. 21A-21D together comprise a computer flow chart of a communications routine called DPULSE; FIG. 21E is diagram showing how the drawings of FIG. 21 should be arranged;

FIGS. 22 is computer flow chart of a communications routine called PULSE0;

FIGS. 23A and 23B together comprise a computer flow chart of a communications routine called PULSE1;

FIGS. 24A and 24B together comprise a computer flow chart of a communications routine called J1;

FIGS. 25A-25E together comprise a computer flow chart of how the communications from an expansion board on the battery charger is received and processed; FIG. 25F is diagram showing how the drawings of FIG. 25 should be arranged;

FIGS. 26A-26C together comprise a computer flow chart of the overall computer program from the battery charger side of the communications path; FIG. 26D is diagram showing how the drawings of FIG. 26 should be arranged;

FIGS. 27A-27D together comprise a computer flow chart of a communications subroutine called RBIDEE; FIG. 27E is diagram showing how the drawings of FIG. 27 should be arranged;

FIGS. 28A-28D together comprise a computer flow chart of a communications subroutine called WBIDEE; FIG. 28E is diagram showing how the drawings of FIG. 28 should be arranged;

FIGS. 29A-29D together comprise a computer flow chart of a communications subroutine called RBIDRAM; FIG. 29E is diagram showing how the drawings of FIG. 29 should be arranged;

FIGS. 30A-30D together comprise a computer flow chart of a communications subroutine called WBIDRAM; FIG. 30E is diagram showing how the drawings of FIG. 30 should be arranged;

FIGS. 31A-31K together comprise a computer flow chart of a communications subroutine called BIDW; FIG. 31L is diagram showing how the drawings of FIG. 31 should be arranged;

FIGS. 32A-32D together comprise a computer flow chart of a set of communications subroutines called VOLTAGE, ERRORCH, DBIT and STARTB; FIG. 32E is diagram showing how the drawings of FIG. 32 should be arranged;

FIGS. 33A-33D together comprise a computer flow chart of a communications subroutine called READ; FIG. 33E is diagram showing how the drawings of FIG. 33 should be arranged.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to the drawings which illustrate the preferred embodiment of the invention, and particularly to FIG. 1, a battery 10 is shown connected to a battery charger 15. The battery size may range from six to thirty-six cells. A set of cables 20 is attached to the battery and a second set of cables 25 is attached to the charger. The cables are connected together by industry standard connectors 30. The length of the cables is typically ten feet, but cable lengths of up to forty feet may be used.

A battery identification device (BID) or communications module 40 is attached to the battery 10. Module 40 contains a variety of information concerning the battery, such as its identification number, the present and maximum temperatures to which the battery has been subjected, the present and minimum battery voltage, and calibration information. Other information, such a information relating to vehicle may also be stored in the module. The information contained in the module 40 is conveyed to an expansion board 45 preferably contained in the battery charger 15.

A computer 50 is connected to the battery charger expansion board 45 by a cable 55 to control operation of the system. The cable 55 is also connected to other battery chargers within the facility, and each is polled from time to time.

In the present invention, the transfer of information between the module 40 and the expansion board 45 uses the existing cables sets 20 and 25; no other wires are needed for this purpose. The cable set 20 is connected directly to the battery 10, and since the battery is typically a high capacity lead-acid battery capable of providing several hundred amperes of current over an eight hour shift to power a vehicle, special techniques are required to impose a usable data signal on the cable set.

In FIG. 2, the communications module 40 is shown in block diagram form and includes connections 60 and 62 to the battery cable set 20. A connection 64 is also made to one of the cells of the battery, preferably the sixth cell, for providing operating current to the module itself through a voltage regulator 66.

The module includes a microprocessor 70 which may contain an internal temporary memory or random access memory (RAM) 72, and a device for storing the microprocessor's instruction set or program or programmable read only memory (PROM) 74. The RAM 72 will hold data only so long as the device is connected to the battery.

A non-volatile memory or EEPROM 76 is also connected to the microprocessor for storing certain data, such as an identification number and calibration data, which information will be retained even if the module is removed from the battery. The typical life of information stored in an EEPROM is approximately ten years.

Voltage sensor 78 and temperature sensor 79 provide data to the microprocessor, which will be stored in the RAM 72. A pulse transmitter 80 is connected to the microprocessor 70 to send data as a series of pulses over the cable set when instructed by the microprocessor, and a pulse receiver 100 senses the pulses on the cable set from the expansion board and for applying appropriately modified signals to the microprocessor.

FIG. 3 is an electrical schematic diagram of a preferred embodiment of the pulse transmitter 80. It is simply a fast acting switch in the form of a FET device 82 having it input 84 connected to the microprocessor 70, and a resistor-capacitor circuit 86 connected to the cable set 20. Upon receipt of a pulse from the microprocessor, the FET will produce an output at 88, which is illustrated in FIG. 4. The pulse will provide 10 microseconds (10 .mu.s) of a complete short circuit to the input of the FET, but the resultant pulse at 89 will have the shape generally shown in FIG. 5 at the terminals of a cable set, due to the impedance characteristics of the battery and the circuit 86.

The circuit 86 is a series circuit including a capacitor C1 and a pair of resistors R1 and R2 connected to the FET 82. When the FET conducts, an effective short circuit is momentarily created by the capacitor C1. The value of this capacitor is chosen to be large enough to insure that the voltage at the battery's terminals will be brought down to its minimum voltage (as a result of the battery's impedance), but not so large that its effectiveness is exceeded and power is wasted. Resistor R3 is a bleeder provided to discharge the capacitor C1 after the FET opens. Resistor R4 insures the FET remains in a non-conducting state absent a switching pulse on its input.

An alternative pulse transmitter 90 is illustrated in FIG. 6 where, rather than short circuiting the terminals of the battery, a higher voltage is imposed on the cable set. This may be done by first charging capacitors C2 and C3 in parallel, and then moving switch 92 to its second position to put the capacitors in series, thus imposing a short duration pulse of higher voltage on the output terminals.

FIG. 7 is an electrical schematic diagram of pulse receiver 100. The receiver is connected to the cable set where it senses pulses having the general waveform shown in FIG. 8. This signal is applied to the circuit 102 which contains a pair of operational amplifiers OP1 and OP2 which form a pulse shaping circuit. All resistor values shown in FIG. 7 are 1% tolerance. FIG. 9 shows a typical output of the circuit at 104 in response to an input signal in the form of FIG. 8. Typically, an individual short duration pulse 110 will have a 10 .mu.s width, followed by an 100 .mu.s space.

The output of circuit 102 is applied to a resettable one-shot multivibrator 106. The multivibrator has a timed output slightly greater than the interval between pulses such that if the pulses are received in sequence, the output remains high, and therefore, if a group of individual short duration pulses is properly received, the output on line 108 of the multivibrator at 106 will take the form shown in FIG. 10 having a pulse 115 of 1.1 ms duration, followed by a 5.6 ms space.

Both the pulse transmitter of FIG. 3 and the pulse receiver of FIG. 7 are used in both the battery module 40 and the expansion board 45.

FIG. 11 shows a typical single data pulse, representing a "1", comprising a plurality of individual short duration pulses 110, each of 10.mu.s duration, followed by a 100 .mu.s space. After a burst of individual short duration pulses, there is a period 112 of approximately 5.6 ms duration where no pulse should be received. The total duration of a data pulse is therefore about 6.7 ms, but it may be made longer or shorter if necessary to facilitate timing factors within the microprocessor 70 or in the expansion board.

FIG. 12 is a waveform diagram showing critical timing events of a typical the data pulse. After the beginning of the data pulse 115 at 120, there is a first period 121 (300 .mu.s) where no measurement is made, followed by a second period 122 (700 .mu.s) where the pulse is tested to determine whether any change in status has occurred. A third period 123 (900 .mu.s) is provided, again where the signal is not sensed, and a fourth period 124 (approximately 4500 .mu.s) where the signal is sensed to determine whether any pulse is detected. Finally, a fifth period 125 (300 .mu.s) where no measurement is made.

The first, third and fifth periods are not tested because they are considered transition periods where the signal level could be either high or low, or transitioning between levels. Within the second and fourth periods 122 and 124, the level must not change; otherwise, an error in the detection of the signal is assumed.

Within the battery module 40, there are two types of memories employed. The EEPROM 76 holds information that is not expected to change, except at long intervals. For example, the EEPROM contains the battery identification number, and this number would not change while the module is attached to the battery, but it would be provided with a new number when the module is relocated on a new battery. It also contains calibration information used primarily to calibrate the analog to digital converters used by the voltage and temperature sensors 78 and 79. This data would not normally change unless recalibration became necessary. This data can be changed from the computer 50.

The RAM 72 holds data while connected to a voltage source, which would normally be the case while the module is associated with a particular battery.

The EEPROM read and write commands are represented by FIG. 13. The RAM read and write commands are represented by FIG. 14. Both of these commands are sent from the expansion boards to the battery module, and include four parts: a four bit start byte 130, 134, a two bit command (CMD) code 131, 135 to indicate whether a read or a write command is being sent, an address 132, 136, and a data field 133, 137. For the EEPROM, the data field 133 is sixteen data bits and for the RAM, the data field 137 is eight bits.

The start byte is a set of four logic "1"s to indicate the beginning of each command. The command field (CMD) is a two bit command pulse where .0..0. hex instructs the module's microprocessor that data from the given address in the EEPROM is to be read; .0.1 hex means that data from the given address in the EEPROM is to be written; .0.2 means that data at the given address in the RAM is to be read; and .0.3 hex means that data at the given address in the RAM is to be written.

The microprocessor 70 contains a program in the PROM 74 which responds to the read and write commands shown in FIGS. 13 and 14, and also an internal program that reads the voltage and temperature data to RAM 72 at regular intervals.

The communications link between the battery module 40 and the expansion board 45 is initiated at the battery charger side of the link. A pulse transmitter similar to the one shown in FIG. 3 is generated under control of a microprocessor contained in the expansion board to impose a high power, low energy pulse at the output terminals on the charger and across the charge cables and connector to the battery 10. Due to inductance in the cables 20 and 25 and the battery 10 itself, the signal at the other end of the signal path is significantly attenuated. The higher cell sizes produce the strongest signals.

The receiver circuit in the module 40 turns this pulse into a digital pulse which can be read by the module's microprocessor. Note that it takes ten pulses to create the waveform 115 shown FIGS. 10 and 12. If any of the ten pulses is missing, that pulse would be broken up and rejected as an invalid pulse by the microcontroller.

Data to be written to the BID module 40 is always sent twice for verification. If the expansion board 45 is reading the BID module 40 it always reads the same location in secession for verification.

The expansion board 45 (referred to as EXP) general flowchart (FIG. 26) provides an overall picture of the structure of the expansion board side of a communication system. A communication link is initiated by the software contained in expansion board whenever a battery is first connected to the charger, or periodically after the charging operation is complete, or whenever requested by computer 50.

First, four start pulses are sent to the module 40, indicating that a communication event is beginning. The next two data bits sent are command bits which indicate what the module is to do (read or write data). The following six pulses specify the address of the module's memory to be used. At this point the EXP program decodes the CMD code 131, 135 (FIGS. 13 and 14).

If CMD is .0..0. hex, the expansion board will expect sixteen pulses to be sent back from the module's EEPROM memory. If the CMD code is .0.1 hex, the expansion board program will send sixteen bits of data to the module's EEPROM memory, that data specified in main program loop. If the CMD code is .0.2 hex, it means that the module will be sending eight bits of data back from its RAM, and if the CMD code is .0.3 hex, the module should expect eight bits of data to be sent from the expansion board to the RAM 72.

FIGS. 27 to 30 describe how the communications works from a MAIN loop of the program. Any of the following four subroutines may be called at any particular point in the expansion board program, provided that the proper data had been previously set up (data to be sent, address). Note that these routines are executed prior to or after battery charging operation.

The first subroutine is RBIDEE, shown in FIG. 27, which reads sixteen bits from module's EEPROM. Prior to calling this program, the EEPROM address to read was loaded into a register ADDR. A counter is set so that the dialogue with the BID module may be repeated up to 25 times. This amount of redundancy is required because of the usually noisy environment in which these system operate.

Once all the parameters are checked and set, routine BIDW (FIG. 31) is called. This is where the actual pulses are transmitted to and received from the BID module. The sixteen bits of data from the module must be received error free twice for the data to be accepted. Of course, the data must match twice also. If the data has been accepted, error free, it is checked to see if it is .0..0.. This value would represent a value completely outside the expected range of values, and therefore represents an obvious error, even though the data has been read twice.

Since .0..0. is not an acceptable answer, the counter is decremented and the loop is started again. If the counter hits .0..0. (meaning a valid data was never obtained), the answer is cleared. A delay at the end of the subroutine insures the code will be in synchronism with module's code the next time a communication is required.

The second subroutine is RBIDRAM, shown in FIG. 28, and it reads eight bits from the BID module's RAM. Prior to calling this program, the RAM (BID RAM) address to read was loaded into the register ADDR. A counter is set for 25 counts, this means the dialogue with the BID module could happen up to 25 times. Next, the register CMD is loaded with .0.2 (HEX) this is the command for reading BIDRAM. Once all the parameters are checked and set, routine BIDW (FIG. 31) is called, as previously described.

The third subroutine is the WBIDRAM routine, shown in FIG. 29. It's purpose is to write eight bits of data from the EXP to the BID module's RAM. In this routine, the counter is set for 50 tries. The CMD register is loaded to HEX .0.3. Two 10 mS delays are called for to insure synchronization with the BID module. Now, subroutine BIDW (FIG. 31) is called twice in a row. This sends the same data two times in a row to insure the module reads it correctly. If not sent twice, the module will reject all data sent.

The EXP reads the same BID RAM address it just wrote to (via the BIDW routine, FIG. 31)). If no errors (reading data back) occurred, DATA1X (the answer from module) is compared to DATA2X (the original data sent), and if they are the same, the routine ends with the normal resynchronizing delay.

The fourth subroutine, shown in FIG. 30, is the WBIDEE routine. It's purpose is to write sixteen bits of data from the EXP to the BID module's EEPROM. In this routine the counter is set for 25 tries. The CMD register is loaded to HEX .0.1. Two 10 mS delays are now called for to insure synchronization with the BID module. Subroutine BIDW (FIG. 31) is called twice in a row. This sends the same data two times in a row to insure the module reads it correctly. If not sent twice the module will reject all data sent. Now the EXP reads the same BID EEPROM address (after 74 mS delay for writing to EEPROM) it just wrote to (via BIDW FIG. 31). If no errors (reading data back) occurred DATA1X and DATA2X (the answer from module) is compared to TMP43 and TMP21 respectively (they hold the original data sent), if they are the same, the routine ends with the normal resynchronizing delay.

The BIDW routine shown in FIG. 31. This routine calls the subroutines that send a pulse out or read a pulse in (READ, DBIT). The four start bytes are sent to the BID module to let it know a communication is starting. The next two data bits sent are command bits which indicate which transaction will take place. The following six data bits indicate to the module which address in its memory it needs to access. Depending on the CMD code, the subroutine will now either send data or read data.

If the CMD code sent to the module was .0..0., the routine will wait for the module to read its EEPROM, then read each pulse of data sent back one at a time. If the CMD code sent to the module was hex .0.1, the routine sends sixteen bits of data to the module one at a time. The CMD's .0.2 and .0.3 hex work basically the same as CMD's .0..0. and .0.1 but only transfer eight bits of data to or from the module. Both of the read portions (CMD .0..0. and .0.1) of this routine have the ability to detect errors (flags produced by read subroutine) occurring while reading the incoming pulse. If any occur, the data is scrapped.

FIG. 32 shows the VOLTAGE, ERRORCH, DBIT, STARTB subroutines, and FIG. 33 shows the READ subroutine.

The VOLTAGE subroutine simply checks for the presence of battery connected to the charger. It is used in the four write and read BID subroutines because it would be useless to try to communicate to a BID module if a battery were not connected.

The ERRORCH routine checks for a flag bit after returning from the READ subroutine. If this flag is set, the communication timing is resynchronized by staying in this loop until the bit counter register is equal to .0..0.. The counter register is decremented in the timer interrupt every 8.19 mS. The bit counter is set for the number of bits expected from the module.

The DBIT subroutine interrogates the data bit that is about to be sent to the BID and produces a "1" (turn BID FET on) or "0" (FET stays off) accordingly. STARTB always produces a "1" output.

The READ routine looks at the incoming data bit, determines its value ("1" or "0") and stores the bit in the proper place. If unexpected data is read during the pulse, an error flag is set.

The battery identification (BID) module flowcharts will now be examined. The flow chart of FIG. 25 shows in general terms how the communications from the EXP board is received and processed. The BID module's communications network input port is constantly being polled by the program. When the input reads a "1", the polling stops and the receive section of code starts. The four start bits are received followed by the two CMD bits. Next, 6 address bits are read to specify where data is to be written or read. This routine interprets the CMD register and decides what to do next.

If the CMD is .0..0., it reads the EEPROM and sends back sixteen bits of data to the EXP board, from the address specified. If the CMD was .0.1, the routine expects to receive sixteen bits of data from the EXP to be stored in EEPROM. A .0.2 and .0.3 hex in the CMD work very similar to CMD's .0..0. and .0.1 hex except they only deal with eight data bits because they are writing or reading RAM. If at any point an error is detected reading data from the EXP, the process is aborted.

Flowcharts BIDCOMM (FIG. 15), BIDCOMM1 (FIGS. 16-19), and BIDCOMM2 (FIGS. 20-24) will give more details on the communications loop and subroutines.

When a communication is started, SPULSE is called four times in a row. Four start bits are sent from the EXP, SPULSE checks each one to see if bit was received properly (each start bit = "1"). Each time a bit is received properly a register called check is decremented, this is how the number of bits read correctly is counted. If there were an error at some point, this register (with its remaining counts) is used for resynchronization (each count in check x 1 bits time).

The next eight bits are read by subroutine DPULSE. DPULSE reads and records each bit. The first two bits are the CMD and the next 6 are the address (address is where data from EXP is written to or read from). Each time the code returns from DPULSE the bit read is stored in its proper register CMD or ADDR (if no errors occurred). Now the CMD code is decoded to see what function the module is to do (write or read).

The BIDCOMM1 flowcharts (FIGS. 16-19) describes the action taken on each one of the four possible commands sent. Referring to FIG. 16, if the CMD is .0..0., then the EEPROM is first read. Then each of the sixteen bits (one EEPROM location is sixteen bits wide) is sent back to the EXP board, one at a time. If the bit to be sent is "0" then subroutine PULSE0 is used, PULSE1 if the bit is a "1".

Referring to FIG. 17, if the CMD is .0.1, then sixteen bits of data are expected from the EXP board. The writing process starts by examining the address specified. If it is OE or OF (hex) the RAM register SECURE must contain the proper value; if it does not, the process is aborted. Now all sixteen bits are received from the EXP at one time. The program now beings polling again.

For purposes of verification the very same CMD, address and sixteen bits of data are resent (within 1 second) from the EXP (sent as soon as resynchronizing delays take place). The BID module must read the data exactly the same. If the data is not sent twice or does not agree (1st and 2nd try) the EEPROM will not be written to. The other CMD's (.0.2 hex, FIG. 18, and .0.3 hex, FIG. 19) work basically the same, only eight bits are read or written from BID RAM.

BIDCOMM2 flowchart describes the SPULSE (FIG. 20), DPULSE (FIG. 21), PULSE0 (FIG. 22), PULSE1 (FIG. 23) and J1 (FIG. 24) loop routines.

SPULSE (FIG. 20) is the routine that is used to receive start pulses from the EXP board. It makes sure that "1" is received and rejects the communication if it sees a "0" for data. DPULSE works the same as SPULSE except that either a "1" or "0" can be read.

The DPULSE routine of FIG. 21 is used when data other than START BYTE data is expected from the EXP. The PULSE0 and PULSE1 routines of FIGS. 22 and 23, respectively are called when data is to be sent back to the EXP. PULSE0 is actually a delay representing A "0" (the EXP input will read a "0"). PULSE1 actually turns on the BID transmit circuit, creating a "1" for data at the EXP input.

In FIG. 24, the J1 loop's purpose is to reset the code to be ready for another communication. This loop does a delay equal to 1 data pulse for every count left in register check. This causes the two sets of software (EXP and BID module) to be resynchronized. If this were not done, the EXP could try to write to the BID when it was not ready. This is useful when an error occurred in a transmission, the BID code would just ignore the rest of the data bits, while staying in synchronism with the EXP.

Thus, using by using the existing cables between the battery and the charger, information from a module on the battery itself can be transferred to an expansion board in the charger. No additional wires or radio communications equipment are required. The specific information transferred can be related to the battery itself, or to the vehicle on which the battery has been used. That information can then be processed by the computer 50 for management purposes.

While the form of apparatus herein described constitutes a preferred embodiment of this invention, it is to be understood that the invention is not limited to this precise form of apparatus and that changes may be made therein without departing from the scope of the invention, which is defined in the appended claims.

Claims

1. An apparatus for generating high power, low energy pulses across the terminals of a large capacity battery, said apparatus comprising

a fast acting switch,

a capacitor, and

a current limiting resistor, and

a switch actuator for causing said switch to close under external control,

wherein said switch, capacitor and resistor are connected in series across the terminals of the battery to impose a momentary short circuit at the battery's terminals to cause a high power, low energy pulse to be generated each time said switch is closed, which pulse may be detected on cables connected directly to the battery terminals.

2. The apparatus of claim 1 wherein said fast acting switch is an FET.

3. The apparatus of claim 1 further including a bleeder resistor connected in parallel with said capacitor.

4. The apparatus of claim 1 further including means for generating a predetermined plurality of spaced apart pulses to create a data pulse representing a logic "1".

5. The apparatus of claim 1 further including a pair of cables for connecting the battery to a charger, and means for sensing each high power, low energy pulse at the charger end of said cables.

6. The apparatus of claim 1 wherein the battery is a lead acid battery.