Capacitor element, method for manufacturing the same, and electro-optic device
A capacitor element includes a lower conductive portion, an underlying film which covers the lower conductive portion, a lower electrode formed on the underling film, a capacitor insulating film including (i) a dielectric film formed on the lower electrode and (ii) a protective film formed on the dielectric film and having a lower etching rate than that of the dielectric film, and an upper electrode formed on the capacitor insulating film. The upper electrode and the lower conductive portion are electrically connected to each other through a connection portion exposed from the underlying film by partially removing the underlying film and the capacitor insulating film.
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1. Technical Field
The present invention relates to the technical field of, for example, a capacitor element, a method for manufacturing the same, and an electro-optic device such as a liquid crystal device, which includes the capacitor element as a holding capacitor.
2. Related Art
In a liquid crystal device which is an example of this sort of electro-optic device, a holding capacitor is provided corresponding to each pixel portion so that an image signal supplied to a pixel electrode is temporarily held. Such a holding capacitor includes a pair of capacitor electrodes and a dielectric film formed between the capacitor electrodes. The pair of capacitor electrodes is electrically connected to wiring provided in a layer different from a layer in which the holding capacitors are formed on a substrate, and constitutes a portion of a circuit portion on the substrate. Japanese Unexamined Patent Application Publication No. 2008-058578 discloses a technique in which for enhancing the efficiency of a process for manufacturing a liquid crystal device, a step of forming contact holes for electrically connecting different layers on a substrate is omitted.
When among the pair of capacitor electrodes, an upper electrode formed above a lower electrode is electrically connected to wiring formed below the holding capacitor, a dielectric film interposed between a pair of electrodes is patterned to a predetermined shape using, for example, an acid etching solution or the like.
However, when a dielectric film is etched with an acid etching solution, the dielectric film is easily etched, and thus it is difficult to pattern the dielectric film into a predetermined shape. For example, when a dielectric film of alumina or the like is formed for increasing the capacitance value of a holding capacitor, the dielectric film of alumina may be formed at a low temperature, and the dielectric film of good quality, which has low leakage current, is formed. However, the dielectric film is easily etched with an acid etching solution. Therefore, even when the dielectric film is formed using a dielectric material which can improve electric characteristics of the dielectric film, there occurs the problem that patterning is difficult by a process for forming holding capacitors.
Such a problem may occur in not only a holding capacitor provided for each pixel portion of a liquid crystal device and a capacitor element in which an upper electrode, which is one of a pair of capacitor electrodes, is electrically connected to a conductive portion provided below the capacitor element.
SUMMARYAn advantage of some aspects of the invention is that the invention provides a capacitor element including a dielectric film which is patterned into a predetermined shape without being excessively etched, a method for manufacturing the same, and an electro-optic device including the capacitor element as a holding capacitor.
According to an embodiment of the present invention, a capacitor element includes a lower conductive portion provided on a substrate, an underlying film which covers the lower conductive portion, a lower electrode formed on the underling film, a capacitor insulating film including (i) a dielectric film formed on the lower electrode and (ii) a protective film formed on the dielectric film and having a lower etching rate than that of the dielectric film, and an upper electrode formed on the capacitor insulating film. The upper electrode and the lower conductive portion are electrically connected to each other through a connection portion exposed from the underlying film by partially removing the underlying film and the capacitor insulating film.
In the capacitor element of the present invention, the lower conductive portion such as a wiring layer is formed on the substrate, and the underlying film such as an insulating film or the like is formed on the lower conductive portion. The lower electrode includes a semiconductor layer of polysilicon or the like, or a metal film, and extends on the underlying film so as to overlap the lower conductive portion.
The capacitor insulating film includes the dielectric film including an alumina layer or the like and formed on the lower electrode and the protective film formed on the dielectric film and composed of a hafnium (Hf)-based material having a lower etching rate than that of the dielectric film. The hafnium (Hf)-based material represents a material containing hafnium, for example, an oxide such as hafnium oxide having a high dielectric constant of about 4 times that of alumina. Such a protective film has a low etching rate for an acid etching solution relative to the dielectric film of alumina or the like. In other words, the material has high resistance to the etching solution and protects the dielectric film so that the dielectric film is not excessively etched when being patterned into a predetermined shape in a process for forming the capacitor element.
The upper electrode is formed on the capacitor insulating film, includes a conductive film of a larger size than the lower electrode, and is formed using, for example, the same conductive material as the lower electrode.
The upper electrode and the lower conductive portion are electrically connected to each other through a connection portion exposed from the underlying film by partially removing the capacitor insulating film. As described above, the capacitor insulating film includes the dielectric film having a high dielectric constant and the protective film having a lower etching rate than that of the dielectric film. Therefore, when the capacitor insulating film is patterned by etching, the dielectric film is patterned into a predetermined shape without being excessively etched. Therefore, the connection portion may be exposed from the underlying film by partially removing the capacitor insulating film so that the dielectric film is patterned into a predetermined shape. The upper electrode and the lower conductive portion are electrically connected to each other, and thus the capacitor element and the lower conductive portion are electrically connected to each other. In addition, in the capacitor element of the present invention, even when the dielectric film is formed using a dielectric material having low resistance to an etching solution, the capacitance value of the capacitor element may be set to a high value.
The capacitor element according to an embodiment of the present invention may further include an interlayer insulating film formed between the capacitor insulating film and the lower electrode outside a region occupied by a layered structure formed by laminating in order the lower electrode, the capacitor insulating film, and the upper electrode.
In this configuration, when the capacitor insulating film is patterned by etching, the lower electrode is protected by the interlayer insulating film so as not to be etched. The layered structure represents an element portion substantially functioning as a capacitor in the capacitor element. Therefore, even if the interlayer insulating film is formed as a portion other than the portion substantially functioning as a capacitor, the electric characteristic of the capacitor element, i.e., the capacitance value, is not decreased.
According to an embodiment of the present invention, a method for manufacturing a capacitor element includes forming a lower electrode on an underling film formed on a lower conductive portion provided on a substrate so as to overlap the lower conductive portion, forming a dielectric film on the lower electrode and then forming a protective film having a lower etching rate than that of the dielectric film on the dielectric film, etching the dielectric film from the protective film so that the dielectric film is patterned to a predetermined planar shape to remove a portion of the dielectric film, which does not overlap the protective film, and forming an upper electrode on the protective film. The upper electrode is formed to overlap a connection portion exposed from the underlying film so that the upper electrode and the lower conductive portion are electrically connected to each other through the connection portion.
In the method for manufacturing a capacitor element, the lower electrode is formed to extend on the underlying film which is formed on the lower conductive portion provided on the substrate so as to overlap the lower conductive portion. The lower electrode is formed by a film forming method such as CVD, PVD, or the like which can be used in a usual semiconductor manufacturing process.
The dielectric film including an alumina film or the like is formed on the lower electrode, and then the protective film composed of hafnium oxide or the like having a lower etching rate than that of the dielectric film is formed on the dielectric film.
The dielectric film is etched from the protective film so that the dielectric film is patterned to a predetermined planar shape to remove a portion of the dielectric film, which does not overlap the protective film. Therefore, the dielectric film is protected by the protective film, and for example, the dielectric film is patterned to a predetermined planar shape without being excessively etched.
Then, the upper electrode of a larger size than the lower electrode is formed on the capacitor insulating film so as to overlap the connection portion exposed from the underlying film. As a result, the upper electrode and the lower conductive portion are electrically connected to each other, and a capacitor element electrically connected to the lower conductive portion is formed on a substrate.
Therefore, like in the above-mentioned capacitor element, the method for manufacturing a capacitor element is capable of forming a capacitor element having a high capacitance value on a substrate and electrically connecting the capacitor element to a lower conductive portion.
According to an embodiment of the present invention, the method for manufacturing a capacitor element may further includes, before forming the dielectric film and the protective film, forming an interlayer insulating film between dielectric film and the lower electrode in a region of a layered structure formed by laminating in order the lower electrode, the dielectric film, and the upper electrode.
In this configuration, when the capacitor insulating film is patterned by etching, the lower electrode is protected by the interlayer insulating film so as not to be etched. In addition, even if the interlayer insulating film is formed as a portion other than a portion substantially functioning as a capacitor, the electric characteristic of the capacitor element, i.e., the capacitance value, is not decreased.
In this case, the interlayer insulating film may be formed by forming the insulating film so that it overlaps the region and then removing a portion of the insulating film, which overlaps the region.
In this case, it may be possible to form the interlayer insulating film while securing a region where a portion substantially functioning as a capacitor in the capacitor element is formed.
According to an embodiment of the present invention, an electro-optic device includes the above-described capacitor element as a storage capacitor electrically connected to a pixel electrode.
Since the electro-optic device includes the above-described capacitor element, it is possible to hold for a predetermined time a pixel electrode potential which is set according to an image signal supplied to each pixel portion during an operation of the electro-optic device and to enhance the display performance.
The operation and other advantages of the present invention are made clear from the embodiment described below.
The invention will be described with reference to the accompanying drawings, wherein like numbers reference like elements.
A capacitor element, a method for manufacturing the same, and an electro-optic device including the capacitor element as a storage capacitor according to embodiments of the present invention are described with reference to the drawings.
<1: Capacitor Element and Method for Manufacturing the Same>
A capacitor element and a method for manufacturing the same according to embodiments of the present invention are described with reference to
In
The lower electrode 510 is formed above a lower conductive portion 580, such as wiring, provided on a substrate 570 so as to overlap the lower conductive portion 580 and extend on an underlying film 560 composed of an insulating material. The underlying film 560 includes, for example, a semiconductor layer of polysilicon or the like, or a metal film.
The capacitor insulating film 520 has a layered structure including a dielectric film 521 composed of an alumina layer and formed on the lower electrode 510, and a protective film 522 formed on the dielectric film 521 and composed of a hafnium (Hf)-based material having a lower etching rate than that of the dielectric film 521. In other words, the protective film 522 is composed of a material having a lower etching rate for an acid etching solution than that of the dielectric film 521 of alumina or the like, i.e., high resistance to the etching solution. Therefore, the protective film 522 protects the dielectric film so that the dielectric film 521 is not excessively etched when being patterned into a predetermined shape in a process for forming the capacitor element 500. In addition, the dielectric constant of the protective film 522 composed of the hafnium-based material is about 4 times that of the dielectric film 521 composed of alumina. Therefore, the capacitance value of the capacitor element 500 is set to a high value as compared with the case in which only a dielectric film of alumina or the like is provided.
The upper electrode 530 is formed on the capacitor insulating film 520, includes a conductive film of a larger size than the lower electrode 510, and is formed using, for example, the same conductive material as the lower electrode 510.
The upper electrode 530 and the lower conductive portion 580 are electrically connected to each other through a contact hole 550, which is an example of a connection portion of the present invention and exposed from the underlying film 560 by partially removing the dielectric film 521 of the capacitor insulating film 520.
As described above, the capacitor insulating film 520 includes the dielectric film 521 having a high dielectric constant and the protective film 522 having a lower etching rate than that of the dielectric film 521. Therefore, when the capacitor insulating film 520 is patterned by etching, the dielectric film 521 is patterned into a predetermined shape without being excessively etched. Therefore, the contact hole 550 may be exposed from the underlying film 560 by partially removing the dielectric film 521 so that the dielectric film 521 is patterned into a predetermined shape. The upper electrode 530 and the lower conductive portion 580 are electrically connected to each other, and thus the capacitor element 500 and the lower conductive portion 580 are electrically connected to each other. In addition, in the capacitor element 500, even when the dielectric film 521 is formed using a dielectric material having low resistance to an etching solution, the capacitance value of the capacitor element 500 may be set to a high value.
Next, the principal steps of the method for manufacturing the capacitor element 500 are successively described with reference to
As shown in
Next, as shown in
Next, as shown in
Then, as shown in
Therefore, the method for manufacturing a capacitor element of this embodiment is capable of forming a capacitor element 500 having a high capacitance value on a substrate 570 and electrically connecting the capacitor element 500 to a lower conductive portion 580.
A capacitor element and a method for manufacturing the same according to other embodiments of the present invention are described with reference to
As shown in
The interlayer insulating film 590 is formed between a capacitor insulating film 525 and a lower electrode 510 outside a region occupied by a layered structure 595 which is formed by stacking in order the lower electrode 510, the capacitor insulating film 525, and an upper electrode 530. The capacitor insulating film 525 is formed by laminating a dielectric film 523 and a protective film 524 composed of the same materials as the above-described dielectric film 521 and the protective film 522, respectively. In the capacitor element 500a, a portion substantially functioning as a capacitor includes portions of the lower electrode 510, the capacitor insulating film 525, and the upper electrode 520, which overlap an opening 590a formed in the interlayer insulating film 590. The thicknesses of the interlayer insulating film 590, the dielectric film 523, and the protective film 524 are, for example, about 200 nm, 20 nm, and 5 nm, respectively. In the capacitor element 500a, when the dielectric film 523 of the capacitor insulating film 525 is patterned by etching, the lower electrode 510 can be protected by the interlayer insulating film 590 so as not to be etched. Therefore, even when the interlayer insulating film 590 is formed as a portion other than the portion substantially functioning a capacitor, the electric characteristics of the capacitor element 500, i.e., the capacitance value, is not decreased. In addition, the interlayer insulating film 590 suppresses deterioration of the lower electrode 510 due to etching.
Next, the method for manufacturing the capacitor element according to this embodiment is described with reference to
As shown in
Next, as shown in
Therefore, when the dielectric film 523 which is a portion of the capacitor insulating film 525 is patterned by subsequent etching, the lower electrode 510 is protected by the interlayer insulating film 590 so as not to be etched. In addition, even if the interlayer insulating film 590 is formed as a portion other than a portion substantially functioning as a capacitor, the electric characteristic of the capacitor element 500a, i.e., the capacitance value, is not decreased. Therefore, it may be possible to form the interlayer insulating film 590 while securing a region where a portion substantially functioning as a capacitor in the capacitor element 500a is formed.
Next, as shown in
Next, as shown in
Then, as shown in
Therefore, like in the above-mentioned capacitor element 500a, the method for manufacturing a capacitor element according to the embodiment is capable of forming a capacitor element 500a having a high capacitance value on a substrate 570 and electrically connecting the capacitor element 500a to a lower conductive portion 580.
<2: Electro-Optic Device>
Next, the configuration of a liquid crystal device which is an example of an electro-optic device including as a storage capacitor a capacitor element having the same configuration as the above-described capacitor element 500 is described with reference to
<2-1: Overall Configuration of Electro-Optic Device>
First, the overall configuration of a liquid crystal device according to an embodiment of the present invention is described with reference to
In
In a peripheral region around the image display region 10a on the TFT array substrate 10, a data line drive circuit 101, external circuit connection terminals 102, and a sample hold circuit (not shown) are provided along one of the sides of the TFT array substrate 10. Scanning line drive circuits 104 are provided along the two sides adjacent to the one side so as to be covered with the frame light-shielding film 53. Further, in order to connect the two scanning line drive circuits 104 provided on both sides of the image display region 10a, a plurality of wirings is provided along the remaining one side of the TFT array substrate 10 so as to be covered with the frame light-shielding film 53. Further, vertical conduction terminals 106 are provided between the TFT array substrate 10 and the counter substrate 20 in order to secure electric conduction between both substrates.
In
<2-2: Basic Configuration of Pixel Portion>
Next, a circuit configuration in the image display region 10a of the liquid crystal device 1 is described with reference to
Each of the plurality of pixels formed in a matrix and constituting the image display region 10a of the liquid crystal device 1 includes the pixel electrode 9a and TFT 30 for switching control of the pixel electrode 9a, a corresponding data line 6a to which image signals are supplied being electrically connected to a source of the TFT 30. Image signals VID1, VID2, . . . , VIDn written on the data lines 6a may be supplied in a line-sequential manner in that order or supplied to each group of a plurality of adjacent data lines 6a.
A corresponding scanning line 11a is electrically connected to a gate of the TFT 30, and scanning signals G1, G2, . . . , Gm are applied as pulses to the scanning lines 11a with predetermined timing in a line sequential manner in that order. The pixel electrode 9a is electrically connected to a drain of the TFT 30, and a switch of the TFT 30 serving as a switching element is closed for a predetermined period so that the image signals VID1, VID 2, . . . , VIDn supplied from the data lines 6a are written with predetermined timing.
The image signals VID1, VID 2, . . . , VIDn at a predetermined level written in the liquid crystal through the pixel electrodes 9a are held for a predetermined time between the pixel electrodes 9a and the counter electrode formed on the counter substrate. The liquid crystal changes in molecular assembly orientation and order according to the voltage level applied and modulates light, thereby permitting gradient display. In a normally white mode, transmittance for incident light decreases depending on the applied voltage by pixel units, while in a normally black mode, transmittance for incident light increases depending on the applied voltage by pixel units. As a whole, light with a contrast according to an image signal is emitted from a liquid crystal device.
In order to prevent leakage of an image signal stored, a holding capacitor 70 is added in parallel to a liquid crystal capacitance formed between the pixel electrode 9a and the counter electrode. The holding capacitor 70 has the same configuration as that of the capacitor element 500. One of the electrodes of the holding capacitor 70 is connected to the drain of the TFT 30 in parallel to the pixel electrode 9a, and the other electrode is electrically connected to corresponding capacitor wiring 400 at a fixed potential so as to be at a constant potential.
<2-3: Specific Configuration of Pixel Portion>
A specific configuration of the pixel portion of the liquid crystal device 1 is described with reference to
In
(Configuration of First Layer—Scanning Lines, Etc—)
The first layer includes the scanning lines 11a. The scanning lines 11a are patterned to a shape including main lines extending along the X direction in
(Configuration of Second Layer—Tft, Etc—)
The second layer includes the TFTs 30. Each TFT 30 has, for example, a LDD (Lightly Doped Drain) structure and is provided with a gate electrode 3a, a semiconductor layer 1a, and an insulating film 2 including a gate insulating film which insulates the gate electrode 3a from the semiconductor layer 1a. The gate electrode 3a is composed of, for example, conductive polysilicon. The semiconductor layer 1a is composed of, for example, polysilicon, and includes a channel region 1a′, a low-concentration source region 1b, a low-concentration drain region 1c, a high-concentration source region 1d, and a high-concentration drain region 1e. The TFT 30 preferably has a LDD structure, but may have an offset structure in which impurities are not implanted into the low-concentration source region 1b and the low-concentration drain region 1c or a self-aligned TFT in which a high concentration of impurities is implanted using the gate electrode 3a as a mask to form a high-concentration source region and a high-concentration drain region.
The gate electrode 3a of the TFT 30 is electrically connected, in a portion 3b, to the corresponding scanning line 11a through a contact hole 12cv formed in the underlying insulating film 12. The underlying insulating film 12 is composed of, for example, a silicon oxide film or the like, and has an interlayer insulating function between the first and second layers. In addition, the underlying insulating film 12 is formed over the entire surface of the TFT array substrate 10 and thus has the function to prevent changes of the element characteristics of the TFT 30 due to roughening or staining by polishing of the substrate surface. Although, in this embodiment, the TFT 30 is a top-gate type, it may be a bottom-gate type.
(Configuration of Third Layer—Data Lines, Etc—)
The third layer includes the data lines 6a and relay layers 600.
The data lines 6a each include a single-layer or multilayer metal film containing aluminum or the like. The data lines 6a may be formed as three-layer films each including aluminum, titanium nitride, and silicon nitride which are deposited in that order from below. The data lines 6a are formed to partially cover the channel regions 1a′ of the TFTs 30. Therefore, the channel regions 1a′ of the TFTs 30 are shielded from incident light on the upper layer side by the data lines 6a which can be disposed near the channel regions 1a′. The data lines 6a are electrically connected to the high-concentration source regions 1d of the TFTs 30 through contact holes 81 passing through the first interlayer insulating film 41.
The relay layers 600 are formed as the same films as the data lines 6a. As shown in
The first interlayer insulating film 41 is composed of, for example, NSG (non-silicate glass). Silicate glass such as PSG (phosphosilicate glass), BSG (boron silicate glass), BPSG (borophosphosilicate glass), and the like, silicon nitride, silicon oxide, and the like may be used for the first interlayer insulating film 41.
(Configuration of Fourth Layer—Storage Capacitors, Etc—)
The fourth layer includes the storage capacitors 70. Each of the storage capacitors 70 includes a capacitor electrode 300 as an upper electrode and a lower electrode 71 which is opposed to each other with a capacitor insulating film 75 provided therebetween. The capacitor insulating film 75 has a structure in which a dielectric film 75a having a high dielectric constant and a protective film 75b having a lower etching rate than that of the dielectric film 75a are laminated. A contact hole 84 is formed after an opening is formed by etching a portion of the dielectric film 75a, which does not overlap the protective film 75b. An extension of the capacitor electrode 300 is electrically connected to the relay layer 600 through the contact hole 84 passing through the second interlayer insulating film 42.
The capacitor electrode 300 and the lower electrode 71 are metal films each having a single-layer or multilayer structure containing at least one of the metals such as Al, Ti, Cr, W, Ta, Mo, and the like. The capacitor electrode 300 and the lower electrode 71 may have a layered structure including an alloy, metal silicide, polysilicide, and nitride. The storage capacitors 70 disposed on the data lines 6a through the interlayer insulating film 42 and adjacent to the TFTs 30 securely shield the channel regions 1a′ of the TFTs 30 from incident light on the upper layer side.
In addition, as shown in
As shown in
(Configuration of Fifth Layer—Pixel Electrodes, Etc—)
The third interlayer insulating film 43 is formed over the entire surface of the fourth layer, and further, the pixel electrodes 9a are formed as the fifth layer on the third interlayer insulating film 43. The third interlayer insulating film 43 is composed of, for example, NSG. Silicate glass such as PSG, BSG, BPSG, and the like, silicon nitride, silicon oxide, and the like may be used for the third interlayer insulating film 43. Like the second interlayer insulating film 42, the surface of the third interlayer insulating film 43 is planarized by CMP or the like.
The pixel electrodes 9a (the outlines are shown by broken lines 9a′ in
Each of the pixel electrodes 9a is electrically connected to the extension of the capacitor electrode 300 through the contact hole 85 passing through the interlayer insulating film 43 (refer to
As described above, the extension of the capacitor electrode 300 and the relay layer 600 and the relay layer 600 and the high-concentration drain region 1e of the TFT 30 are electrically connected to each other through the contact holes 84 and 83, respectively. That is, the pixel electrode 9a and the high-concentration drain region 1e of the TFT 30 are electrically connected to each other through the relay layer 600 and the extension of the capacitor electrode 300. Thus, it is possible to avoid difficulty in connecting a pixel electrode and a drain through a contact hole because of a long distance between layers. In addition, the layered structure and the manufacturing process are not complicated. Further, an alignment film 16 subjected to predetermined orientation treatment, such as rubbing, is provided on the pixel electrodes 9a. The configuration of the pixel portion on the TFT array substrate side is described above.
On the other hand, on the counter substrate 20, the counter electrode 21 is provided over the entire surface of the facing surface, and further, an alignment film 22 is provided on the counter electrode 21 (the lower side of the counter electrode 21 shown in
The liquid crystal layer 50 is provided between the TFT array substrate 10 and the counter substrate 20 configured as described above. The liquid crystal layer 50 is formed by sealing a liquid crystal in a space formed by sealing the peripheries of the substrates 10 and 20 with a sealing material. When an electric field is not applied between the pixel electrodes 9a and the counter electrode 21, the liquid crystal layer 50 assumes a predetermined orientation state by the alignment films 16 and 22 subjected to orientation treatment such as rubbing or the like.
The above-described configuration of the pixel portion is common to all pixel portions as shown in
The entire disclosure of Japanese Patent Application No. 2008-270614, filed Oct. 21, 2008 is expressly incorporated by reference herein.
Claims
1. A capacitor element substrate comprising:
- a lower conductive portion;
- an underlying film which covers the lower conductive portion;
- a lower electrode formed on the underling film;
- a capacitor insulating film including: a dielectric film formed on the lower electrode; and a protective film formed on the dielectric film and having a lower etching rate than that of the dielectric film;
- an upper electrode formed on the capacitor insulating film, the upper electrode and the lower conductive portion being electrically connected to each other through a connection portion exposed from the underlying film by partially removing the underlying film and the capacitor insulating film; and
- an interlayer insulating film formed between the capacitor insulating film and the lower electrode outside a region occupied by a layered structure formed by laminating in order the lower electrode, the capacitor insulating film, and the upper electrode.
2. An electro-optic device comprising: the capacitor element substrate according to claim 1 and a pixel electrode, wherein the upper electrode is electrically connected to the pixel electrode.
3. An electro-optic device comprising:
- a capacitor element substrate including: a lower conductive portion; an underlying film which covers the lower conductive portion; a lower electrode formed on the underling film; a capacitor insulating film including: a dielectric film formed on the lower electrode; and a protective film formed on the dielectric film and having a lower etching rate than that of the dielectric film; an upper electrode formed on the capacitor insulating film, the upper electrode and the lower conductive portion being electrically connected to each other through a connection portion exposed from the underlying film by partially removing the underlying film and the capacitor insulating film; and a pixel electrode, wherein the upper electrode is electrically connected to the pixel electrode.
7473926 | January 6, 2009 | Lee et al. |
2007-227752 | September 2007 | JP |
2008-058578 | March 2008 | JP |
Type: Grant
Filed: Oct 20, 2009
Date of Patent: Sep 11, 2012
Patent Publication Number: 20100097536
Assignee: Seiko Epson Corporation (Tokyo)
Inventor: Takunori Iki (Chitose)
Primary Examiner: James Dudek
Attorney: Maschoff Gilmore & Israelsen
Application Number: 12/582,565
International Classification: G02F 1/1343 (20060101);