Electronic postal rate memory

- Pitney Bowes Inc.
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Description

FIG. 1 is a perspective view of an electronic postal rate memory showing my new design;

FIG. 2 is a front elevational view thereof on a reduced scale;

FIG. 3 is a top plan view thereof on a reduced scale;

FIG. 4 is a bottom view thereof on a reduced scale;

FIG. 5 is a rear elevatioal view thereof on a reduced scale;

FIG. 6 is a left side elevational view thereof on a reduced scale;

FIG. 7 is a right side elevational view thereof on a reduced scale.

Referenced Cited
U.S. Patent Documents
3017232 January 1962 Schwab et al.
3798507 March 1974 Damon et al.
3952232 April 20, 1976 Coules
Other references
  • Electronics, 2-17-77, p. 22-Circuit Board with Ejector Handle. Electronics, 4-28-77, p. 99, top right, Memory Board. Vero Bulletin, 6-71, Card Ejector.
Patent History
Patent number: D261760
Type: Grant
Filed: Dec 22, 1978
Date of Patent: Nov 10, 1981
Assignee: Pitney Bowes Inc. (Stamford, CT)
Inventor: Daniel F. Dlugos (Huntington, CT)
Primary Examiner: Susan J. Lucas
Attorneys: Mark E. Levy, William D. Soltow, Jr., Albert W. Scribner
Application Number: 5/972,583
Classifications
Current U.S. Class: D14/114; D13/99
International Classification: D1402; D1399;