Holder for testing an integrated circuit chip
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Description
FIG. 1 is a top, front, and right side perspective view of a holder for testing an integrated circuit chip showing my new design;
FIG. 2 is a bottom, rear, and left side perspective view thereof;
FIG. 3 is a left side elevational view thereof, the right side being a mirror image thereof;
FIG. 4 is a rear elevational view thereof; and
FIG. 5 is a front elevatioal view thereof.
Referenced Cited
Patent History
Patent number: D298923
Type: Grant
Filed: Feb 4, 1986
Date of Patent: Dec 13, 1988
Assignee: Vanguard Electronics Company, Inc. (Gardena, CA)
Inventor: Yoshinobu Sakihara (Los Angeles, CA)
Primary Examiner: B. J. Bullock
Assistant Examiner: Ruth Takemoto
Law Firm: Freilich, Hornbaker, Rosen & Fernandez
Application Number: 6/825,804
Type: Grant
Filed: Feb 4, 1986
Date of Patent: Dec 13, 1988
Assignee: Vanguard Electronics Company, Inc. (Gardena, CA)
Inventor: Yoshinobu Sakihara (Los Angeles, CA)
Primary Examiner: B. J. Bullock
Assistant Examiner: Ruth Takemoto
Law Firm: Freilich, Hornbaker, Rosen & Fernandez
Application Number: 6/825,804
Classifications
Current U.S. Class:
Element Or Attachment (4) (D10/80)