Delay line correlator
A circuit for the analog correlation of a 2.5 GHz signal to remove impairments such as echo, cross talk and intersymbol interference is described. Loop stability in a loop which generates an error signal and tap weights is achieved by providing a further delay from the taps of the delay line.
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The invention relates to the field of analog signal processing.PRIOR ART AND RELATED ART
Digital signal processing (DSP) is widely used to process data carrying signals to remove, for example, inter-symbol interference (ISI), echo, cross talk and other impairments, and to provide filtering, correlation and other processing. Typically, after some analog filtering and amplification, the analog signal is converted to a digital signal for the DSP. The design of the analog-to-digital (A-to-D) converter can become critical particularly as baud rates increase. In fact, in some applications the design of an A-to-D converter may be considered to be a limiting factor.
The problems associated with the prior art will be described in more detail in conjunction with
A method and apparatus are described for processing an input analog signal X(t) in the analog domain. In the method of the present invention, the input signal is delayed in a plurality of serial analog stages. The signal tapped from each of the stages (n) is further delayed and combined with an analog error signal to provide a plurality of analog tap weights Wn. The signal from a stage n is then combined with the tap weight Wn for that stage. A summing occurs of the plurality of signals XnWn to provide a signal Y(t). Slicing of the summed signal is used to generate the error signal. The further delay provides stability needed because of the feedback loop which includes the generation of the error signal and tap weights.
In one embodiment, the further delaying of a signal from a stage n is provided by using a signal from stage n+a, where a is a positive integer.
A method and apparatus for processing an analog signal is described. In the following description, numerous specific details are set forth, such as specific frequencies, in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art, that the present invention may be practiced without these specific details. In other instances, well-known circuit elements, such as amplifiers and multipliers, are not described in detail in order to not unnecessarily obscure the present invention.Prior Art of FIG. 1
The DSP input is to a feed forward equalizer 19 to remove such impairments as ISI caused by insertion loss. The output of equalizer 19 is summed with an output from the feedback equalizer 27. An error signal is used by the DSP section which is developed through a slicer 21. The input and output of the slicer 21 are subtracted from one another by the subtractor 24 to provide an error signal on line 25. This error signal is coupled to both equalizers 19 and 27. A digital output signal is provided on line 20.
The signal-to-noise ratio for the arrangement of
As will be seen in conjunction with
Unlike the duplexing circuit of
The input signal from the circuit 32 is coupled to a low pass filter 40 through the high frequency transformer 34. This may be an ordinary analog low pass filter such as typically used to limit the high frequencies of a signal which is subsequently digitized. Generally, frequencies higher than those that can be faithfully digitized are removed.
The output of the filter 40 is coupled to an amplifier 41 which receives a gain control signal. The amplifier 41 may be an ordinary analog amplifier, such as used in DSP approach of
The output of the amplifier 41 is coupled to an analog delay line 45. The delay line 45 has a plurality of stages such as stages 45a and 45b, each of which provides equal periods of delay. Each stage has one or more segments, each segment of which includes an inductor and a capacitor. This allows for a fractionally spaced equalizer as well as symbol spaced equalizers. For the illustrated embodiment, each stage has a single inductor and a single capacitor. Ideally the delay line 45 is lossless, although as a practical matter, there is some loss associated with each of the stages. For purposes of discussion, each of the stages are consecutively numbered from n=1 to n=N.
In a preferred embodiment, the entire delay line is fabricated from passive elements (inductors and capacitors) without amplification between stages. This reduces the noise that would otherwise occur and build up over the delay line. Ideally, the magnitude at each tap is constant with only the phase of the signal changing.
A signal at a tap from each stage of the delay line 45 is coupled to two combining circuits. Specifically in
The resultant analog signal from multiplier 52 is coupled to a integrator 56. The integrator 56, which may be an ordinary capacitance integrator, integrates the analog signal from the multiplier 52. In one embodiment, the integrator 56 has a time constant measured in microseconds for a received signal in the GHz range. Thus, this integration is relatively long with respect to the period of the received signal. The output of the integrator 56 is coupled as one input to the multiplier 58 and is multiplied by the signal from tap 50.
There is a delay circuit 51, two combining circuit and an integrator for each of the taps of the delay line 45. The outputs from the second combining circuits, such as the multiplier 58, are all summed in the summer 60. As will be discussed later, the output of a summer 66 provides the analog output signal, Y(t), which is the input signal X(t), after it has been processed to remove impairments.
The analog error signal on line 54 is developed by slicing the signal Y(t) in the slicer 61 and then subtracting the resultant signal from the input to the slicer in the subtractor 62. This results in an error signal which is used, as will be described, to develop the adaptive tap weights forming one input to the second combining circuit (e.g. multiplier 58).
The embodiment of
The circuitry of
The circuitry of
where Y(t) is the signal at the output of the summer 60, Wn the adaptive tap weights, and X(t−nT), the input function at the taps for each stage n, where T is equal to the time delay of each of the stages. This equation can be expanded as follows:
Y(t)=W0X(t)+W1(t−T)+W2(t−2T) . . . Wn(t−NT)
where N+1 is the total number of stages in the delay line. Each term in this equation has a value represented by the output of the second combining means such as the multiplier 58. The terms are then summed within the summer 60 to provide Y(t).
The tap weights for the embodiment of
where 1/A is a constant, e(t) is the error signal on line 54, and τ is the delay provided by the differential delay 51. The integration shown in the above equation is performed by the integrator 56.
As may be noted from
In DSP this loop stabilizing delay is not required. In the digital domain, an error signal value, for instance, can be readily stored and then used under the control of a timing signal, and thus, the feedback problem described above does not occur.
An alternate embodiment is shown in
Assume that τ is equal to 2T. If this is the case, then the signal at the tap of stage n+2 provides the same delay as the differential delay 51 of
The inductors of
The performance of the duplexing circuits of
Thus, improved front end processing has been described for a data carrying signal received over a twisted pair. Many of the impairments often removed with DSP are removed in the analog domain. This, as mentioned, significantly reduces the performance required of the A-to-D converter, and thereby provides a more readily realizable, better performing circuit and lower power consumption.
1. A method comprising:
- delaying a received signal in a plurality of serial analog stages (n);
- further delaying a signal tapped from stage n;
- combining the further delayed signal from stage n with an analog error signal to provide an analog tap weight Wn; and
- combining the delayed signal from stage n with Wn.
2. The method of claim 1, wherein the step of delaying the received signal from stage n comprises receiving a signal from stage n+a, where a is a positive integer.
3. The method of claim 1, wherein the combining of the delayed signal from stage n with Wn results in a plurality of signals XnWn.
4. The method of claim 3, including summing the plurality of signals XnWn.
5. The method of claim 4, including slicing a signal resulting from the summing of the plurality of signals XnWn to provide the analog error signal.
6. The method defined by claim 5, wherein there is a loop delay in the summing, slicing and the steps for forming the XnWn and wherein the further delaying provides a delay equal to or greater than the loop delay.
7. The method of claim 5, wherein the step of delaying the received signal from stage n comprises receiving a signal from stage n+a, where a is a positive integer.
8. The method of claim 2, wherein the combining of the delayed signal from stage n+a with Wn results in a plurality of signals XnWn.
9. The method of claim 8, including summing the plurality of signals XnWn.
10. The method of claim 9, including slicing a signal resulting from the summing of the plurality of signals XnWn to provide the analog error signal.
11. The method defined by claim 1, wherein generation of Wn includes integrating the signal from the first combining step.
12. An apparatus comprising:
- an analog delay line having a plurality of taps at each of stages (n), a first one of the stages for receiving an input signal;
- a plurality of delay circuits each coupled to a tap at a stage n of the delay line to provide a delayed signal;
- a plurality of first combining circuits, each for combining an error signal with the delayed signal from one of the delay circuits to provide a plurality of tap weights Wn; and
- a plurality of second combining circuits, each coupled to a stage n and coupled to receive one of the weighting signals Wn.
13. The apparatus of claim 12, wherein each stage of the delay line includes an inductor and a capacitor.
14. The apparatus of claim 12, wherein the first combining circuits each comprise a first analog multiplier.
15. The apparatus of claim 14, including an integrator coupled to each of the first combining circuit.
16. The apparatus of claim 14, wherein the second combining circuits each comprise a second analog multiplier.
17. The apparatus of claim 12, including a summer coupled to the plurality of second combining circuits for summing the output of the second combining circuits.
18. The apparatus of claim 17, including a slicer circuit coupled to receive a summed signal from the summer.
19. The apparatus of claim 18, wherein the first combining circuits comprise first multipliers and the second combining circuits comprise second multipliers.
20. The apparatus of claim 19, wherein each stage of the delay line comprises an inductor and capacitor.
21. An apparatus comprising:
- an analog delay line having a plurality of stages (n), a first one of the stages for receiving an input signal;
- a plurality of first combining circuits, each for combining an error signal with a signal tapped from one of the stages n+a of the delay line to provide a plurality of weighting signals Wn, where “a” is a positive integer; and
- a plurality of second combining circuits, each coupled to a stage n and coupled to receive one of the signals Wn.
22. The apparatus of claim 21, wherein each of the stages of the delay line has an inductor and a capacitor.
23. The apparatus of claim 22, wherein each of the first combining circuits comprises a first multiplier.
24. The apparatus of claim 23, wherein each of the second combining circuits comprise a second multiplier.
25. The apparatus of claim 24, including a summer coupled to the second multipliers.
26. The apparatus of claim 25, including a slicer coupled to the summer and the first multipliers.
Filed: Oct 5, 2011
Date of Patent: Nov 6, 2012
Assignee: NetLogic Microsystems, Inc. (Irvine, CA)
Inventors: Joseph N. Babanezhad (Cupertino, CA), Bijit Halder (Santa Clara, CA)
Primary Examiner: Don N Vo
Attorney: Sterne, Kessler, Goldstein & Fox PLLC
Application Number: 13/373,475
International Classification: H03K 5/159 (20060101);