Gap elimination in memory data accession

This invention relates to the reduction of gaps in the flow of data accessed in a synchronous serial storage serial communicating data processing memory by the provision of access storage capability at each storage location. The problem to which the invention is directed is the fact that in a synchronously driven array of the type having a number of data storage locations that are accessed by a communicating channel linking all the storage locations in series, the information flow in the communication channel will be limited by the time required for the proper point to be moved around each storage location and the resulting gaps in the data will effect the speed of response. The invention takes the bits to be transferred as they are synchronously propagated around one loop and holds them as the data is synchronously propagated around the other loop until the insertion point arrives. The invention provides a specific size buffer or intermediate storage loop that can hold the amount of data being transferred until the timing is accommodated. The intermediate loop buffer must be big enough for the transferring data but it should not be much larger or there will still be a gap in the data in the communicating loop in proportion to the amount the intermediate loop is oversize.

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Patent History
Patent number: T102502
Type: Grant
Filed: May 5, 1981
Date of Patent: Dec 7, 1982
Inventor: Clifton D. Cullum, Jr. (Putnam Valley, NY)
Application Number: 6/260,620
Current U.S. Class: With Switch At Interacting Point (365/16)
International Classification: G11C 1908;