Synchronous data link slow-poll protocol
A first data processor (10) and at least a second data processor (11) are connected by a data link (12). The processors each have a communication adapter (14) which is connected to the data link and system clock (21) which times functions within the processor. Under a synchronous data link control (SDLC) protocol which has information frames and supervisory frames, one of the processors is designated as the primary station and the other, the secondary station. Whenever supervisory frames are transmitted between the primary and secondary stations, means are operative for inserting a mandatory non-polling quiet period of a predetermined length prior to each poll so that the processor at the secondary station is freed for non-polling functions.
Type: Grant
Filed: Nov 9, 1982
Date of Patent: Mar 6, 1984
Inventors: Lon E. Hall (Austin, TX), Richard E. Eveland (Austin, TX)
Application Number: 6/440,263
International Classification: G06F 300;
