Abstract: In partial scan testing of a circuit the optimal quantity of scan flip-flops required to eliminate all feedback, except self-loops, in a circuit is determined. For determining a minimal feedback vertex set (MFVS) for the S-graph of a circuit to be tested, MFVS-preserving transformations, partitioned search strategy and integer linear program (ILP)-based lower bounding techniques are combined to obtain an exact algorithm for computing the MFVS. The result is used in the fabrication of the circuit with minimal overhead in terms of area and performance degradation as a result of providing the capability to perform partial scan testing of the fabricated circuit.

Abstract: A partial scan methodology selects scan flip flops (FFs) in the minimum feedback vertex set (MFVS) of the FF dependency graph so that all loops, except self-loops, are broken. The MFVS of the circuit, i.e. the minimum quantity of gates whose removal makes the circuit acyclic, is a lower bound and in many cases is significantly smaller than the MFVS of the dependency graph. Since only FFs arc considered for scan, FFs are repositioned so that, in a modified circuit, every circuit MFVS gate drives one FF that can be scanned. A method is disclosed by which resynthesis and retiming can always transform any circuit into an equivalent circuit whose FF dependency graph MFVS is equal to the MFVS of the original circuit. Therefore, the MFVS of a circuit is a lower bound on the quantity of scan FFs needed. The necessary and sufficient conditions under which legal retiming can produce the desired FF repositioning are identified.

Abstract: An integrated circuit structure is generated to perform a given combinational function. A data processing system generates the integrated circuit structure when provided with an input specification of the function to be performed by the structure. The resulting integrated circuit structure is comprised of both restoring logic networks and pass logic networks. The integrated circuit structure is generated in three major steps. First, data structures, comprised of multidimensional spaces, are computed to represent the function. Two types of data structures are computed: those which view an input as a pass value and a data structure which views the inputs solely as control variables. In the second major step prime implicants are found within the data structures. Third, from among the prime implicants a certain subset is selected to cover the function most efficiently. The third major step, of selecting a most efficient subset of prime implicants, further comprises three main substeps.

Abstract: An apparatus for determining power supply wirings of a semiconductor device includes a unit for executing a logic simulation based on both data concerning each of logic circuit blocks constituting the semiconductor device and data concerning signals for testing operations of the device, and thereby generating a respective output signal data for the logic circuit blocks, a unit for computing a respective operational frequency of the logic circuit blocks based on the generated output signal data, and a unit for computing a respective wiring width of each power supply line for supplying each of the logic circuit blocks with powers. The respective wiring width of each power supply line is determined based on the computed respective operational frequency of the logic circuit blocks and a plurality of wiring widths of respective power supply lines optimumly selected for each of a plurality of operational frequencies in advance.

Abstract: To improve the coupling adjustment workability and precision of a rotor, irrespective of change in bearing characteristics due to an increase of rotational speed, the apparatus detects angular frequencies (.omega.) and reference mark positions (.theta.) of the rotor; detects vibration displacements (r) of the rotor; analyzes vibration vector components (.omega.), (r) and (.theta.) of rotation synchronizing vibrations; extracts a specific angular frequency (.omega..sub.1) at which a higher harmonic vibration frequency (.omega..sub.R) matches a natural frequency of the rotor, and various rotation synchronizing vibration vector components at (.omega..sub.1), at (.omega..sub.R) and (.omega..sub.2 to .omega..sub.i), respectively; estimates static vibration vector components (r.sub.0, .theta..sub.0) at zero angular frequency (.omega..sub.0) on the basis of rotation synchronizing vibration vector components (r.sub.T, .theta..sub.T) at (.omega..sub.1 to .omega..sub.

Abstract: An apparatus and a method are disclosed for measuring the concentration of fibrinogen that contributes to the clotting of blood. The apparatus utilizes a potentiophotometer that provides an output which is directly indicative of the fibrinogen concentration in the blood sample. The present invention takes into account the prothrombin time which is defined as the time between the injection of a reagent into a sample of the blood being measured and the time of the clotting or coagulation. The present invention relies on the knowledge that a specified minimum amount of fibrinogen needs to be present in the blood sample in order to detect the forming of a clot. After the detection of the specified minimum amount, the invention then relies on monitors for the fibrinogen concentration to decrease to a value which is less than the specified minimum amount.

Abstract: Methods and apparatae for metering energy consumption in a mass transfer heat delivery system using acoustic signals. A first type of method uses the phase difference between two simultaneously generated acoustic signals to determine the flow rate of liquid through a station of the heat delivery system. A first transducer and second transducers are used to transmit the first and second acoustic signals, respectively, through the liquid in response to an applied drive signal. The drive signal is removed from the first and second transducers such that the first and second transducers may be used to detect the arrival of the second and first acoustic signals, respectively. A phase detector measures the phase difference between the two acoustic signals as detected by the first and second transducers. A second type of method uses time lag analysis. A first transducer is used to transmit an acoustic signal through the liquid towards a second transducer in response to an applied drive signal.

Abstract: The present invention provides method and apparatus for testing data transmissions between fax modems (and other data transmission devices which utilize asynchronous serial ports for connection of DTE equipment) through synchronization and resynchronization of data bits input to a computer from a receiving fax modem with a plurality of preshifted sequences of data bits stored in the computer's memory. In a closed loop testing environment, first and second fax modems are connected together via a synchronous telephone line and are coupled to a computer via first and second asynchronous lines input to the computer's COM ports. The program utilized by the computer initially stores in memory a first sequence of data bits partitioned into units with each unit comprising N data bits.

Abstract: A novel method for analyzing a light intensity distribution on a flat surface in a projection system wherein a pattern is projected by use of a light through a pupil on the flat surface. The pattern is analyzed into plural polygonal elements where a combination of the polygonal elements constitutes the pattern. Fourier transformations of vertexes of each of the polygonal elements except for the pattern are calculated for subsequent addition and subtraction of the Fourier transformations of all the polygonal elements to thereby obtain a Fourier transformation of the pattern. A product of the Fourier transformation of the pattern and a pupil function is calculated for the pupil. An invert Fourier transformation of the product is calculated to thereby obtain a light intensity distribution.

Abstract: A first-in first-out (FIFO) memory includes flag generation circuitry indicating the relative fullness of the memory. A write and a read counter count the number of read and write clock signals used to read to and write from the memory. A subtractor circuit receives the values in the counters as inputs, and generates a difference signal as an output. This difference signal is then compared to a program value, and a flag generated indicating the relative magnitudes of the difference value and the program value. Several different program values can be utilized to generate several different flags for the memory.

Abstract: A data logger includes a housing containing at least one sensor; programmable controller including a pre-programmed Erasable Programmable Read Only Memory (EPROM) containing control instructions and sensor drivers for all sensors; a Random Access Memory (RAM) providing data storage for storing data from each sensor; a power supply; and electromagnetic transfer device for accessing the logger and recovering data from the data storage from external to the casing; the RAM being adapted to accept, from external to the housing and via the electro-magnetic transfer device, instructions on the sensor drivers to evoke a desired sample regime; the logger also including a power up coil is provided within the housing to enable power from the external to the housing to be supplied during programming and during recovery of data.

Abstract: A three-dimensional measuring method obtains three-dimensional information related to an image including one or a plurality of objects based on input information which describes the image. The method includes the steps of (a) selecting information necessary for calculating marks of presumed information from the input information, where each of the marks are used to evaluate the appropriateness of the presumed information, (b) calculating marks of each pixel of the image based on the information selected by the step (a) and based on feedback information which is derived from an internal state, where the internal state includes information related to the object for each pixel of the image, (c) adding the marks for each pixel calculated in the step (b) for each object so as to obtain a total mark, (d) arbitrarily changing the internal state so as to reduce the total mark, and (e) outputting the internal state in which the total mark is a local minimum as the three-dimensional information.

Abstract: A sampled-continuous probability method of velocity measurement of an object having informatively-structural inhomogeneity by periodical execution of a cycle of the measurement, with determination of time during which a selected local part of the object moves along the measuring base of zone of observation is proposed. Selection of the local part in the beginning of the measuring base and its subsequent determination at the end of the measuring base is performed with the use of an informative aggregate of selected informative signs of a dominant informative component of the inhomogeneity. In order to increase the accuracy and speed of the method, the beginning of each cycle of velocity measurement is performed in response to a special command formed after the beginning of a preceding cycle of the velocity measurement with a given interval of time of shifting of the cycles, but within the preceding cycle.

Abstract: An apparatus and method are provided for calibrating a measuring transmitter which provides an output signal proportional to a parameter of interest measured by a sensor in the measuring transmitter without removing the measuring transmitter from its normal operating position. The apparatus includes a housing, a calibration sensor element located in the housing for sensing said parameter of interest, and a tube for coupling the housing to the measuring transmitter, thereby exposing the calibration sensor to the same parameter of interest as the measuring sensor in the measuring transmitter.

Abstract: A method is described for dynamically calibrating a flowmeter used in cardiopulmonary performance analyzing equipment which takes into account the ambient conditions at the test site in terms of relative humidity, barometric pressure and temperature. At the time of factory calibration, a density factor is computed and stored in a nonvolatile memory along with a calibration factor obtained by passing a known volume of gas at a known relative humidity, temperature and pressure through a pneumotach mouthpiece in a predetermined time span. When the system is being used in the field to evaluate a patient, a new density factor is computed that takes into account the relative humidity, barometric pressure and temperature at the test site and this new density factor along with the density factor previously computed and stored at factory calibration are used to compute a new flow calibration factor for use in obtaining an accurate flow parameter from the system flowmeter.

Abstract: Application of VHDL simulators to check the conformance of a design with Design for Testability (DFT) rules. A special DFT logic using VHDL's powerful logic modeling capabilities is defined and a kind of symbolic simulation based on this DFT logic is performed.

Abstract: A method of signal sample interpolation utilizing a second order curve utilizing a linear interpolator to select a mid-point between respective input samples, eliminating phase error and spatial variation, utilizing the interpolated points as reference points for a quadratic interpolation wherein the space between the reference points is one half the distance between respective signal sample points, and thirdly combining the operations of linear interpolation and quadratic interpolation for simultaneous execution. More particularly, the quadratic interpolation is reformed based on the output of the linear interpolation.

Abstract: A filter capable of having its damping and frequency parameters independently varied. The filter can be represented in either a digital or an analog computation network. The network comprises four multipliers for multiplying by a frequency term twice and a damping factor twice. In addition, the network comprises two unit delay blocks for temporarily storing previous signal input values for zeros or output values for poles. These stored values are used in computing subsequent outputs. The multipliers are configured with adders and subtractors to compute a next output value as a combination of a current input, a weight-2+2df+f.sup.2 -wd.sup.2 f.sup.2 times the most recent saved value and a weight 1-2df+wd.sup.2 f.sup.2 times the previous saved value. Moreover, unity gain at DC can be achieved.

Abstract: A filter circuit switches a switching mechanism based on multiplier held in a data register DATA RGST as a digital data, based on the output data of data register DATA RGST, a multiplication circuit M is arranged to have weights corresponding to a capacity of capacitance connected with a common analog input voltage X.

Abstract: A Galois field multiplication method for a set of a finite number of elements which enables four arithmetical operations including an addition, a deduction, a multiplication and a division, and a multiplier utilizing the multiplication method are disclosed. The Galois field multiplication method easily realizes various Galois field multipliers by ANDing respective items of a multiplicand with a corresponding one of the items of a multiplier factor in a stepwise manner, rotating left values resulted from the AND operation at the previous step, exclusively ORing the respective values resulted from the rotation with the respective corresponding values resulted from the AND operation at the current step, and operating on the highest polynomial term generated at the previous step in accordance with a generated polynomial.

Abstract: An integrated multichip memory module structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the appearance of a single, higher level memory chip. A memory subunit is formed having N memory chips with each memory chip of the subunit having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the module's I/O pins. A preformed electrical interface layer is employed at one end of the memory subunit to electrically interconnect the controlling logic chip with the memory chips comprising the subunit. The controlling logic chip has smaller dimensions than the dimensions of the memory chips comprising the subunit.

Abstract: A poly-silicon or amorphous silicon plate having cone-like protrusions is provided on a Si substrate in a tunnel window area such that the edges of the protrusions are placed very close to a floating gate. Alternatively, the top surface of a Si substrate is shaped into protrusions.

Abstract: An electrically erasable and programmable memory device has a twin well electrically separated by an insulating wall into a plurality of sections respectively assigned to a plurality of memory sectors. The plurality of sections are selectively biased for erasing data bits stored in floating type field effect transistors that form the plurality of memory sectors.

Abstract: The present invention provides methods and apparatus for resetting all of the cells in a random access memory (RAM) during one clock cycle without requiring ancillary drivers. At the start of the reset cycle, each column in the memory array is selected to receive the reset value and then each data line in the array is driven low while the inverse of the data line is driven high. After a first predetermined delay, each word line is driven high and all of the memory cells are thus reset. The word lines are then driven low and after a second predetermined delay, the data lines are driven back to a high value. In this manner, each cell in the memory array is reset during one clock cycle.

Abstract: In a dynamic random access memory in which the number of data buffers is selectable, a buffer supply can be configured by a control signal to provide pump charge capacitance which is appropriate for providing the power required for energizing the selected number of buffers. In response to an external control signal, a second capacitor (or capacitor bank) can be precharged and then applied to the output terminal of buffer supply simultaneously with the precharging and application of the charge on the first capacitor. The dimension of the first capacitor is suitable for a buffer supply for the first buffer configuration and the second capacitor is suitable for a buffer supply for additional buffer amplifiers of the second configuration.

Abstract: In a semiconductor memory device having a plurality of memory cells and a data output buffer for transferring a data signal from the memory cells to external peripheral circuits, a circuit for controlling the data output buffer, comprising a address transition detector for detecting a transition of an address signal to generate an address transition detect signal in a pulse form, a delay controller for generating a delay control signal, the delay control signal having a logic value set by a manufacturer according to whether the semiconductor memory device has a repaired memory cell, and an output enable signal generator for generating an output enable signal at a time point delayed by a time period from the generation of the address transition detect signal from the address transition detector, the time period being determined based on a logic value of the delay control signal from the delay controller, the output enable signal generator outputting the output enable signal to the data output buffer to control

Abstract: A shift register comprises a plurality of amorphous silicon thin-film transistors configured in a plurality of register cells through which data is shifted through a plurality of amorphous silicon thin-film floating-gate transistors. In the event power is cutoff or lost, the floating gate transistors non-volatilely store the data which can be recovered or restored when power is subsequently turned on. Each cell comprises two stages in which data signals are written before being input into the next stage and next cell. A clock generator receives clocking signals for controlling the shifting of data through the register.

Abstract: A method of, and apparatus for, decoupling a defective or otherwise non-operational memory block from the power lines of a memory device is disclosed. Defects which cause excessive current consumption in defective memory blocks can be repaired through this approach. Mass-production yields can be improved significantly.

Abstract: A semiconductor memory device includes a plurality of memory cell arrays and a plurality of word lines and bit lines. The semiconductor memory device has a plurality of row driving circuits for simultaneously activating a plurality of word lines, and a plurality of column driving circuits for simultaneously and independently activating a plurality of column selection lines to simultaneously select a plurality of bit lines. A data selector selects, from the memory cells selected by the word and bit lines, a memory cell selected by different word lines and bit lines. Thus, a plurality of bits are read out or written into the memory cell arrays in parallel.

Abstract: An integrated circuit memory (30) having redundancy shares read, global data lines shared between a regular memory array (35) and a plurality of redundant columns (41). Redundant data and regular data are multiplexed onto the read global data lines by emitter summing bipolar transistors of regular sense amplifiers (46) with a redundant multiplexer (83). When a redundant column is used to replace a defective regular column, a match circuit (88) generates a match signal for selecting a redundant multiplexer circuit (84, 85, or 86) and for deselecting a corresponding regular sense amplifier (46). The match circuit (88) includes emitter summing circuits (230, 240) to rapidly generate the match signal.

Abstract: There is provided a switch 140 between an address line 121 and external output terminals A0.about.An, controlled by outputs of a counter circuit 117 and a test mode control circuit 119. The switch 140 transfers a variation of an address signal to external output terminals A0.about.An, without connecting the address line 121 with the external address terminals A0.about.An, directly.

Abstract: According to the present invention, a first memory block of the memory chip is placed into the long write test mode, meaning that all wordlines of the first memory block are turned off and the voltages on all the bitlines of the first memory block are controlled such that either all the bitlines true of a memory block are equal to a low logic level, all the bitlines complement of the memory block are equal to the low logic level, or all the bitlines true and bitlines complement of the memory block are both equal to the low logic level. Next, a second memory block of the memory chip is likewise placed into the long write test mode, while the first memory block remains in the long write test mode. After a long pause which causes a long write disturb condition, the memory blocks of the memory chip are one by one taken out of the long write test and read disturbed. Then, the rows of the first memory block are selected, one by one, in minimal cycle time to read disturb the first memory block.

Abstract: When power is turned off during erasure or writing of an EEPROM, electric charge remains on the bit and word selecting lines and on the control line due to the high voltage applied to write or erase data. This charge is discharged through the memory cells when the power is turned on. Erroneous erasure, erroneous writing, and erroneous reading are prevented by including a reset circuit for producing a reset signal when the power is turned on. A bias circuit is connected to the reset circuit for producing a predetermined voltage during the period of the reset signal. A driver circuit receptive of the reset signal selects and drives all word lines with the predetermined voltage during the period of the reset signal, and discharging circuits are provided for electrically discharging all control lines and all bit lines during the period of the reset signal. When the device is turned on, the reset signal is generated, thereby discharging the bit lines and control lines.

Abstract: A sense amplifier circuit includes a differential input circuit which receives first and second data inputs, din1and din2, and generates, in response to a first control signal .PHI..sub.1 being active LOW, a differential voltage across first and second nodes, which is indicative of a voltage difference between the first and second data inputs, din1 and din2; a pull-up circuit which connects, in response to a second control signal .PHI..sub.2 being active LOW, a high voltage reference Vdd to both the first and second nodes; a latching circuit which generates and latches, in response to voltages provided on the first and second nodes by the differential input and pull-up circuits, first and second latched data outputs; and an equalization circuit which equalizes, in response to a third control signal .PHI..sub.0 being active LOW, voltages on data lines respectively connected to the first and second data outputs. Timing of the first and second control signals, .PHI..sub.1 and .PHI..sub.

Abstract: A column start signal generation circuit for a memory device, comprising a dummy data storage unit including a plurality of dummy cells for storing dummy data, each of the plurality of dummy cells being connected to a corresponding one of a plurality of word lines and a first dummy bit line or a second dummy bit line, the second dummy bit line being complementary to the first dummy bit line, a dummy data generator for outputting the dummy data to the plurality of dummy cells in the dummy data storage unit in response to a state of a write signal inputted therein, a sense amplification circuit for amplifying the dummy data from one of the plurality of dummy cells in the dummy data storage unit connected to an enabled one of the plurality of word lines, and a sense amplification sensor for sensing a level of an output signal from the sense amplification circuit and outputting a column start signal in accordance with the sensed result.

Abstract: A semiconductor integrated circuit for controlling a power source with which a power source potential on the basis of different external power source potentials, for example, 5 V and 3 V, can accurately be obtained. The semiconductor integrated circuit for switching between an external power source and a backup power source has an arrangement that, when the external power source potential is supplied to an external power source potential node, the potential at a first connection node on the basis of the external power source potential and a first reference potential of a first reference potential generating circuit are subjected to a comparison by a first comparator, and a first power source potential discriminating portion transmits a first comparison result signal.

Abstract: In order to access several pieces of information concurrently, computers can make use of multi-port access memories. This invention introduces a circuit for a memory system that can be used in such applications. Dual-ported memory access is achieved without duplication of the memory arrays or of the word and bit lines used in the circuit. The circuit allows concurrent read and/or write operations by controlling access to independently controlled sections of the word lines in a memory array and is useful for dual ported data caches. In instruction cache memory applications, the circuitry can be used to allow concurrent access to a number of multiple words. The total number of words accessed concurrently is equal to the total cache width and is independent of the address of the lowest word being accessed.

Abstract: A semiconductor memory, particularly a sychronous DRAM which includes a bus driving circuit driving read/write buses to first and second potentials in a write operation, a data amplifier driving the read/write buses to third and fourth potentials in a read operation, and a precharge control circuit precharging the data read/write buses to a precharge level to a predetermined level after the write operation has completed.

Abstract: The invention provides a chemical mixture device that avoids the mixing of large batches of chemicals and provides a continuous and precisely mixed mixture. For mixing water and a chemical, a large water tank and a chemical tank supply water and chemicals to first and second mixing tanks. As small batches are mixed in one mixing tank, the mixture is drawn from the other mixing tank.

Abstract: A method for concurrently gathering acoustic and resistivity data for mapping the texture of the sidewall of a borehole using a single imaging tool. The data are sampled, formatted and merged to provide a single composite image of the borehole sidewall.

Abstract: Disclosed is a method for processing geophysical data that have been gathered over irregular topography. According to the method, a datum is established that lies above the highest topographic peak. The data are time-shifted from the surface to the datum using a replacement velocity that is an extrapolation of the underlying formation velocity. The wavefields beneath the surface are forwardly modeled using a modeling velocity substantially equal to zero. Between the surface and the datum, the wavefields are upwardly modeled using the replacement velocity.

Abstract: The present invention provides a method and system for characterizing the sounds of ocean captured by passive sonar listening devices. The present invention accomplishes this by first generating a spectrogram from the received sonar signal. The spectrogram is characterized in terms of textural features and signal processing parameters. The textural features and signal processing parameters are fed into a neural network ensemble that has been trained to favor specific features and/or parameters. The trained neural network ensemble classifies the signal as either Type-I or clutter.

Abstract: A clock generator and interrupt bypass circuit for use in reducing the power consumption of the electrical system in which they are implemented. The clock generator provides module clock signals for sequencing modules within the same electrical system, and is capable of generating those module clock signals when in an active mode, and of not generating those module clock signals when in a stand-by mode. The clock generator is further capable of providing a delay of a predetermined length from a request to enter shut-down mode to actual entry into shut-down mode, allowing time to prepare the electrical system for shut-down mode. The interrupt bypass circuit provides a means of leaving shut-down mode in the event that the relevant interrupt requests have been masked.

Abstract: The present invention relates to a process for producing casings for time pieces and, more particularly, a process for producing casings from disposable metal containers for receiving watch movements and the resulting time pieces.

Abstract: A car loading audio instrument adapted to be used by being connected to a car battery so that an electric power is supplied to the audio instrument and comprising a circuit breaker to break a circuit in a non-reversible manner in accordance with detection of robbery of the car loading audio instrument so that it is prohibited from being operated. A robbery is detected when two power lines supplying power are disconnected from each other.

Abstract: There are provided magnetooptic recording and reproducing method and apparatus of the Curie point writing type in which recording information can be read out by using a magnetic Kerr effect and the overwriting can be performed. At a position away from a laser irradiating section of a magnetooptic recording disk having first to third magnetic layers, there is applied a predetermined magnetic field which can magnetize the third magnetic layer in a uniform perpendicular direction and can magnetize the second magnetic layer in a uniform in-surface direction.

Abstract: A magnetic recording system having a magnetic head and a magnetic-field generating device including a compensation circuit for supplying a current generating a magnetic field to cancel a leakage magnetic field applied to the magnetic recording medium, the leakage field arising from at least one of an actuator magnetically driven to drive the magnetic head and an actuator magnetically driven to focus and track a laser beam on the magneto-optical disk.

Abstract: Text data is arranged into groups. A unique code is assigned to each group. The data is encoded so that the codes represent the groups. The groups and their assigned codes are transmitted to a receiver where they are stored as a table correlating each group to its assigned code. After the table is transmitted, the program and the encoded text data are transmitted to the receiver, preferably in synchronism. At the receiver, the data is decoded from the table and displayed as the program is reproduced.

Abstract: A disc reproducing apparatus for an optical disc on which data is recorded. The reproducing apparatus reproduces data recorded on the disc as reproduced data, and, in response to a user input, performs data retrieval, a process in which the data to be reproduced from the disc is selected. The apparatus comprises a main body section and a display, attached to the main body section, for displaying reproduced data. The main body section includes an optical pickup that provides signals in response to the disc, a signal processing circuit that processes the signals from the optical pickup means to provide reproduced data, a feed motor that moves the optical pickup radially relative to the optical disc, and a feed motor control that controls the feed motor. The main body section also includes a device that rotationally drives the optical disc, and an input device that receives the user input. Finally, the main body section includes a control device that includes a single central processing unit.

Abstract: A subcode R-W channel data de-interleaving and de-scrambling method and apparatus includes the ability to de-interleave and de-scramble the encoded subchannel data without the necessity of storage elements, by dynamically calculating the final location of each byte of data within a packet as it is read from the CD-Rom. A pack counter monitors the pack number of the current byte of data. An index counter monitors the location of the current data within a pack. A subtractor uses the values from the pack counter and the index counter to obtain an input value, a first portion of which is supplied to a first offset generator. A second portion of the subtractor output is used to select a base address. The first offset generator determines the pack number of the current byte of data after the de-interleave process. A second offset generator receives a value from the index counter and generates a corresponding value.