Abstract: The present invention relates to a non-naturally occurring, recombinant equine herpesvirus. The invention also relates to a recombinant equine herpesvirus capable of replication which comprises viral DNA from a species of equine herpesvirus and foreign DNA, the foreign DNA being inserted into the equine herpesviral DNA at a site which is not essential for replication of the equine herpesvirus. The invention also relates to DNA encoding the US2 protein of an equine herpesvirus. The invention relates to homology vectors for producing recombinant equine herpesviruses which produce recombinant equine herpesviruses by inserting foreign DNA into equine herpesviral DNA. The invention further relates to a method of producing a fetal-safe, live recombinant equine herpesvirus.

Abstract: The present invention is directed to an isolated bacteriophage designated .phi.CPG1. The invention is further directed to an isolated DNA molecule encoding bacteriophage .phi.CPG1, or a fragment thereof, a DNA molecule comprising DNA encoding bacteriophage .phi.CPG1 with heterologous DNA inserted therein, or a fragment thereof, and to oligonucleotides consisting essentially of a portion of the DNA molecule encoding .phi.CPG1. The bacteriophage .phi.CPG1 was isolated from Chlamydia psittaci strain Guinea Pig inclusion Conjunctivitis.

Abstract: A material being a dsRNA gene segment coding for the major outer capsid glycoprotein of a rotavirus.

Abstract: The present invention is drawn to isolates of Candida oleophila which are effective for the control of postharvest diseases in fruit and to biocontrol compositions which include such isolates. A method of utilizing the isolates to inhibit pathogens which cause postharvest diseases is also described. The organisms were isolated from the surface of tomato fruit and are useful for the control of a variety of fruit-rot pathogens in a variety of fruits.

Abstract: The method for immobilizing water-soluble bioorganic compounds to capillary-porous carrier comprises application of solutions of water-soluble bioorganic compounds onto a capillary-porous carrier, setting the carrier temperature equal to or below the dew point of the ambient air, keeping the carrier till appearance of water condensate and complete swelling of the carrier, whereupon the carrier surface is coated with a layer of water-immiscible nonluminescent inert oil and is allowed to stand till completion of the chemical reaction of bonding the bioorganic compounds with the carrier.

Abstract: Cell culture substrates comprising dried films of native fibrillar collagen produced by a method in which collagen fibers are hydrolyzed in acid, solubilized, and reformed as gels on porous surfaces under non-physiologic salt conditions to produce large fibers with the striations characteristic of collagen fibers found in vivo. The gels are collapsed onto the porous surfaces by drawing the interfibril fluid out of the gel through the underside of the porous surface and then dried to form films. Dried collagen films made in this manner retain native fibrillar collagen structure and excellent diffusion characteristics. Native fibrillar collagen films produced according to the methods of the invention are useful as cell culture substrates. They have particularly advantageous properties for growth and differentiation of epithelial cells. This effect is synergistically enhanced by addition of butyric acid as a differentiation inducing agent.

Abstract: In a system for processing gases containing carbon dioxide by means of a fluid containing algae, with a reactor vessel that can be illuminated and in which light energy is supplied to the algae, the invention proposes that the reactor vessel be designed as a plane element, with the plane element being made transparent to light on at least one of its two surfaces.

Abstract: Isolated DNA molecules comprising a portion of a human hexokinase gene promoter are disclosed. The molecules comprise promoter and insulin-sensitive transcription regulatory elements. These molecules can be used within methods for detecting insulin-like activity in test substances.

Abstract: A method and kit for growing eucaryotic cells using a hydrolyzate of a protein material containing peptides and free amino acids. The material contains L-glutamine, preferably in an amount of greater than 20 percent by weight. Ninety percent by weight of the mixture is less than 1,000 kD in molecular weight. The free amino acid level is less than 20 percent by weight and the average peptide length is less than 20 amino acids.

Abstract: GUC and GUA ribozymes which cleave HIV RNA are provided. The ribozymes cleave HIV RNA in vitro and in vivo. When the ribozymes are expressed in cells, they inhibit HIV replication in the cells.

Abstract: A method and apparatus for analyzing a sample to determine its mineral composition. The invention combines X-ray diffraction with Fourier transform infrared spectroscopy to provide a complete spectrum including molecular vibrations, probed by FTIR scans and lattice spacing measured by X-ray diffraction in a single representation. This FX spectrum provides a more complete and accurate mineralogy than either of the techniques alone. In addition, new techniques for independent X-ray diffraction analysis and FTIR analysis are described.

Abstract: An analyzer for performing automated assay testing. The analyzer includes a storage and conveyor system for conveying cuvettes to an incubation or processing conveyor, a storage and selection system for test sample containers, a storage and selection system for reagent containers, sample and reagent aspirating and dispensing probes, a separation system for separating bound from unbound tracer or labeled reagent, a detection system and date collection/processing system. All of the subunits of the machine are controlled by a central processing unit to coordinate the activity of all of the subunits of the analyzer. The analyzer is specifically suited for performing heterogeneous binding assay protocols, particularly immunoassays.

Abstract: An apparatus for flow injection analysis is disclosed which comprises: (a) an open flow cell containing an upper cell body, a lower cell body contiguously affixed to the upper cell body, and a cell chamber provided in the upper cell body, the cell chamber having a bottom and a top, wherein the top of the cell chamber is open to an atmosphere; (b) a carrier fluid inlet port provided in a lower portion of the upper cell body and in communication with the cell chamber; (c) a fluid delivery device for introducing a carrier fluid into the cell chamber through the carrier fluid inlet; (d) an over-flow outlet setup in an upper portion of the upper cell body to allow exit of the carrier fluid and thus maintaining a constant fluid volume in the cell chamber; (e) a detector disposed in the lower cell body in such a manner that its detecting surface is placed at the bottom of the cell chamber and and facing upward; and (f) a sample injecting assembly, separated from the inlet port and the fluid delivery device for injec

Abstract: The invention relates to a reaction chamber, which includes a cylindrical vessel, with at one end, at least one inlet or outlet tube or lead-through fitted with a valve for a liquid or gaseous component. The other end of the vessel is open. The reaction chamber further comprises a plunger, which performs a reciprocating movement within the cylindrical vessel in axial direction through the open end of the vessel. The plunger tightens against the inner wall of the cylindrical vessel, and has at least one channel, in substantially axial direction, fitted with a valve or connected to a tube fitted with a valve. The invention relates also to an assay method based on the use of the reaction chamber.

Abstract: A flame based method for analyzing a sample by introducing the sample into a combustible gas mixture, igniting the combustible gas mixture to produce a flame, and detecting a characteristic of the resulting flame to determine the identity and/or concentration of one or more chemical substances in the sample, wherein the combustible gas mixture is generated by water electrolysis. The same method is also utilizable for determining the identity and/or concentration of one or more chemical compounds in the sample. A flame based detector apparatus for analyzing a sample is also described.

Abstract: The present invention provides a biosensor that detects an analyte in a sample by measuring the response of a membrane within which associated ion channels undergo state changes upon interaction between the analyte and the ionic channels. The state change response is detected as result of the change in ionic flow through the membrane.

Abstract: Combinatorial libraries of labeled biochemical compounds and methods for producing such combinatorial libraries comprising the steps of producing labeled individual units, combining at least two of the labeled individual units so as to produce a labeled biochemical compound, and repeating this process at least once so as to produce a combinatorial library of labeled biochemical compounds. Also, methods for determining the conformation of a biochemical compound which comprise producing a combinatorial library of labeled biochemical compounds, contacting the combinatorial library of labeled biochemical compounds with a target receptor molecule so that a selected labeled biochemical compound binds to the target receptor molecule, and determining the conformation of the selected labeled biochemical compound when bound to the receptor molecule.

Abstract: A method and apparatus for determining qualitatively or quantitatively the presence of analyte bound to a separation media without doing a bound/free separation. In the method, the bound fraction is collected in an assay region of a body of liquid which includes the free analyte, and the assay is performed by comparing the radiant-energy response in the assay region to the radiant-energy response in a control region of the body of liquid which is free of bound analyte. The apparatus has a chamber which contains the body of liquid, one or more collection elements and a control element and position in the body of liquid parallel to an opaque wall which has a colliminating slit in registry with each element. Each slit enables sensing of the radiant-energy response from the body of liquid between the slit and its associated elements.

Abstract: Novel quinidine derivatives are provided which can be used in an improved immunoasssay for the detection of quinidine and quinidine metabolites.

Abstract: The present invention relates to a TFT comprising: a cylindrical gate electrode formed on a substrate, a gate electrode insulating film formed on said gate electrode, and a round polysilicon channel layer formed on said gate electrode insulating film, wherein said channel layer covers a predetermined portion of said gate electrode insulating film including the inside wall portion and a part of the upper portion of said cylindrical gate electrode, and a method fabricating thereof. The present invention provides improved characteristics of a TFT by increasing the amount of ON current thereof with maximized channel width while the channel length is maintained at a constant value.

Abstract: Oxygen ion is implanted into a silicon substrate to remain a silicon layer on a surface of the silicon substrate. In this state, a silicon oxide layer is formed under the silicon layer. Silicon oxide particles are formed and remained in the residual silicon layer. While maintaining this state, the silicon substrate is heated to a predetermined temperature not less than 1300.degree. C. Alternatively, the silicon substrate is heated at a high temperature-rise rate to 900.degree.-1100.degree. C., and thereafter is heated at a low temperature-rise rate to the temperature not less than 1300.degree. C. The silicon substrate is held at the predetermined temperature not less than 1300.degree. C. for a predetermined time, whereby crystallinity of the residual silicon layer is restored.

Abstract: In forming a thin film transistor (TFT) having an offset structure or a lightly doped drain (LDD) structure, a blocking material having a lower etching rate than that of a material constructing a gate electrode is formed. By using the blocking material as a mask, a gate electrode material is side-etched selectively to form gate electrodes. The blocking material is processed selectively and remains in a drain region side. Also, an offset region or an LDD region is formed under the blocking material by performing an impurity ion implantation. On the other hand, after the gate electrodes are formed, a resist is added and then light exposure is performed from a source region side using a light blocking material as a mask, so that the resist remains in a drain region side of the gate electrode. Also, by implanting an impurity ion, an offset region or an LDD region is formed in the drain region side.

Abstract: In a nonvolatile memory device and manufacturing method, the device includes cell transistors having sources and drains shared by cell transistors adjacent in a first direction, a floating gate confined to the respective cell transistors, and a control gate shared by cell transistors adjacent in a second direction, first plugged conductive layers formed in a long rod shape in the second direction so that sources of cell transistors adjacent in the second direction are connected with one another, second plugged conductive layers each connected with drains of the respective cell transistors, a common source line formed in a long rod shape in the second direction so as to be connected with the first plugged conductive layers thereon, a pad layer formed so as to be confined to the respective cell transistors on the second plugged conductive layers, and a bit line connected with the pad layer through a contact hole.

Abstract: A metal-to-metal antifuse disposed between two aluminum metallization layers in a CMOS integrated circuit or similar structure includes an antifuse material layer having an aluminum-free conductive link. The aluminum-free link is formed by forming a first barrier metal layer out of TiN having a first thickness, a second barrier metal layer out of TiN having a second thickness which may be less than said first thickness, the first and second barrier metal layers separating the antifuse material layer from first and second electrodes. The antifuse is programmed by applying a voltage potential capable of programming the antifuse across the electrodes with the more positive side of the potential applied to the electrode adjacent the barrier metal layer having the least thickness.

Abstract: A multi-region material structure and process for forming capacitors and interconnect lines for use with integrated circuits provides (1) capacitor first or bottom electrodes comprising a transition-metal nitride; (2) a capacitor dielectric comprising a transition-metal oxide; (3) capacitor second or top electrodes comprising a transition-metal nitride, a metal or multiple conductive layers; (4) one or more levels of interconnect lines; (5) electrical insulation between adjacent regions as required by the application; and (6) bonding between two regions when such bonding is required to achieve strong region-to-region adhesion or to achieve a region-to-region interface that has a low density of electrical defects.

Abstract: A semiconductor device capacitor structure comprises a semiconductor substrate having an impurity diffusion region; an insulating layer formed on the semiconductor substrate and having a contact hole on the impurity diffusion region; a first lower electrode of a half ring type formed on the insulating film along an upper edge of the contact hole; a second lower electrode formed on a surface of the substrate exposed through the contact hole, a wall of the contact hole, and the first lower electrode; a dielectric layer formed on the first and second lower electrodes; and an upper electrode formed on the dielectric layer. This structure increases capacitance, thereby improving the characteristics and reliability of the device.

Abstract: A semiconductor device is supported by a semiconductor body which comprises a substrate, an oxide layer and a weakly doped monocrystalline wafer. Trenches for a dielectrically isolating layer which surrounds a component region are etched in the wafer. A field effect transistor in the component region has two doped wafer-line gate regions, which have been diffused in the component region with the aid of a first mask. Two heavily doped regions are diffused in the component region with the aid of a second mask, these regions forming the source region and the drain region of the transistor. The semiconductor body is easy to produce and is available commercially, which simplifies manufacture of the field effect transistor. Manufacture is also simplified because the configuration of both the component region and the parts of the transistor are determined by the simple choice of masks. The component region is weakly doped and is easy to deplete of charge carriers.

Abstract: A method of growing gallium nitride on a spinel substrate by providing a supporting substrate having a surface, and disposing a plurality of buffer layers on the surface of the supporting substrate. The plurality of buffer layers including a first buffer layer of aluminum oxynitride having a low percentage of mismatch to the spinel substrate. The second buffer layer is disposed on the first buffer layer and includes a plurality of layers of a graded aluminum oxynitride having a low dislocation density. A third buffer layer of aluminum nitride is disposed on the second buffer layer. A fourth buffer layer of gallium nitride is disposed on the third buffer layer. Subsequently, a photonic device structure, such as a laser, LED or detector, an electronic device structure, such as a field effect transistor or modulation doped field effect transistor, or an optical waveguide is fabricated on the fourth buffer layer.

Abstract: A titanium layer is formed by depositing titanium over entire surface of a gate electrode, a P-type silicon substrate, an insulation layer, an oxide layer and so forth. By effecting first RTA (Rapid Thermal Annealing) under nitrogen atmosphere, titanium silicide layer of C49 type structure is formed. At this time, the regions of the titanium layer which are on the oxide layer and the insulation layer and upper part of the region of the titanium layer which is formed on the silicon substrate are reacted with N.sub.2 gas to produce titanium nitride layer. In conjunction therewith, titanium layer on the surface of the insulation layer and the oxide layer is slightly reacted to form titanium silicide thin film. Subsequently, only titanium nitride is selectively removed. Thereafter, under oxygen atmosphere, second RTA is performed at 850.degree. C. for 10 sec. to oxidize the titanium silicide thin film to make it insulative.

Abstract: A semiconductor device assembly having external connections, including power supply connections such as to a power source or ground, is made without resort to bond fingers. Rather, external connections are directly made from a semiconductor die to a conductive layer. The conductive layer is disposed on one surface of a printed wring board and is divided into electrically insulated conductive segments. Each of the conductive segments is connected to an external connection, and includes one or more interconnects that can be directly connected to a semiconductor die. The conductive segments are surrounded by an array of bond fingers which serve to connect the semiconductor die to further external connections, such as signal connections. The present invention is especially advantageous in the fabrication of pin grid array (PGA) and ball grid array (BGA) type integrated circuit packages.

Abstract: A fast economical method for modification or repair of micro-circuit wiring patterns covered by a dielectric using a conducting bridge and focused ion beam technology. A conducting bridge is formed on the dielectric between selected points of the wiring pattern using a mask formed by assembling selectively shaped pieces of a transparent mask material such as plastic. The conducting bridge is formed from a material such as gold, copper, or platinum and has sufficient conductivity for long distances. A focused ion beam is then used to form contact holes in the dielectric thereby exposing selected regions of the wiring pattern for connection to the conducting bridge. Connecting material is then selectively deposited using focussed ion beam assisted chemical vapor deposition to connect the conducting bridge to the appropriate points of the wiring pattern. The length of the connecting material does not exceed about 200 micrometers and thus has adequate conductivity.

Abstract: A method for manufacturing a charge-coupled device in which the resistances of the respective poly-gates are made to be the same to thereby enhance the charge transfer efficiency, is disclosed including the steps of forming a first semiconductor layer on a substrate; implanting an impurity ion having a first concentration on the first semiconductor layer; patterning the first semiconductor layer to form a plurality of first gate electrode lines having a first width and spaced apart by a constant distance; forming a second semiconductor layer on the first gate electrode line and the exposed entire surface of the substrate; implanting an impurity ion having a second concentration on the second semiconductor layer; and patterning the second semiconductor layer to form second gate electrode lines having a second width between the first gate electrode lines.

Abstract: A three-layer BGA package includes a BGA Vss plane disposed between upper and lower BGA package traces, and also includes upper and lower BGA package Vss traces on the outer periphery of the BGA package. Vias electrically and thermally couple the BGA Vss plane to upper and lower BGA package Vss traces. Other vias electrically couple Vdd and IC signals from Vdd and signal traces on the upper and lower surfaces of the BGA package. Solder balls connected to the BGA package lower traces are soldered to matching traces on a system PCB. The periphery Vss traces, vias and solder balls help maintain current flow in the BGA Vss plane. In addition to providing a low impedance current return path (and thus reduced ground bounce and reduced IC signal delay time) for current sunk by an IC within the BGA package, the BGA Vss plane provides heat sinking. A four-layer BGA package further includes a BGA Vdd plane located intermediate the BGA Vss plane and the traces on the lower surface of the BGA package.

Abstract: The present invention is related to a flexible IC layout method utilized for an IC having a plurality of logic gates in a first direction connected with a plurality of logic gates in a second direction wherein each of the logic gates has at least one polysilicon region and each of the logic gates in the first direction has an output serving as an input of a corresponding one of the logic gates in the second direction, which includes a step of forming input terminals for the logic gates by ion implantation. The present invention is flexible because the addition or deduction of the number of the input terminals according to the present invention can be achieved by ion implantation.

Abstract: A method of manufacturing a semiconductor device including the steps of: forming an insulating film on an electrical connection area; forming a contact hole in the insulating film; forming a crystalline semiconductor region in the contact hole; forming a wiring layer covering the contact hole; and selectively implanting ions over the wiring layer by using a resist mask to make the crystalline semiconductor region have a high resistance. A semiconductor device having customized wiring connections can be manufactured in a short term.

Abstract: A test apparatus for determining alignment of an implantation mask in the construction of thin film transistors (TFTs), a method for determining the alignment of an implantation mask employed in the construction of TFTs, and a method for constructing TFTs, employing a test implantation mask for the construction of an implantation region for multiple adjacent TFTs, are provided in which the test implantation mask has a sloped or stepped profile such that the masked area increases as the test implantation mask extends from one TFT to another TFT.

Abstract: To produce a three-dimensional circuit arrangement, a first substrate (1) is thinned, stacked onto a second substrate (2) and fixedly connected to the latter. The first substrate (1) and the second substrate (2) in this case each comprise circuit structures (12, 22) and metallization planes (13, 23). At least one first contact hole (16) and one second contact hole (4) are opened, which reach the metallization plane (13, 23) in the first substrate (1) and second substrate (2), respectively, the second contact hole (4) passing through the first substrate (1). The metallization planes (13, 23) of the two substrates (1, 2) are electrically connected to one another via a conductive layer (7).

Abstract: A capacitor structure of a semiconductor device which includes a semiconductor substrate, a first metal layer formed on the substrate, and a second metal layer formed on the first metal layer. The first metal layer has a nitridation-treated film along its outer surface. A tungsten film having a rugged surface is formed on the entire outer surfaces of the first and second metal layers. Because of the nitridation-treated film along the first layer, the tungsten film will be uniformly distributed along the first and second metals. A thin dielectric film is then formed on the surface of the tungsten, followed by a third metal layer formed on the dielectric film.

Abstract: A retrograde well region, having a buried layer of high conductivity, is formed in a semiconductor substrate. A trench structure is selectively etched in the semiconductor substrate down to a region proximate to or within the buried layer. A conducting local interconnect material is formed within and proximate to the trench structure to electrically connect surface portions of the substrate to the buried layer. The buried layer is used to provide a voltage source to an integrated circuit. In one application, a P-type buried layer provides ground potential or V.sub.SS to a source region of an N-channel FET transistor. In a second application, an N-type buried layer provides supply potential or V.sub.CC to a source of a P-channel FET transistor.

Abstract: A semiconductor device (83)including a transistor (85) with a nonuniformly doped channel region can be formed with a relatively simple process without having to use high dose implants or additional heat cycles. In one embodiment, a polysilicon layer (14) and silicon nitride layer (16) are patterned at the minimum resolution limit. The polysilicon layer is then isotropically etched to form a winged gate structure (32). A selective channel implant step is performed where ions are implanted through at least one of the nitride wings of the winged gate structure (32) but are not implanted through the polysilicon layer (14). Another polysilicon layer (64)is conformally deposited and etched such that the polysilicon (74) does not extend beyond the edges of the nitride wings.

Abstract: The invention relates to a transistor having a ramped gate oxide thickness, a semiconductor device containing the same and a method for making a transistor.

Abstract: A semiconductor structure to prevent gate wrap-around and corner parasitic leakage comprising a semiconductor substrate having a planar surface. A trench is located in the substrate, the trench having a sidewall. An intersection of the trench and the surface forms a corner. A dielectric lines the sidewall of the trench. And, a corner dielectric co-aligned with the corner extends a subminimum dimension distance over the substrate from the corner.

Abstract: The present invention disclosed a structure of a charge storage electrode the and manufacturing method therefor. The present invention features forming initial oxide pattern(s) having viscous property at certain temperatures on a barrier layer as rectangular bar-shaped pattern(s) and applying heat to the oxide pattern(s) to transform the initial oxide pattern(s) to cylindrical oxide pattern(s); depositing polysilicon layer on the cylindrical oxide pattern(s); etching each end of the portions of the polysilicon layer and removing the oxide pattern(s); so as to provide a charge storage electrode structure having at least one conduit(s) which is formed with a polysilicon. The charge storage electrode structure according to the present invention has an increased effective surface area and is manufactured by a relatively simple method facilitating the manufacture of highly integrated semiconductor device.

Abstract: A method for filling a trench within a silicon substrate. There is first provided a silicon substrate having a trench formed therein. There is then oxidized thermally the silicon substrate to form within the trench a thermal silicon oxide trench liner layer. There is then formed upon the thermal silicon oxide trench liner layer a conformal silicon oxide intermediate layer formed through a plasma enhanced chemical vapor deposition (PECVD) method employing a silane silicon source material. Finally, there is then formed upon the conformal silicon oxide intermediate layer a gap filling silicon oxide trench fill layer through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method employing an ozone oxidant and a tetra-ethyl-ortho-silicate (TEOS) silicon source material.

Abstract: A method for making planar metal interconnections and T-shaped metal plugs for integrated circuits is achieved. The method involves forming a planar insulating (SiO.sub.2) and a hard mask film over a first level of interconnections. A patterned first photoresist layer is then formed for etching trenches in the hard mask film and partially into the planar insulating layer (SiO.sub.2) in which a second level of interconnections are to be formed. The patterned photoresist layer is then laterally etched to expose the hard mask adjacent to the trenches in the SiO.sub.2, and the hard mask is then removed adjacent to the trenches to form a self-aligned mask for the metal plug contact openings. A patterned second photoresist mask aligned over the trenches is then used to etch the contact openings in the trenches, using the hard mask to form T-shaped plug contact openings to the first level of interconnections.

Abstract: A method of forming an aluminum-alloy pattern at room temperature, which is capable of eliminating the generation of after-corrosion and enhancing the anisotropic processing. In a first step, an etching mask made of a silicon nitride based film is formed on an aluminum-alloy film formed on a barrier metal layer which is formed on a substrate. In a second step, the aluminum-alloy film is dry-etched at room temperature, to form a pattern of the aluminum-alloy film. The etching selection ratio of the aluminum-alloy film to the etching mask is thus improved, and further a sidewall protective film made of aluminum nitride is formed on the etching sidewall, thereby sufficiently performing the anisotropic processing for the aluminum-alloy pattern. In subsequent steps, the barrier metal layer may also be etched and removed at room temperature, and a further sidewall protective film made of aluminum oxide is formed on the etching sidewall as a result of oxygen plasma processing.

Abstract: A thermoplastic thermoformable composite material for shaping and stretching into a desired form without voids and holes, including a core formed by at least one layer of chopped fibers enveloped and impregnated by thermoplastic material to form a fabric layer. Layers of thermoplastic material respectively positioned on opposite sides of the fabric layer core, and the layers of thermoplastic material provided with a sufficient thickness to flow into and heal any voids or holes formed in the core as the composite material is shaped and stretched into a desired form.

Abstract: Abrasion resistant glass, which consists essentially of the following components:______________________________________ SiO.sub.2 75.5 to 85.5 (wt %), RO 1 to 8 (wt %), R'.sub.2 O 10 to 23.5 (wt %), RO + R'.sub.2 O 11 to 24.5 (wt %), Al.sub.2 O.sub.3 0 to 5 (wt %), ______________________________________ RO/R'.sub.2 O (weight ratio) at most 0.5,provided that R is at least one member selected from Mg and Ca, and R' is at least one member selected from Li, Na and K, and of which the density measured at room temperature is at most 2.41 g/cc.

Abstract: An aluminosilicate glass having a composition comprising, as calculated in weight percent on an oxide basis, of 40-57% SiO.sub.2, 2.0-11% Al.sub.2 O.sub.3, 1-16% CaO, 8-21.5% SrO, 14-31.5% BaO, 0-3% MgO, and 0-4% B.sub.2 O.sub.3, the glass having a temperature not over 1450.degree. C. at a viscosity of 20 MPa.multidot.s (200 poises), a CTE of 60-90.times.10.sup.-7 /.degree. C. and a strain point over 630.degree. C.

Abstract: A novel ceramic substrate useful for the preparation of superconductors, said substrate having the formula Ba.sub.2 DyMO.sub.5.5 where M represents at least one of the metals Zr, Sn and Hf and a process for the preparation of said ceramic substrate, which comprises (i)Reacting salts of dysprosium, barium and Zr, Sn or Hf in an organic medium, (ii) Pressing the resultant mixture in the form of pellets, (iii)Calcining the pellets by heating at a temperature in the range of 1000.degree. to 1200.degree. C., (iv)Repeating the calcination process for 30-45 h at temperature in the range of 1000.degree.-1200.degree. C. until a highly homogenous mixture is formed, (v)Grinding the calcined material and pelletizing at a pressure in the range of 3 to 4 tons/cm.sup.2, (vi) Sintering the resultant product at a temperature in the range of 1200.degree. to 1600.degree. C. for a period of 10 to 30 h, and then furnace cooled to room temperature.