Abstract: A computer system operable on a DC voltage is provided. The computer system includes a microprocessor, a system memory coupled to the microprocessor, a bus coupled to the microprocessor, an input device coupled to the bus, and a voltage adapter system for providing a DC voltage to the computer system. The voltage adapter system includes a voltage modifying device adapted for converting an AC voltage to a DC voltage. A first cable assembly is electrically connected to supply the AC voltage from an AC power supply to the voltage modifying device. A second cable assembly is provided for selectively supplying the DC voltage to the system from the voltage modifying device or from a remote DC voltage power supply. The second cable assembly is connectable at a first end to the system and connectable at a second end to the voltage modifying device and to the remote DC voltage power supply.

Abstract: Military vehicles often provide power to operate chargers to charge portable rechargeable batteries in the field. The military uses a NATO standardized DC slave plug as a connection from the vehicle battery to external charger devices. The NATO standardized DC slave plug is directly connected to the vehicle battery and offers no electrical protection to the vehicle battery. This method employs a battery charger adapter providing controlled DC power from the vehicle battery to charger devices for recharging Army communication batteries. The battery charger adapter is connected between the NATO standardized DC slave plug and an external charger and includes an electromechanical relay acting as an automatic safety switch which cuts off the load on the vehicle battery when the battery voltage falls to a predetermined critical voltage level, to prevent over-discharge of the vehicle battery.

Abstract: A memory device which includes intermediate storage, or cache, and unidirectional data paths coupling the intermediate storage to external input/output. The invention improves the response of the memory device by eliminating dual latencies associated with the transition from a write request to a read request. The method of use of the invention and systems incorporating the invention are further described.

Abstract: A three state, dual port CAM cell responsive to three combinations, i.e., 0,0 and 1,0 and 0,1, of two binary inputs includes a pair of latches, each having a pair of inverters connected in a regenerative feedback circuit. For the 0,0 combination, a driver and FET disable the second inverter in such a way that output tenninals of the latches supply 0,0 to a pair of data lines. For the 1,0 combination, both inverters of both latches are enabled, causing the latches to supply the data lines with 1,0. For the 0,1 combination, the second inverter is disabled in such a way that the output terminals of the latches supply the data lines with 0,1.

Abstract: There is a memory module for use in conjunction with high speed, impedance-controlled buses. Each memory card may be a conventional printed circuit card with memory chips attached directly to the card. Alternately, high density memory modules assembled from pluggable sub-modules may be used. These sub-modules may be temporarily assembled for testing and/or burn-in. Bus terminations mounted directly on the memory card or the memory module eliminate the need for bus exit connections, allowing the freed up connection capacity to be used to address additional memory capacity on the module. An innovative pin-in-hole contact system is used both to connect sub-modules to the memory module and, optionally, to connect the memory module to a mother board or similar structure. A thermal control structure may be placed in the memory module to cool the increased number of memory chips to prevent excess heat build-up and ensure reliable memory operation.

Abstract: An integrated circuit device such as an integrated circuit memory device, includes a first fuse group such as a first laser fuse group including a plurality of first laser fuses each having a first narrow end, a second opposite end which is wider and a bent central portion. Pitches of the first end of the plurality of first laser fuses are narrow and pitches of the second end are wide. The plurality of first laser fuses are adjacent one another. A second fuse group such as a second laser fuse group includes a plurality of second laser fuses each having a first wide end, a second opposite end which is narrower, and a bent central portion. Pitches of the first end of the plurality of second laser fuses are wide and pitches of the second end are narrow. The second plurality of laser fuses are adjacent one another. The first ends of the laser fuses in the first laser fuse group are adjacent the first ends of laser fuses in the second laser fuse group.

Abstract: As a ferroelectric memory cell arrangement, one terminal of a ferroelectric capacitor is connected to a word line. This eliminates a plate line that is conventionally necessary and enables write and read by controlling only a word line and a bit line. No need for a driver circuit for driving a plate line facilitates control of write and read operations and design of control line potential timings. This reduces the circuit scale and the chip size.

Abstract: Trench capacitors are arranged in the form of a matrix at a constant pitch in row directions while being sequentially shifted between adjacent rows by a predetermined pitch. An element isolating insulator film is formed so as to surround active regions, each of which is adjacent to adjacent two capacitors in row directions, together with a partial region of the two capacitors. Transistors, which have gate electrodes continuously formed as word lines, are formed so as to be adjacent to the respective capacitors. One of the source and drain diffusion layers is connected to the capacitor node layer of a corresponding one of the capacitors via a connecting conductor. The other of the source and drain diffusion layers serves as a bit line contact layer shared by adjacent two transistors in the row directions, so that bit lines connected to the respective bit line contact layers in the row directions are formed. Three word lines are provided between adjacent bit line contact layers.

Abstract: A 4-T SRAM cell includes access transistors of a first type and cell (pull-up or pull-down) transistors of a second type. For example, the cell includes PMOS access transistors and NMOS pull-down transistors. The cell may also include leaky-junction or Schottky loads.

Abstract: A random access memory cell includes a forward inverter and a feedback inverter connected to the forward inverter. The feedback inverter includes a ground access transistor configured to selectively connect and isolate the feedback inverter to ground. The ground access transistor is isolated from ground in response to a first digital state global clear signal generated during a global clear state. A set of random access memory cells are simultaneously programmed to store identical values in response to the first digital state global clear signal during the global clear state. The ground access transistor is connected to ground in response to a second digital state global clear signal generated during a programming state. Selected random access memory cells are programmed to store selected values in response to the second digital state global clear signal during the programming state.

Abstract: Described is an SRAM cell made from two cross-coupled inverters. The output from each inverter is a data node, and the two data nodes store logical complementary signals. Each data node is connected to a pass transistor that is coupled directly to the power supply voltage, rather than coupled to a pair of bitlines. The inverters can be connected to a reading circuit, a writing circuit, or a stand-by circuit as desired for different phases of the memory operation. Data is read from the SRAM cell by using a current sensing differential amplifier. Data is written to the SRAM cell by controlling voltages on the cross-coupled inverters, and compatible with conventional writing signals.

Abstract: A non-volatile random access memory (NVRAM) of the type with magnetoresistive memory elements (1) connected by sets of non-intersecting conductor sense lines (3, 4) which define the address of each memory element (1) and are connectable to a magnetic write/read recording unit. The memory elements are a plurality of magnetoresistive submicron dots or wires (1) embedded in a membrane (2) through which the submicron dots or wires extend. The sets of non-intersecting conductor sense lines (3, 4) are connected to the opposite ends of the submicron dots or wires (1) on opposite sides of the membrane.

Abstract: A hybrid device includes a magnetoresistance (MR) element, a resistor connected in series to an end of the MR element, and a field effect transistor (FET) having its gate electrode connected to the connection point of the MR element and the resistor. The hybrid device constitutes an essential part of a memory apparatus, in which the other end of the MR element and the drain electrode of the FET are grounded, a voltage source is provided for applying a predetermined voltage to the MR element, and a second voltage source or a current source is provided for flowing a drain current in the FET. The memory apparatus can record information by utilizing two different states of the resistance of the MR element. The FET functions both as an switching element for writing/reading information and an amplifying element for boosting the resistance difference. The memory apparatus may comprise a plurality of hybrid devices wired so as to form an XY-matrix pattern.

Abstract: A magnetic memory cell with symmetric switching characteristics includes a sense layer and a reference layer coupled to the sense layer through a barrier layer. The magnetic memory cell further includes an additional reference layer coupled to the sense layer through a spacer layer. The additional reference layer is formed so that a set of demagnetization and coupling fields from the additional reference layer balance a set of demagnetization and coupling fields from the reference layer.

Abstract: A method of operating a semiconductor device that includes a first memory cell with discontinuous storage elements or dots (108) in lieu of a conventional floating gate can be programmed to at least one of three different states. The different states are possible because the read current for the memory cell is different when the dots are programmed near the source region or near the drain region. Embodiments may use two different potentials for power supplies or three different potentials. The two-potential embodiment simplifies the design, whereas the three-potential embodiment has a reduced risk of disturb problems in adjacent unselected memory cells (100B, 100C, and 100D).

Abstract: In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored.

Abstract: According to one embodiment, a nonvolatile storage circuit (100) can include a volatile portion (102) that includes p-channel metal-oxide-semiconductor (MOS) transistors (106-0 and 106-1) and n-channel MOS (NMOS) transistors (108-0 and 108-1) arranged in a complementary MOS (CMOS) latch configuration. Also included are nonvolatile devices (116-0 and 116-1) disposed between PMOS transistor 106-0 and NMOS transistor 108-0, and between PMOS transistor 106-1 and NMOS transistor 108-1. Nonvolatile devices (116-0 and 116-1) can include silicon-oxide-nitride-semiconductor (SONOS) transistors that can be programmed to opposite states to recall a logic value when power is applied to the nonvolatile storage circuit (100). In a read mode, a bias voltage VBIAS can be applied to nonvolatile devices (116-0 and 116-1) that tends to retain charge in both nonvolatile devices (116-0 and 116-1).

Abstract: In order to optimize writing of the cell, the latter is written in a condition of equilibrium between an injection current Ig and the displacement current CppVsl. In this way, during writing, the voltage of the floating gate region Vfl remains constant, as does the drain current and the rise in the threshold voltage. In particular, both for programming and for soft-writing after erasure, the substrate of the cell is biased at a negative voltage Vsb with respect to the source region, and the control gate region of the cell receives a ramp voltage Vcg with a selected predetermined inclination Vsl satisfying an equilibrium condition Vsl<Ig,sat/Cpp.

Abstract: A method to tighten the threshold voltage distribution curve in a memory device composed of multiple memory cells organized in rows and columns by soft programming each memory cell. Soft programming voltages that utilize the hot-carrier mechanism are selected and are applied sequentially to memory cells in wordlines. The soft programming voltages include a ramped voltage VGS of <3 volts, a VDS of <5 volts and a Vsub of <0 volts. The soft programming voltages are applied for a time period of <10 microseconds. The VT distribution is reduced to a maximum width of <2 volts. The soft programming is applied to the memory cells after the memory cells have been verified as having been erased and a having been overerase corrected.

Abstract: The present invention disclosed the test cell and method of analyzing using the same which can analysis the cause of degradation of flash EEPROM cell in connection with programming, erasing or reading operation. The test cell comprises a first unit cell consisted of a drain, a source and a floating gate, a control gate; a second unit cell consisted of a drain, a source and a floating gate, control gate formed integrally with the floating gate and control gate of the first unit cell, respectively; and a third unit cell consisted of a drain, a source and a floating gate, a control gate formed integrally with the floating gate and control gate of the first unit cell, respectively.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Abstract: A virtual ground type array has a number of electrically data-programmable, erasable memory cells, arranged matrix-wise in rows and columns. A multiple number of row lines are each connecting the control gates of memory cells located in one row and a multiple number of column lines are each commonly connecting the drain and source of memory cells constituting columns. The memory cells are programmed sequentially in the order of degree of the difference in charge amount in the floating gate from the erased state (data‘00’).

Abstract: A method for fast programming by tunnel effect a floating gate memory cell having a floating gate region separated from a substrate region by a gate oxide layer, wherein an electric field of at least 10 MV/cm is applied to the gate oxide layer for a programming time less than or equal to 100 ns, for example in the range between 20 and 100 ns, and in one embodiment preferably of approximately 50 ns. The gate oxide layer is preferably less than 10 nm. With the foregoing, floating gate memory cells operating as single level or multilevel RAM cells, of a static or dynamic type, or as flash or EEPROM cells, can be obtained where the programming time is substantially reduced.

Abstract: A method for sensing the state of erasure of a flash (EEPROM) memory device. In one embodiment, the source voltage during erase is monitored and compared to a value determined during a characterization procedure. In a second embodiment, the rate of change of the source voltage during erase is determined and compared to a value determined during a characterization procedure. The characterization procedure correlates state of erasure with source voltages and slopes of the rate of change of source voltage versus time curve for the memory cells. The determination of the source voltage and the determination of the rate of change of the source voltage and the associated state of erasure allows modification of the erase procedure.

Abstract: A unified erase method used in an array of flash EEPROM memory cells arranged in a plurality of sectors for performing either a single-sector, multiple-sector, or all-sector erasing operation with a reduced amount of total erase time and a uniform VT distribution as good as that of a single-sector erase operation is provided. An erase-verify operation is performed sequentially on the plurality of sectors from a first sector to a last sector beginning with a first address of each sector if its corresponding erase-on signal is not turned OFF. The current address of each sector is stored at a point where the erase-verify operation failed. An erase pulse is applied only to all sectors simultaneously that have not passed the erase-verify operation. The erase-verify operation is then repeated beginning at the current address stored. The erasing operation is terminated when the erase-on signal has been turned OFF in all sectors in the plurality of sectors.

Abstract: A memory cell array includes a normal memory cell array divided into a plurality of memory blocks, a row redundant circuit and a column redundant circuit. Independent data lines are provided for the normal memory cell array, the row redundant circuit and the column redundant circuit, respectively. A data line shift circuit selectively connects each data I/O line to a global data bus. A redundant control circuit generates a shift setting signal corresponding to the defective address for setting a connection form in a data line shift circuit when an address signal matches with a defective address.

Abstract: A semiconductor memory device having nonvolatile memory cells arranged in matrix comprises and bit lines connected to drains of the memory cells. Latches provided for the respective bit lines or in the ratio of one latch to a number of bit lines, as are; transfer gates for electrically separating the respective latches from the bit lines. The device also having bit line voltage detection circuits for detecting voltages of the respective bit lines and latch reset circuits for inverting data stored in the respective latches in accordance with the outputs from the bit line voltage detection circuits. Therefore, data stored in each latch can be rewritten even by a very small memory cell current, resulting in stable program verify.

Abstract: A current mirror-type load circuit is provided for a global data line pair. A read gate amplifier used as a block select gate for each of the local data line pairs. A read gate amplifier includes a MOS transistor having its gate connected to a corresponding local data line. A data write driver writes the logic-inverted data of the write data upon equalization after the data write operation. A high-speed access becomes possible by reducing the time required for reading of data and by reducing the write recovery time.

Abstract: The operating speed and stability of a semiconductor memory device of the type performing reading and writing at regular intervals are improved. A read/write pulse width controller varies the pulse width of a read/write pulse width control signal in such a manner that the width during reading is shorter than that during writing. A column decoder outputs a column-select signal having a pulse width equal to that of the read/write pulse width control signal. And a column-select gate connects an associated pair of bit lines to a pair of data lines while the column-select signal is high. During reading, a sufficiently long time can be allotted for equalizing potentials on the data lines. On the other hand, during writing, plenty of time can be allowed for connecting a pair of data lines to the pair of bit line. As a result, reading and writing can be performed stably enough at a sufficiently high speed.

Abstract: A data transfer circuit for read data operations in a memory circuit employs a two-stage bit switch. True and compliment bit lines from a memory cell array are coupled to gates of a pair of transistors in a first stage bit switch. The data from the bit lines is thus transferred to a pair of read data nodes without a DC connection, so charge-sharing is avoided. Also, this allows the data to be extracted without a full logic-level swing of the bit lines, so faster operation is provided. The data from the data nodes is transferred to a pair of data lines through a second-stage bit switch activated by a timing input. The differential voltage on the bit lines is enhanced by a sense amplifier, and, also, the use of the first-stage bit switch allows the bit lines to be precharged to only half the logic level, speeding up operation; this sense amplifier is activated before the timing input for the second-stage bit switch.

Abstract: The present invention relates to a column redundancy circuit for a semiconductor memory which can facilitate a high integration semiconductor circuit whose memory array is divided into a plurality of array units to be properly operated at a high frequency. The plurality of array units in the memory array include a plurality of normal memory cells and a plurality of redundancy memory cells. The redundancy data stored in the redundancy memory cells are outputted to a first main amplifier, and the normal data stored in the normal memory cells are outputted to a second main amplifier. A column redundancy unit outputs a redundancy enable signal according to a column address, a row address and a fuse short state. According to the logical state of the redundancy enable signal, the switch unit selects the redundancy data from the first main amplifier or the normal data from the second amplifier, and outputs it to a data output buffer.

Abstract: In a semiconductor memory device, a memory cell array 108 and a GND selector circuit 107 arranged in the vicinity of the memory cell array are connected via a metal wiring. In the GND selector circuit 107, a single transistor is connected to a single line of the metal wiring. A GND selecting transistor in the GND selector circuit 107 is also used as a precharge selecting transistor. The memory cell array 108 and a Y selector circuit 110 arranged in the vicinity of the memory cell array are connected via a digit line. In the Y selector circuit 110, a single digit-selecting transistor is connected to a single digit line. The digit-selecting transistor is also used as a precharge selecting transistor.

Abstract: A method and apparatus for programmable read only memory with high speed differential sensing at low operating voltage. In one embodiment, a programmable memory cell is comprised of word line, a bitline, and a transistor. The transistor, representing a single binary digit (bit), has a gate coupled to a word line, a drain coupled to a bitline, and a source capable of being programmed to provide a logic level of 0 and a logic level of 1. By programming the source of the transistor, the bitline approximately equal capacitance for both logic level 0 and logic level 1 states.

Abstract: A circuit for a sense amplifier (14) for use with a memory device (10). The circuit includes two devices (40 and 42) that are controlled by a selector (44). The first device (40) drives the sense amplifier (14) with a first current level. The second device (42) drives the sense amplifier (14) with a second current level, different from the first current level. The selector (44) is coupled to the first and second devices (40 and 42) so as to selectively couple one of the first and second devices (40 and 42) to the sense amplifier (14) based on a power supply voltage of the memory device (10).

Abstract: A circuit for generating timing signals for clocking the sensing amplifiers of a SRAM memory array having a plurality of memory cells joined in rows by wordlines and in columns by bitlines including a dummy bitline, a plurality of dummy memory cells joined to the dummy bit column, means for accessing a plurality of the dummy memory cells in parallel to generate a bitline charging current significantly greater than a bitline charging current in a typical operative column of the SRAM memory array, a circuit responsive to current in the dummy bitline for generating a timing signal to sense amplifiers for generating output signals from the operative columns of the SRAM.

Abstract: An optical memory 200 including an optical storage element 301 for storing data as a packet of photons, optical storage element 301 delaying in time the packet of photons traveling through the storage element from a first point to a second point. A photon source 302 receives an electrical signal representing data and injects the packet on to optical storage element 301 in response, and a detector 303 selectively detects the packet traveling on optical storage element 301. A feedback path 306/305 couples photon source 302 and detector 303 for recirculating the packet through storage element 301.

Abstract: An integrated circuit first-in, first-out (“FIFO”) memory device comprises an input bus for receiving data, an input buffer coupled to the input bus for storing the data and at least one dynamic random access memory (“DRAM”) array coupled to the input buffer. A write pointer is operative for storing the data in the input buffer to a location within the memory array indicated and an output bus is coupled to the memory array and a read pointer for providing previously written data from the memory array at a location indicated by the read pointer. In a preferred embodiment, the FIFO further comprises at least one static random access memory (“SRAM”) row, or register, interposed between the input and output buses and the memory array having a width corresponding to each row of the memory array.

Abstract: A semiconductor memory device includes a logic unit, a DRAM unit, and first and second PMOS transistors. In a normal mode, the first PMOS transistor is off and the second PMOS transistor is on, whereby power supply voltage is supplied to all the circuits. In a power down mode, the first PMOS transistor is on and the second PMOS transistor is off, so that power is not supplied to circuitry that is not required for a self refresh operation. Power supply voltage is provided to circuitry that is required for a self refresh operation. Thus, current consumption during self refresh can be reduced.

Abstract: An integrated circuit includes a first conductive layer, an insulator layer disposed on the first conductive layer, and a second conductive layer disposed on the insulator layer. A first fuse is disposed in the first conductive layer and provides a first signal, and a second fuse is disposed in the second conductive layer in alignment with the first fuse and provides a second signal.

Abstract: A NAND EEPROM is disclosed which is capable of variously setting, for each chip, the voltage to be applied to the control gates of memory cells. The semiconductor chip includes a NAND memory cell array and a high-voltage generating circuit for generating data writing internal voltage VPP required when data is written on the memory cell array. Moreover, the semiconductor chip includes a set voltage selection circuit for arbitrarily setting the level of the voltage VPP generated by the high-voltage generating circuit for each chip and a multiplexer for extracting, to the outside of the chip, setting signal LTF which is a signal for enabling the level of the voltage VPP set arbitrarily.

Abstract: A semiconductor memory device with multi-bank structure, includes multiple voltage boosting circuits or internal power supply voltage generating circuits, each of which generates a high voltage to be provided to a bank. The respective voltage boosting circuits or internal power supply voltage generating circuits are sequentially selected under the control of a select signal generating circuit which generates select signals corresponding to the voltage boosting circuits by use of a row address strobe signal. According to the above-mentioned configuration, the number of the voltage boosting circuits is less than the number of banks in the memory device. Therefore, the area that the voltage boosting circuits or internal power supply voltage generating circuits occupy on a chip does not increase in proportion to the increase in the number of banks.

Abstract: An on-chip voltage generating device for semiconductor memory which generates a higher voltage than a power supply voltage or a lower voltage than a ground voltage is provided. The on-chip voltage generating device comprises an on-chip voltage generater for outputting the on-chip voltage by a pumping operation, an on-chip voltage detector for receiving the on-chip voltage, the on-chip voltage detector detecting the voltage level of the on-chip voltage and controlling the operation of the on-chip voltage generater; and an oscillator for controlling an operation of the on-chip voltage detector.

Abstract: The present invention provides a memory system that retrieves data based upon redundant form address data. The memory system includes a memory having a plurality of memory lines and an address decoder that enables one of the memory lines in response to a redundant form address signal. A redundant form decoder decodes redundant form data into a differential pair of decoded address lines for each bit position of a memory address. One of the two differential pairs carries correct address data. The one address line to be used is determined on a memory line by memory line basis, using the address of the memory lines themselves. The redundant form address decoder avoids a completion add that would otherwise be required, yielding very fast access to memory.

Abstract: A semiconductor memory device which prevents a sub word line from being incorrectly selected when a main word line breaks. A plurality of memory cells are connected to a main word decoder each via the main word line, a sub word decoder, and a sub word line. A plurality of redundant memory cells are connected to a redundant fuse circuit each via a redundant main word line, a redundant sub word decoder, and a redundant sub word line. A connection between the main word line and the sub word decoder and a connection between the redundant main word line and the redundant sub word decoder are each grounded by a high-resistance resistor.

Abstract: A synchronous semiconductor memory device has improved layout and circuitry so as to provide rapid operation. Data paths between sub-arrays and memory cells and corresponding DQ pads are equalized to provide approximately equal line delays, transmission losses, etc. Input clock circuitry converts a “asynchronous” external clock signal and external clock enable signal to an internal “synchronous” clock signal. Input command signals are not stored in input registers, but instead are latched so as to provide such input signals rapidly downstream. Multiple redundant compare circuitry is provided to improve delays inherent in selecting between external or internal addresses. Input/output pull up circuitry is enabled during both read and write operations, but shortened during write operations. Two or more voltage pump circuits are employed that permit sharing of power therebetween to compensate for increased power demands to row lines, data output lines, etc.

Abstract: The present invention comprises a flash memory or similar nonvolatile memory circuit characterized by a constitution that enables read operations in two modes, a clock-synchronous burst read mode and a clock-asynchronous normal read mode, the device being set to normal read mode in response to power on, and being set to burst read mode in response to a control signal instructing the burst read mode. The memory device includes a burst mode switching circuit internally. This burst mode switching circuit sets an output circuit to normal read mode in response to the power ON so as to enable read operations not synchronized with the clock after the power ON. In response to a burst mode control signal provided by the system, the burst mode switching circuit sets the output circuit to burst read mode. Thus, the system can perform the burst read to the nonvolatile memory device under the environment analogous to conventional main memory access.

Abstract: A multiple synthesizer based timing signal generation scheme is described that allows accurate data and strobe generation in high speed source synchronous system interfaces. Multiple loop locked clock synthesizers (e.g., phase locked loops, delay locked loops) are used to generate multiple clock signals. Data and strobe signals are triggered off of transitions of one of the clock signals. Because multiple loop locked clock synthesizers are used to generate the clock signals, optimal or near optimal alignment of the data and strobe signals can be achieved. Improved alignment of the data and strobe signals provides improved data transmission rates.

Abstract: An electronic instrument includes a memory device, clock lines through which complementary clock signals are transmitted to be used for synchronization of a data output operation and a data input operation for the memory device, and strobe signal lines through which a first output strobe signal, a second output strobe signal, a first input strobe signal and a second input strobe signal are transmitted to be used to settle output data from the memory device in the data output operation and to settle input data supplied to the memory device, the first and second output strobe signals being in complementary relation to each other, the first and second input strobe signals being in complementary relation to each other.

Abstract: A digital transmit beamformer system with multiple beam transmit capability has a plurality of multi-channel transmitters, each channel with a source of sampled, complex-valued initial waveform information representative of the ultimate desired waveform to be applied to one or more corresponding transducer elements for each beam. Each multi-channel transmitter applies beamformation delays and apodization to each channel's respective initial waveform information digitally, digitally modulates the information by a carrier frequency, and interpolates the information to the DAC sample rate for conversion to an analog signal and application to the associated transducer element(s). The beamformer transmitters can be programmed per channel and per beam with carrier frequency, delay, apodization and calibration values. For pulsed wave operation, pulse waveform parameters can be specified to the beamformer transmitters on a per firing basis, without degrading the scan frame rate to non-useful diagnostic levels.

Abstract: Acoustic intensity is measured by a submerged probe consisting of two passive geophones mounted in spaced relationship with their sensing axes aligned. The geophones are connected through a cable to a remote spectrum analyzer in which acoustic intensity is computed from the velocity gradient between the two geophones. The exclusive use of geophones, which inherently have low impedance outputs, eliminates the need for preamplification in the probe. The geophones are mounted inside an acoustically transparent, thin rubber shell, which reduces the effects of noise due to flow.