Abstract: A computer system with an Intelligent Input/Output architecture having a plug-and-play control mechanism for assigning and controlling one or more adapters. The computer system comprises at least one host processor for executing a host operating system, the host processor disposed on a host bus, an input/output (I/O) bus operably coupled to the host bus via a host-to-bus bridge, and a plurality of peripheral devices or adapters operably connected to the I/O bus for transferring data in I/O transactions controlled by an IOP resource. Initially, a selected adapter is defaulted to an “assigned” state without changing the interrupt routing associated with the adapter. Upon detecting the presence of a driver module that is executable on the IOP, the assigned adapter is marked as “controlled” and the interrupt routing is configured to deliver interrupts to the IOP. Subsequently, the controlled adapter is rendered “hidden” from the host operating system.

Abstract: A computer is coupled via a bus to a peripheral device. The peripheral device includes an I/O device portion placed on a single microchip coupled to a process device portion. The I/O device portion includes a physical layer in communication with the computer, and a data channel processor in communication with peripheral device. A single oscillator controls the speed of both of these components, and each component includes a dedicated frequency divider. The process device portion may be hardware, software or hardware and software, and may be implemented on a single chip or on multiple chips. To reduce pin count, interface controllers may be used to communicate between the I/O device portion and the process device portion across a single channel.

Abstract: Data processing apparatus is described comprising a processor and at least one peripheral device. The processor is arranged to service the peripheral device either in an interrupt mode in which the peripheral device is serviced in response to interrupt signals generated by the peripheral device or in a timed mode in which the peripheral device is periodically polled and serviced if required. The apparatus has a dynamic switching arrangement for switching from the interrupt mode to the timed mode depending upon conditions dynamically determined within the apparatus, at least one of said conditions being that the rate at which the peripheral device generates interrupt signals exceeds a predefined or programmable threshold frequency. The rate of polling in the timed mode is less than the threshold frequency.

Abstract: Disclosed is a SCSI host adapter for use in a computer system. The SCSI host adapter is configured to provide the computer system with interconnection with internal and/or external target devices. The SCSI host adapter includes a low voltage differential connector for interconnecting to a low voltage differential bus, and the low voltage differential bus is configured to communicate a first transaction. The SCSI host adapter also includes a single ended connector for interconnecting to a single ended bus, and the single ended bus is configured to communicate a second transaction. Furthermore, the SCSI host adapter includes a transceiver unit that is configured to interface between the low voltage differential bus and the single ended bus and produce a target information signal. The target information signal is configured to indicate whether the first transaction or the second transaction is occurring between the SCSI host adapter and the low voltage differential bus or the single ended bus.

Abstract: A method and apparatus for levelizing transfer delays for a channel of devices. One method described determines a controller delay value by iteratively testing memory transfers to determine a largest transfer latency value using a subset of all available delays for at least one of a plurality of memory devices. Additionally, a memory device delay value for each of the plurality of memory devices is determined by testing memory transfers using at least one delay value for each of the plurality of memory devices.

Abstract: A software architecture for the hot add and swap of adapters. The software architecture allows users to replace failed components, upgrade outdated components, and add new functionality, such as new network interfaces, disk interface adapters and storage, without impacting existing users. The software architecture supports the hot add and swap of off-the-shelf adapters, including those adapters that are programmable.

Abstract: The process and arrangement enable the target-oriented and thereby collision-free transmission of data (addressing and useful data) via a synchronous system bus (SBsyn) in a microprocessor system (&mgr;PS), given data accesses of a microprocessor (&mgr;P) of the microprocessor system (&mgr;PS) to peripheral apparatuses (SP, DAC, AE) of the microprocessor (e.g. a memory, a digital-analog circuit, a display) that are system-compatible and system-incompatible with respect to data transmission protocols (e.g. I2C protocol). A control signal (SS), e.g. fashioned as a chip select signal, is transmitted on a separate control line (SL) between the microprocessor (&mgr;P) and the system-incompatible apparatus (AE) for the selection of the system-compatible and system-incompatible peripheral apparatuses (SP, DAC, AE) of the microprocessor (&mgr;P). Free addresses are respectively assigned to the system-compatible and the system-incompatible apparatuses (SP, DAC, AE).

Abstract: Asynchronous and isochronous data is transferred over a bus connecting a first device and a second device. Data is selectably transferred over the bus in either asynchronous priority mode or isochronous priority mode. Asynchronous priority mode gives priority to transfer of the asynchronous data and isochronous priority mode gives priority to transfer of the isochronous data. In addition, data transferred over the bus is selectably transferred in either whole-bus mode: in which the entire data bus transfers data in one direction or in or half-bus mode in which portions of the data bus may transfer data in different directions.

Abstract: To reduce latency on a shared bus during bus arbitration, a novel shared bus system uses device select lines between a bus arbiter and the bus devices to select the bus slave concurrently with the granting of the shared bus to the bus master. Specifically, a bus device requests the use of the shared bus by driving an active state on a bus request terminal and driving a destination ID value corresponding to the desired bus slave to the bus arbiter. The bus arbiter then drives an active state on a bus grant output terminal coupled to the bus grant input terminal of the requesting device. Concurrently, the bus arbiter drives an active state on the device select output terminal coupled to the device select input terminal of the desired bus slave. In addition posted read request tagging can be simplified using a transaction ID bus to supplement the shared bus.

Abstract: The present invention provides control bus (SMBus) management and interface for a smart battery system having an SMBus two-wire interface with a clock and data line. Electrostatic discharge protection circuitry which does not have the potential to inadvertently charge a dead battery is provided for the SMBus. SMBus mastering circuitry is also provided to work in conjunction with the SMBus interfacing routines for communications on the bus.

Abstract: A bridge for a multi-processor system provides interfaces to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism arbitrates between the first and the second processing sets for access to each others I/O bus and to the device bus in a first, split, mode, and monitors lockstep operation of the first and second processing sets in a second, combined, mode. On detecting a lockstep error in the combined mode, the bridge transfers to an error mode. The bridge control mechanism buffers write accesses in a posted write buffer in the error mode pending resolution of the error.

Abstract: A switch positioned on an exterior housing of a mobile computer has a first position associated with enablement of a wireless communication device incorporated within the mobile computer. When in the first position, the switch provides indication that the wireless communication device is enabled. The switch also has a second position associated with disablement of the wireless communication device. When in the second position, the switch provides indication that the wireless communication device is disabled. The switch having no affect on the enablement or disablement of the mobile computer. Also included is a means for enabling the wireless communication device when the switch is in the first position and disabling the wireless communication device when the switch is in the second position. Furthermore, light emitting diodes provide indication of the status of the wireless communication device within the mobile computer.

Abstract: During burst write transactions, a memory accepts data over an address bus after an address has been received. In order to accept data over the address bus, the memory temporarily stores the data received over the address bus in an internal data buffer. The internal data buffer then transfers the data to an array upon completion of the write transaction. During burst read transactions, the memory transmits data over the address bus during one of the four clock cycles after the address is received. In this way a burst write transaction is completed in three clock cycles instead of four. Burst read transactions are completed in four clock cycles instead of five.

Abstract: A method and apparatus for decoupling internal latencies of a bus bridge from those on an external bus is described. In one embodiment, the method includes detecting a write cycle by an initiator for transmitting data to a device. The method further includes asserting a write request to the device, responsive to detecting the write cycle, asserting a ready request to the initiator without detecting an acknowledge from the device, and receiving the data from the initiator.

Abstract: An apparatus for an method of sending and receiving data on a Universal Serial Bus using a memory shared among a number of end points are disclosed. The memory is a double buffer which allows the next packet to be prepared while the current packet is being transmitted. The invention also supports transmission retry.

Abstract: A multiprocessor processing 200 includes a memory system having a memory controller 202 for linking a plurality of processors 201 with an integrated memory 203. Integrated memory 203 comprises a plurality of static random access arrays 603 and a dynamic random access 407.

Abstract: The present invention discloses an apparatus for combining partially defected synchronous dynamic random access memories. By selecting each memory chip with corresponding workable blocks, the partially defected SDRAMs can be combined as a workable device which can be programmed and operated in the same way as a defect-free chip. The apparatus for combining partially defected synchronous dynamic random access memory chips of the present invention includes a workable block selecting circuit and a chip selecting circuit. The workable block selecting circuit is responsive to a reference signal for selecting workable blocks of the synchronous dynamic random access memories. The chip selecting circuit is responsive to a chip selecting signal and the reference signal for selecting a chip from the synchronous dynamic random access memory chips.

Abstract: A computer system for high-performance video and audio manipulations comprising a locked memory cartridge and an audio/video/compact disk (CD) drive controller/coprocessor. The computer system has a central processing unit (CPU) with at least one bus associated therewith, with the bus having at least one bus line. The cartridge comprises a readable memory, a memory control circuit, a lock control circuit, and a connector all in circuit communication with each other. The connector allows the memory, the memory control circuit, and the lock control circuit to be pluggably connected in circuit communication with the CPU. The memory control circuit scrambles some of the bus lines, thereby scrambling the data in the memory on reset, and unscrambles the bus lines responsive to inputs from the lock control circuit.

Abstract: A portion of digital data records are stored on a direct access storage device (DASD) in emulation of sequential-access media when the parent digital data records are transferred to a sequential-access media. The efficiency of storage and access to the data portion is improved by random-access recall of the data in the data portion, and by constructing a data portion trailer containing various statistics about the records for referencing the digital data and advancing to target data. The volume data portion trailer is constructed as read forward and forward space block operations are performed. Data is preferably stored in logically assembled records. Interspersed with the records, there may be one or more marker codes, which function like tape marks among the various data records. The volume trailer may contain pointers to each record, a record count and marker codes for the data portion. Statistics contained in the data portion trailer enable substantially more efficient access of the data by a DASD.

Abstract: A converter system that allows a host system using a first interface to use a second storage using a second interface. The invention provides a method to allow an ECKD MVS DASD storage using an ESCON interface to be used by an open system using a SCSI-type interface without changes to the ESCON storage or the open storage interfaces. The method also permits the SCSI-type interfaced open system to be physically located greater than 25 meters from the ESCON storage system. The method involves mapping the SCSI-type interface data and commands into parameters used and understood by the ESCON storage. The invention may also be implemented to provide a digital data storage medium containing the method of the invention and a digital apparatus capable of executing the invention.

Abstract: A disk control device is operationally connected to a high-order device and operates a plurality of disk devices. A cache is included in the disk control device for storing data including a plurality of parity data from a corresponding plurality of parity groups in the plurality of disk devices. The disk control device also includes a cache management table for indicating the positions of the data stored in the cache. Cache management means is provided for transferring a selected data request by the host control from the plurality of disk devices to the cache when the cache management table indicates that said selected data is not stored in the cache. Control means transfers the selected data from the cache to the high-order device when the cache management means informs the control means that the selected data is stored in the cache.

Abstract: An information storage system having a volume managing function and including a magnetooptical disk auto-changer, the system having data location optimizing means for, in accordance with access speed at which an access of data is made from each of disks, performing an optimizing function for optimizing data location in a case where data is stored in the disk, a volume management table for collecting and storing statistical information of data accesses for determining validity of the optimizing function when each of the disks has made an access to data, and data optimization determination means for determining validity of the optimizing function in accordance with the statistical information of data accesses.

Abstract: A data transmission device which can read information on an IC card without changing a structure of a conventional floppy disc drive is provided. The IC card includes memory elements for storing information therein. The IC card is accommodated in the data transmission device and the data transmission device is attached to the floppy disc drive so that data stored in the IC card is read via the floppy disc drive. The IC card is electrically connected to the data transmission device. A magnetic head core unit of the data transmission device is magnetically connected to a magnetic head of the floppy disc drive so as to transmit data to the floppy disc drive via the magnetic head. A waveform of data read from the IC card is changed to a waveform which is conformable to a reproduction characteristic of the floppy disc drive.

Abstract: A cache for use with a network filter that receives, stores and ejects local rule bases dynamically. The cache stores a rule that was derived from a rule base in the filter. The cache rule is associated in the cache with a rule base indicator indicating from which rule base the cache rule was derived, and a rule base version number indicating the version of the rule base from which the cache rule was derived. When the filter receives a packet, the cache is searched for a rule applicable to a received packet. If no such rule is found, the filter rule base is found, and an applicable rule is carried out and copied to the cache along with a rule base indicator and version number. If a cache rule is found, it is implemented if its version number matches the version number of the rule base from which it was derived. Otherwise, the cache rule is deleted. The cache provides an efficient way of accurately implementing the rules of a dynamic rule base without having to search the entire rule base for each packet.

Abstract: A high-performance and cost-effective cache memory system is provided for use in conjunction with a high-speed computer system. The cache memory system is used on a computer system having a central processing unit (CPU) of the type having a back-off function that can be activated to temporarily halt the CPU when receiving a back-off signal. The cache memory system is capable of enabling the back-off signal in the event that the data read request signal from the CPU is determined to be a miss. During the back-off duration of the CPU, the requested data are moved from the primary memory unit to the cache memory module. This feature allows the overall performance of the computer system to be high even though a low-speed tag random-access memory (RAM) is used in the cache memory system, allowing the computer system to be highly cost-effective to use with high performance.

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

Abstract: A method and apparatus for utilizing a data cache in a system with both 2D and 3D graphics applications. In a specific embodiment of the present invention, a mode signal is received by the video system indicating whether a 2D or 3D application is to be used. Depending on the mode signal, either as a unified cache capable of being accessed by two separate data access streams, or two independent caches, each accessed by one data access stream.

Abstract: A microprocessor (62) for coupling to an external read/write memory (70) having an addressable storage space for storing data. The microprocessor includes a data storage circuit (76) for storing a portion of the data, where that portion of data comprises non-cacheable data. The microprocessor further includes a class storage circuit (80) for storing a class identifier corresponding to the portion of the non-cacheable data, as well as an input (TERMINATE) for receiving a terminate signal and an input (CLASS) for receiving a class signal. Lastly, the microprocessor includes an indicator (82) for indicating that the portion of the non-cacheable data in the data storage circuit is expired in response to assertions of the terminate signal and the class signal matching the class identifier.

Abstract: A system and method for processing a sequence of requests for data by one or more central processing units (CPUs) after cache misses. Each CPU request includes a CPU-ID tag identifying the CPU issuing the request for data and an address identifying a location in lower-level memory where the data is stored. Cache-control ID tags are assigned to identify the locations in the request queue of the respective CPU-ID tags associated with each CPU request. Cache-control requests consisting of the cache-control ID tags and the respective address information are sent from the request queue to the lower-level memory or storage devices. Data is then returned along with the corresponding CCU-ID tags in the order in which it is returned by the storage devices. Finally, the sequence of CPU requests for data is fulfilled by returning the data and CPU-ID tag in the order in which the data was returned from lower-level memory.

Abstract: In a cache system which includes a single global bus (5), a plurality of central processing units (1, 2) connected to the global bus, and a main memory unit (3 or 4) connected to the global bus, each of the central processing units includes a local bus (110 or 210), a plurality of store-in-caches (101-104 or 201-204), and a bus bridge (120 or 220) connected to the local bus and the global bus for controlling, by monitoring cache tags representative of states of the store-in-caches of each central processing unit, a request delivered from one of the store-in-caches of each central processing unit to the local bus to avoid store-confliction due to the request and a different request delivered to the global bus from one of the store-in-caches of a different central processing unit of the central processing units and to thereby keepcache-coherency among the store-in-caches of the central processing units.

Abstract: A method of managing and speculatively issuing architectural operations in a computer system. A first architectural operation is snooped and translated into a plurality of granular architectural operations to effect a large-scale architectural operation. The first architectural operation can be a first cache instruction directed to a memory block, and a plurality of cache instructions are issued which are directed to memory blocks contained in a page associated with the memory block. The granular architectural operations are transmitted to a processor bus of the computer system. A processor bus history table may be used to store a record of the large-scale architectural operation. The history table then can filter out any later architectural operation that is subsumed by the large-scale architectural operation. The history table monitors the processor bus to ensure that the large-scale architectural operations recorded in the table are still valid.

Abstract: A method of controlling first and second processing elements which have associated respective first and second address memories, and associated respective first and second data memories, the method comprising storing first and second pluralities of address entries in the first and second address memories respectively, exchanging a pre-determined number of address entries between the first and second address memories, retrieving data entries from a common data store on the basis of the address entries held in the first address memory, storing the retrieved data entries in the first data memory, and exchanging the pre-determined number of data entries between the first and second data memories, such that the first data memory includes data entries corresponding to the address entries stored in the first address memory, and such that the second data memory includes data entries corresponding to the address entries stored in the second address memory.

Abstract: A method and apparatus for selectively incrementing a count number associated with nodes which are subject to a compare and swap operation in a concurrent non-blocking priority queue. A memory is partitioned into a free list and a priority queue, and stores data in multiple nodes residing at least in the free list. Each node has a pointer and a count number associated therewith. Multiple processors access the memory and perform a compare and swap operation on the nodes. The count numbers associated with nodes are next fields selectively incremented only upon a successful compare and swap operation of a node being enqued behind it and when the enqued node is put onto one of the lists of the priority list.

Abstract: The present invention retrieves data across independent computer nodes of a server cluster by providing for I/O shipping of block level requests to peer intelligent host-bus adapters (hereinafter referred to as HBA). This peer-to-peer distribution of block I/O requests is transparent to the host. The HBA has the intelligence to decide whether to satisfy a block I/O request locally or remotely. Each HBA driver utilizes the I2O protocol, which allows peer-to-peer communication independent of the operating system or hardware of the underlying network. In a first embodiment of the present invention, local and remote storage channels, within a node, are supported by a single HBA. In a second embodiment of the present invention, local storage channels, within a node, are supported by one HBA, and the remote storage channel, within a node, is supported by a separate HBA.

Abstract: A method for efficiently updating as shared data structure in a multiprocessor environment comprises accessing a queue variable associated with time-based data events in the data structure. Information associated with the queue variable is used to determine the point of insertion of a new time-based data event. If a new time based data event is inserted, the data of the queue variable of a preceding time-based data event is altered to identify the new time-based data event. An embodiment employing a contention-free locking mechanism is also disclosed.

Abstract: A data backup and restore method and system for a multiple computer system environment is provided. The method/system comprises an automated approach for backing up and if necessary restoring computer system data from a first computer system to an auxiliary storage pool of a second computer system. At the first computer system, a renaming of system data to be backed up is accomplished such that the renamed system data designates the first computer system as the source system of the system data and comprises a name different from any name of system data at the second computer system. The renamed system data is then backup stored by the first computer system to the auxiliary storage pool of the second computer system. Multiple computer systems in the multisystem environment can be backed up to the same target computer system, either to the same auxiliary storage pool or to different auxiliary storage pools. Partial or complete restore of the backed up system data is also discussed.

Abstract: Two data storage systems are interconnected by a data link for remote mirroring of data. Each volume of data is configured as local, primary in a remotely mirrored volume pair, or secondary in a remotely mirrored volume pair. Normally, a host computer directly accesses either a local or a primary volume, and data written to a primary volume is automatically sent over the link to a corresponding secondary volume. Each remotely mirrored volume pair can operate in a selected synchronization mode including synchronous, semi-synchronous, adaptive copy-remote write pending, and adaptive copy-disk. Direct write access to a secondary volume is denied if a “sync required” attribute is set for the volume and the volume is not synchronized. If a “volume domino” mode is enabled for a remotely mirrored volume pair, access to a volume of the pair is denied when the other volume is inaccessible.

Abstract: A method (320) of implementing a set of ordering rules for executing requests for access to a system memory (14) includes the steps of identifying a request status (322) for a new request for access to the system memory (14) and assigning a tag to the new access request (324) based on the status of the new request. A control circuit (106) inserts the new access request (340) into one of a read buffer (302) or a write buffer (304) at a specified location within one or the read or write buffers (302, 304) based on the status of the new access request. When the new access request is enqueued (342) and sent to an arbitration circuit (306), the requests are executed in an order with another access request (344) from the other of the read or write buffer based on the request status and the tag of the new request.

Abstract: A memory device including an array of memory cells and a method for copying information within the memory device. Each memory cell includes a first memory sub-cell and a second memory sub-cell. Each memory cell also includes a device that copies information from the first memory sub-cell into the second memory sub-cell. Each memory cell may include a static random access memory (SRAM) cell and may utilize tri-state inverters to make overwriting information easier and reduce power consumption. Each memory cell may also include a second copy device that allows information to be copied from the second memory sub-cell to the first memory sub-cell. The memory device may be provided in a register file of a microprocessor to copy information from an architectural branch register (ABR) file to a speculative branch register (SBR) file.

Abstract: An apparatus and method for aligning any number of multiple parallel channels of data signals according to a single clock is provided. The synchronization process is accomplished through the use of a First-In-First-Out (FIFO) principle and individual storage elements implementing the FIFO principle for each received data channel. Each channel's data signals are read into a corresponding storage element, maintained in order, and read out upon the assertion of read signals in synchronization with a designated single clock signal. The apparatus and method preferably uses indications of data ready to be read from a storage element implementing the FIFO principle and the presence of a master clock signal to activate the reading of the data from the corresponding storage element. Therefore, each data channel is fully aligned with the master clock signal. The clock-data alignment function may be implemented for a 100BASE-T4 receiver.

Abstract: An integrated memory controller (IMC) which includes data compression and decompression engines for improved performance. The memory controller (IMC) of the present invention preferably sits on the main CPU bus or a high speed system peripheral bus such as the PCI bus and couples to system memory. The IMC preferably uses a lossless data compression and decompression scheme. Data transfers to and from the integrated memory controller of the present invention can thus be in either two formats, these being compressed or normal (non-compressed). The IMC also preferably includes microcode for specific decompression of particular data formats such as digital video and digital audio. Compressed data from system I/O peripherals such as the hard drive, floppy drive, or local area network (LAN) are decompressed in the IMC and stored into system memory or saved in the system memory in compressed format.

Abstract: A memory module includes a plurality of memory chips on the module; first logic for configuring the memory module to operate in a selectable mode; second logic for storing initial presence detect (PD) data; and third logic for storing modified PD data that corresponds to a requested mode of operation of the memory module received from a system controller.

Abstract: Interface bridge (13) between a system bus (ASBUS) and at least one local bus (11, 12), the system space directly addressable through said system bus being greater than the system space directly addressable through the local bus, comprising a plurality of programmable decoders (17, 18, 19) each of which defines a distinct range within the range directly addressable through the local bus, and a range attribute as range of local bus addresses to be translated or to be transferred directly to the system bus and also identifies a local bus address as being included or otherwise within the range, so that depending on whether the local bus address belongs to one of the ranges or not and on the range attribute, the local bus address is transferred to the system bus as a direct address or as an address translated by a translation logic (20, 21) and capable of addressing the entire system space.

Abstract: A method for searching for a record in a table in a memory of a computer system. A table of records is organized into a group of arrays. A hashing algorithm locates a record in the table. Multiple hashing functions are executed concurrently, according to the number of arrays in the group, such that the record can be located relatively quickly in one of the arrays in the group. The table is analyzed to determine the information content of each bit in a string of bits comprising an index value associated with the table, according to Shannon's formula for information-theoretic entropy. The entropy associated with each bit in the string of bits provides a basis for selecting a subset of bits in the string of bits from which to obtain the seed values utilized in the hashing functions. A rotating mask, based on Neumann's code, is applied to the subset of bits to obtain different seed values for each of the hashing functions, thereby minimizing the correlation of the keys provided by the hashing functions.

Abstract: An address generator for a solid state disk drive device includes a hardware multiplier logic circuit dedicated to computation of the address by multiplying a lock size by a logical block number, to obtain the start address for a memory array read or write operation. The dedicated multiplier circuit advantageously provides very quick computation of these relatively large numbers, which typically involves a 32 bit by 16 bit multiplication. The multiplier includes a shift register initially holding the logical block number which is shifted a particular number of times, the number of shift pulses representing a value of the block length. The output of the shift register is the desired address.

Abstract: A parallel processor is provided that includes integrated debugging capabilities. The processor includes a pipelined processing engine, having an array of processing element complex stages, and input and output header buffers. A debug system is provided that, when triggered, may put some or all of the processing element complexes into a debug mode of operation. When a complex is in debug mode, examination of internal stages of the component circuits of the complex may occur, in order to facilitate debugging of software and hardware errors that may occur during operation of the processor.

Abstract: A method for exchanging information within a mesh network that has an array of nodes defined by four quadrants. The method includes the initial step of exchanging information from a set of nodes in one quadrant to a set of nodes located in an adjacent quadrant. The exchange of information simultaneously occurs in both a vertical and horizontal direction within the array. Information is then exchanged between nodes within the same quadrant and subquadrants.

Abstract: An apparatus for processing data has a plurality of single-bit processing elements coupled together to form an m×n processing element array, where m is an integer number of rows and n is an integer number of columns. Each processing element has addressable storage for storing pixel data in an array format in which each addressable storage holds all of the bits associated with one pixel; and the processing element array includes a mechanism for providing direct read/write access to the addressable storage located in any addressed row of the processing element array without requiring that data be passed through other rows of the array.

Abstract: A pipelined data processing unit includes an instruction sequencer and n functional units capable of executing n operations in parallel. The instruction sequencer includes a random access memory for storing very-long-instruction-words (VLIWs) used in operations involving the execution of two or more functional units in parallel. Each VLIW comprises a plurality of short-instruction-words (SIWs) where each SIW corresponds to a unique type of instruction associated with a unique functional unit. VLIWs are composed in the VLIW memory by loading and concatenating SIWs in each address, or entry. VLIWs are executed via the execute-VLIW (XV) instruction. The iVLIWs can be compressed at a VLIW memory address by use of a mask field contained within the XV1 instruction which specifics which functional units are enabled, or disabled, during the execution of the VLIW. The mask can be changed each time the XV1 instruction is executed, effectively modifying the VLIW every time it is executed.

Abstract: A data protecting method wherein a resident control program which is stored as to be resident in a storage medium driving device judges on the basis of instruction from an executing device for executing a specified process, whether a control program for executing the process is incorporated or not therein, searches the control program from a set storage medium when the result of judgment is NO, reads in the searched control program, and incorporates the read-in control program therein. A storage medium driving device which stores this resident control program as to be resident, and a storage medium which is driven by this device.