Patents Issued in February 20, 2001
  • Patent number: 6192429
    Abstract: An integrated circuit memory device includes a DQM input buffer controller that enables the DQM buffer to process the DQM mask signal during a row active period of a read operation and a write operation of an integrated circuit memory device, and during a latency period of the read operation and the write operation, and that disables the DQM buffer otherwise during the read operation and the write operation. Thus, the DQM buffer is enabled to process the DQM mask signal during those portions of the read and write operations in which the external DQM mask signal is received and the DQM buffer is otherwise disabled during the read and write operations. The controller can also disable the DQM buffer during a refresh operation of the memory device and a power-down operation of the memory device. Accordingly, reduced current consumption in the DQM buffers may be obtained by only enabling the DQM input buffers when a DQM mask signal is expected during the read and write operations of the memory device.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: February 20, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-seop Jeong, Yong-cheol Bae
  • Patent number: 6192430
    Abstract: A mixed-signal processor (MSP) chip with a flexible serial interface which simultaneously accommodates two serial ports on a reduced number of pins. The pin definitions of these serial ports are configured to function well with several different external chips. Any two of these chips, or two of any one of these chips, may be used concurrently by the present MSP. When used with chips that require it, the present MSP chip provides a clock signal to each of these. When used with other chips, the MSP will can receive a clock signal from an external chip, and will then pass this signal through to any chip on the other of the two serial ports.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: February 20, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Ching-yuh Tsay, Richard E. Downing, George Paul Eaves, Craig Lance Dalley, Ian Lloyd Bower
  • Patent number: 6192431
    Abstract: A method and apparatus for configuring the pinout of an integrated circuit. An integrated circuit includes an input/output structure including an input/output port. The input/output structure communicates a first signal in a first configuration and a second signal in a second configuration. The first and second signals are parallel signals of a bus.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: February 20, 2001
    Assignee: Intel Corporation
    Inventors: Sanjay Dabral, Dilip K. Sampath, Christopher Cheng
  • Patent number: 6192432
    Abstract: An improved compressed file system is provided. In a preferred embodiment of the present invention, a memory cache is used for storing uncompressed data that is sent to or received from a compressed logical drive. When writing data to the compressed logical drive, the preferred embodiment of the present invention determines whether to use write-behind caching or write-through caching.
    Type: Grant
    Filed: April 5, 1999
    Date of Patent: February 20, 2001
    Assignee: Microsoft Corporation
    Inventors: Benjamin W. Slivka, Forrest Foltz
  • Patent number: 6192433
    Abstract: An on line serviceable computing system employing a small computer system interface (SCSI) bus architecture connecting two host computers to at least one additional shared device including a termination adapter circuit that can sense when a SCSI termination at the end of the SCSI bus is lost and automatically switch in a new SCSI bus termination to thereby ensure that the bus is terminated at both ends as required for continuous operation.
    Type: Grant
    Filed: July 14, 1998
    Date of Patent: February 20, 2001
    Assignee: Tandem Computers Incorporated
    Inventors: Wing Chan, David L. Griffith
  • Patent number: 6192434
    Abstract: A software architecture for the hot add and swap of adapters. The software architecture allows users to replace failed components, upgrade outdated components, and add new functionality, such as new network interfaces, disk interface adapters and storage, without impacting existing users. The software architecture supports the hot add and swap of off-the-shelf adapters, including those adapters that are programmable.
    Type: Grant
    Filed: October 1, 1997
    Date of Patent: February 20, 2001
    Assignee: Micron Electronics, INC
    Inventors: Walter August Wallach, Mehrdad Khalili, Mallikarjunan Mahalingam, John M. Reed
  • Patent number: 6192435
    Abstract: An interface between a main computer 20 and a peripheral unit 30 allows connection/disconnection of the peripheral unit to and from the main computer during the operation of the main computer, while achieving reduction of fluctuation in the source voltage caused by hot line connection/disconnection, as well as a reduction of the circuit size. The interface includes a connector having long terminal pairs and short terminal pairs, by which the peripheral unit 30 is connected to the main computer 20. The peripheral unit 30 contains a delay circuit comprised of a FET 10 for controlling ON/OFF operation of the electric current path, a capacitor C1, and resistors R1 and R2. The signal path containing R1 and R2 forms a closed loop only when the peripheral unit is completely inserted into the main computer. During the insertion, the long terminal pairs are first connected, which is followed by connection of the short terminal pair.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: February 20, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Akira Takahashi
  • Patent number: 6192436
    Abstract: A system and method for configuration of electronic devices using a smart card. A smart card configurable and testable system includes a programmable device, a bridge coupled to the programmable device, and a smart card interface coupled to the bridge. The bridge is configured and arranged to format configuration data from the smart card for transmission to the programmable device, and the smart card interface arrangement is configured and arranged to provide configuration data from the smart card to the bridge.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: February 20, 2001
    Assignee: Xilinx Inc.
    Inventors: Neil G. Jacobson, Matthew T. Murphy
  • Patent number: 6192437
    Abstract: A transmission apparatus includes a shelf which includes a working card slot and a protection card slot, the working card slot supplying a first slot ID to a first card inserted in the working card slot, and the protection card slot supplying a second slot ID to a second card inserted in the protection card slot. A control logic circuit, provided within each of the first and second cards, receives one of the first slot ID or the second slot ID, a redundancy/non-redundancy R/N signal and a working/protection W/P signal, and outputs a control signal depending on the related slot ID, the R/N signal and the W/P signal. A line connection relay, provided within each of the first and second cards, connects either a working line or a protection line to an output of the related card in accordance with the control signal supplied by the control logic circuit.
    Type: Grant
    Filed: August 16, 1999
    Date of Patent: February 20, 2001
    Assignee: Fujitsu Limited
    Inventors: Akihiko Oka, Keiichiro Tsukamoto
  • Patent number: 6192438
    Abstract: A U-interface matching circuit and matching method is disclosed. The circuit includes a plurality of BRI (Basic Rate Interface) boards implementing a digital subscriber's matching, a control board controlling operating modes of the plurality of BRI boards and an SA (Serial Access)-bus providing an independent data transmission path with regard to the plurality of BRI boards. The method includes a first step identifying mounting locations of a plurality of BRI boards, a second step reading an RX flag area of a first BRI board for data transmission and identifying whether the read RX flag is a flag representing the access complete of the first BRI board, a third step setting the first BRI mode as a write mode and transmitting the data length value and transmission data when the RX flag is a flag representing an access complete of the first BRI board, and a fourth step receiving transmission data of the first BRI board.
    Type: Grant
    Filed: December 31, 1998
    Date of Patent: February 20, 2001
    Assignee: LG Information & Communications, Ltd.
    Inventor: Ki Hyuk An
  • Patent number: 6192439
    Abstract: An interrupt steering architecture that enables an intelligent peripheral device to process interrupts from PCI devices associated with a PCI bus is disclosed. The interrupt steering architecture enables the PCI interrupt signals to be steered to either a host CPU or to an intelligent peripheral device. The interrupt steering architecture is wholly compliant with the PCI bus specification and does not utilize additional sideband signals. The interrupt steering architecture is under user control and can be set by the user at system initialization or reset.
    Type: Grant
    Filed: August 11, 1998
    Date of Patent: February 20, 2001
    Assignee: Hewlett-Packard Company
    Inventors: Paul Grunewald, Wesley H. Stelter, Jiangang Ding
  • Patent number: 6192440
    Abstract: A system and method for dynamically calculating the maximum amount of time a peripheral component event can be stored before generating a corresponding interrupt. Specifically, in this embodiment, the host computer is adapted to have a peripheral component removably coupled thereto and is adapted to operate a peripheral component driver. The peripheral component driver, in turn, is adapted to dynamically calculate the maximum amount of time a peripheral component event can be stored before generating a corresponding interrupt. The peripheral component of this embodiment is adapted to store the peripheral component event and cause the generation of an interrupt when the peripheral component event has been stored for the maximum amount of time. Once again, the present embodiment, like the previous embodiments, reduces the frequency with which interrupts are generated, and minimizes the CPU overhead associated with the servicing of interrupts.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: February 20, 2001
    Assignee: 3Com Corporation
    Inventors: Glen H. Lowe, Edmund Chen
  • Patent number: 6192441
    Abstract: This device controls the interrupts of a microprocessor based on events occurring in at least one entity associated with this microprocessor. The device organizes the storage of words representative of at least an origin and a type of the interrupt issued by the entity. The interrupts from the entity are stored in an area of a memory. When there is more than one entity, each entity has an area of memory allocated to it. The microprocessor can access these memory areas and process the interrupts. An indicator is also provided so that the device can tell when a memory area has become full.
    Type: Grant
    Filed: August 1, 1996
    Date of Patent: February 20, 2001
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Claude Athenes, Pascal Moniot
  • Patent number: 6192442
    Abstract: An interrupt controller includes conductors for receiving interrupt request signals, a memory, a register and control logic. Each of the interrupt request signals are capable of indicating an interrupt request. The memory is capable of storing information about the interrupt request signals, and the register is writable to identify a set of locations of the memory for scanning. The control logic scans the set of locations for interrupt requests and does not scan other locations of the memory for interrupt requests. In some cases, the number of interrupt request signals are exceeds the number of locations. For these cases, information about selected interrupt signals are stored in the locations.
    Type: Grant
    Filed: April 29, 1998
    Date of Patent: February 20, 2001
    Assignee: Intel Corporation
    Inventors: Kenneth C. Haren, Tuan Quach
  • Patent number: 6192443
    Abstract: An apparatus for use in a distributed processing system having a plurality of nodes wherein selected nodes are fenced or unfenced from selected ones of peripheral device server nodes in a fence/unfence operation. A common memory is provided for storing a fence map listing nodes fenced from server nodes. In the fence/unfence operation, a request processing node proposes changes to the fence map, and if no node fails during the fence/unfence operation, the proposed changes are changed into committed changes. If a node fails during the fence/unfence operation, the proposed changes are erased, the previous committed changes are restored, and the fence/unfence request is removed from the process queue for processing by the request processing node.
    Type: Grant
    Filed: July 29, 1998
    Date of Patent: February 20, 2001
    Assignee: International Business Machines Corporation
    Inventor: Gili Mendel
  • Patent number: 6192444
    Abstract: A method and system in accordance with the present invention provides additional addressable space on a disk for use by a host processor using a virtual data storage subsystem. The method and system includes defining at least one of a plurality of extended image devices on a disk and requesting an instant image to be addressed to an extended image device utilizing channel command words by a host processor. The method and system also includes reading the instant image utilizing commands, such as channel command words or common descriptor blocks, by the host processor. In a method and system in accordance with the present invention, a plurality of extended image devices are defined as extensions of a primary functional device. Data may be transferred between at least one of the plurality of extended images and the primary functional device, or between at least one of the plurality of extended image devices and another of the plurality of extended image devices.
    Type: Grant
    Filed: January 5, 1998
    Date of Patent: February 20, 2001
    Assignee: International Business Machines Corporation
    Inventors: Michael Wayne White, Patrick James Tomsula, David Serls
  • Patent number: 6192445
    Abstract: A programming system and method for programming a programmable memory device having multiple individually programmable memory cells, such as an electrically programmable read only memory (EPROM), includes the use of an address and programming pulse signal source and a programming and test controller for establishing, based upon the programming of a small number of on-chip sample memory cells, a presumptively sufficient initial programming pulse duration for programming the remaining memory cells. In the event it is found during actual programming that such an initial programming pulse duration is insufficient for any particular memory cell, additional programming pulses, each of which is significantly shorter in duration than the initial programming pulse, are applied to such memory cell as needed until the programming of such memory cell is completed.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: February 20, 2001
    Assignee: Altera Corporation
    Inventor: Saiid Rezvani
  • Patent number: 6192446
    Abstract: A memory device includes a memory array, a plurality of external lines, a command buffer, and control logic. The plurality of external lines is adapted for receiving an external command. The command buffer is adapted to store at least one command buffer entry. The control logic is coupled to the plurality of external lines and the command buffer. The control logic is adapted to access the memory array based on one of the command buffer entry and the external command. A method for providing commands to a memory device is provided. The memory device includes a command buffer, control logic and a memory array. The method includes reading a first buffered command from the command buffer. The first buffered command is provided to the control logic. The memory array is accessed based on the first buffered command.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: February 20, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Patrick J. Mullarkey, Casey R. Kurth, Scott J. Derner
  • Patent number: 6192447
    Abstract: A resettable memory apparatus includes a random access memory including a plurality of memory locations, each memory location stores a plurality of bits of data. A single register has a plurality of bits, there is one bit for each of the plurality of memory locations. A reset signal resets all of the bits in the register to invalid. A reset value is generated when reading a particular one of the memory locations while the corresponding bit in the register is invalid to provide a resettable random access memory. Writing data to the particular memory location sets the corresponding bit in the register to valid. Subsequent reads to the location while produced the data stored therein as long as the corresponding bit in the register remains valid.
    Type: Grant
    Filed: April 9, 1998
    Date of Patent: February 20, 2001
    Assignee: Compaq Computer Corporation
    Inventor: Mark A. Shand
  • Patent number: 6192448
    Abstract: A disk controller and associated method where conventional disk drive size files stored in the host computer are replaced with a drive size list maintained in the disk drive device controller. The disk size list structure permits the controller to do the disk drive sizing and provides a simplified list of disk drive size ranges that can be applied to all disk drives on the system regardless of disk drive make, model, or manufacturer. A disk drive size list can be generated from the existing disk drive configuration and maintained and updated with a minimum of user interaction.
    Type: Grant
    Filed: August 18, 1998
    Date of Patent: February 20, 2001
    Assignee: International Business Machines Corporation
    Inventor: Al Mansur
  • Patent number: 6192449
    Abstract: A most recently used bit (25) is used to determine if a data transfer should occur from a fill buffer (20) into a data memory (32) in a cache (15). If the data to be displaced in the data memory (32) has been referenced more recently than the data present in the fill buffer (20), then the transfer should not occur. When a cache miss does occur, a control register (50) is used to determine the conditions for loading the fill buffer (20).
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: February 20, 2001
    Assignee: Motorola, Inc.
    Inventors: Joseph C. Circello, Anup S. Tirumala, Vasudev J. Bibikar
  • Patent number: 6192450
    Abstract: Data in a write cache is coalesced together prior to each destage operation. This results in higher performance by destaging a large quantity of data from the cache with each destage operation. A root item of data is located, and then a working set of data is collected by identifying additional data in the cache that will be destaged to locations in the storage device adjacent to the root item of data. The root item of data may be identified by starting at the location of the least recently accessed data in the cache, and then selecting a root item of data at a lower storage device address than the least recently accessed data, or may be chosen from a larger than average group of data items that were stored together into the cache. To speed execution, data items are added to a working set by, where possible, scanning an queue of data items kept in access order to locate data items at adjacent storage locations.
    Type: Grant
    Filed: February 3, 1998
    Date of Patent: February 20, 2001
    Assignee: International Business Machines Corporation
    Inventors: Ellen Marie Bauman, Robert Edward Galbraith, Mark A. Johnson
  • Patent number: 6192451
    Abstract: A data processing system and method of maintaining cache coherency in a data processing system are described. The data processing system includes a plurality of caches and a plurality of processors grouped into at least first and second clusters, where each of the first and second clusters has at least one upper level cache and at least one lower level cache. According to the method, a first data item in the upper level cache of the first cluster is stored in association with an address tag indicating a particular address. A coherency indicator in the upper level cache of the first cluster is set to a first state that indicates that the address tag is valid and that the first data item is invalid. Similarly, in the upper level cache of the second cluster, a second data item is stored in association with an address tag indicating the particular address. In addition, a coherency indicator in the upper level cache of the second cluster is set to the first state.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: February 20, 2001
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, John Steven Dodson, Jerry Don Lewis
  • Patent number: 6192452
    Abstract: A method for avoiding data loss due to cancelled transactions within a non-uniform memory access (NUMA) data processing system is disclosed. A NUMA data processing system includes a node interconnect to which at least a first node and a second node are coupled. The first and the second nodes each includes a local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and a node interconnect. The node controller detects certain situations which, due to the nature of a NUMA data processing system, can lead to data loss. These situations share the common feature that a node controller ends up with the only copy of a modified cache line and the original transaction that requested the modified cache line may not be issued again with the same tag or may not be issued again at all.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: February 20, 2001
    Assignee: International Business Machines Corporation
    Inventors: John Peyton Bannister, Gary Dale Carpenter, Mark Edward Dean, David Brian Glasco, Richard Nicholas Iachetta, Jr.
  • Patent number: 6192453
    Abstract: A method and apparatus for preventing the occurrence of deadlocks from the execution of unresolvable system bus operations. In general, each snooper speculatively accepts a given operation when it has a snoop buffer available. However, rather than unconditionally processing the operation, the snooper waits to determine if another participant retried the operation due to unavailability of a snoop buffer. If some snooping participant retrys an operation, all snoopers that speculatively accepted an operation for processing abandon said operation. If no snooping participant retrys the operation, sufficient snooping resources were available for all necessary caches to begin processing the operation and the initiator can consider the operation completed. In other words, no operation is processed until all the necessary snooping resources are available to accept the operation. This prevents the system from getting into the ping-pong deadlock.
    Type: Grant
    Filed: July 13, 1998
    Date of Patent: February 20, 2001
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Derek Edward Williams, John Michael Kaiser ()
  • Patent number: 6192454
    Abstract: A storage medium unit is used as a part of a system for providing information-on-demanding service. The storage medium unit has a storage device for storing information data including video data and/or audio data to be retrieved therefrom and transmitted to end user devices of the information-on-demand service, a memory controller for controlling the storage device, and a memory device for storing software program. The software program is downloaded from a system manager of said system into said memory device. The memory controller controls operation of the storage device according to the downloaded software program.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: February 20, 2001
    Assignee: Sony Europa B.V.
    Inventor: Johan De Vos
  • Patent number: 6192455
    Abstract: A method for preventing access to a system management random access memory (SMRAM) space is disclosed. The method intercepts access to an accelerated graphics port (AGP) aperture memory space and re-directs the access to non-SMRAM space if the access is directed to the SMRAM space.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: February 20, 2001
    Assignee: Intel Corporation
    Inventors: Zohar Bogin, Vincent E. VonBokern
  • Patent number: 6192456
    Abstract: A method includes operations for creating and formatting FAT partitions beyond the first gigabyte of a disk having more than one gigabyte of data storage space, when the disk is associated with a controller card that does not include an option-ROM with a BIOS. In particular, the method populates at least one variable of each partition boot sector with a non-F6 value which then is detected to cause the use of the partition LBA for formatting the boot sector, rather than the partition CHS. A computer readable medium can also include program instructions for creating and formatting FAT partitions beyond the first gigabyte of a disk having more than one gigabyte of data storage space, when the disk is associated with a controller card that does not include an option-ROM with a BIOS.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: February 20, 2001
    Assignee: Adaptec, Inc.
    Inventors: Yen-Chung Lin, Thanh Tu Bui
  • Patent number: 6192457
    Abstract: A method for implementing a graphics address remapping table as a virtual register in system memory. The remapping table includes virtual registers that each store a target index that references a block of the system memory that stores graphics data. The method uses an indirect addressing scheme that enables the individual virtual registers of the remapping table to be accessed in response to a transaction request. Accessing a selected virtual register indirectly requested by the transaction request enables the method to access graphics data pointed to by the selected virtual register.
    Type: Grant
    Filed: July 2, 1997
    Date of Patent: February 20, 2001
    Assignee: Micron Technology, Inc.
    Inventor: A. Kent Porterfield
  • Patent number: 6192458
    Abstract: To avoid multiplexing within the critical address paths, the same address field is employed as a index to the cache directory and cache memory regardless of the cache memory size. An increase in cache memory size is supported by increasing associativity within the cache directory and memory, for example by increasing congruence classes from two members to four members. For the smaller cache size, an additional address “index” bit is employed to select one of multiple groups of address tags/data items within a cache directory or cache memory row by comparison to a bit forced to a logic 1.
    Type: Grant
    Filed: March 23, 1998
    Date of Patent: February 20, 2001
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, John Steven Dodson, Jerry Don Lewis
  • Patent number: 6192459
    Abstract: A data retrieval system receives a data address identifying data to be retrieved. A portion of the received data address is communicated to a data storage device during a first clock cycle. The system determines a second address portion based on the received data address. The second address portion is communicated to the data storage device during a second clock cycle. Data is then retrieved from the data storage device based on the address portions communicated to the data storage device. The portion of the received data address communicated to the data storage device during the first clock cycle is a set address and the second address portion communicated to the data storage device during the second clock cycle is a way address. A read cycle can be initiated after communicating a portion of the received data address to the data storage device during the first clock cycle.
    Type: Grant
    Filed: March 23, 1998
    Date of Patent: February 20, 2001
    Assignee: Intel Corporation
    Inventors: Randy M. Bonella, Peter D. MacWilliams, Konrad K. Lai
  • Patent number: 6192460
    Abstract: Disclosed is a method and apparatus for accessing data in a computer system after a failed data operation in which I/O process state information is unknown. The failed data operation may cause data inconsistency among multiple devices associated with a shadow set for storing data. The disclosed system includes techniques for allowing continued data accesses while simultaneously re-establishing data consistency among members of the shadow set.
    Type: Grant
    Filed: December 16, 1997
    Date of Patent: February 20, 2001
    Assignee: Compaq Computer Corporation
    Inventors: William Lyle Goleman, Scott Howard Davis, David William Thiel
  • Patent number: 6192461
    Abstract: One aspect of the invention relates to an apparatus for processing a store instruction on a superscalar processor that employs in-order completion of instructions, the processor having an instruction dispatch unit, an architected register file, a rename register file, a load store unit, a completion unit and cache memory. In one embodiment of the invention, the apparatus includes a pointer queue having an entry corresponding to the store instruction, the entry containing a pointer to the entries in the architected and rename register files that contain data required by the store instruction; and a multiplexer coupled to read ports on the architected and rename register files so that data can be passed from one of the register files into an entry in a data queue, the data queue being coupled to the cache memory.
    Type: Grant
    Filed: January 30, 1998
    Date of Patent: February 20, 2001
    Assignee: International Business Machines Corporation
    Inventors: Barry D. Williamson, Jim E. Phillips, Dq Nguyen
  • Patent number: 6192462
    Abstract: A superscalar microprocessor is provided which maintains coherency between a pair of caches accessed from different stages of an instruction processing pipeline. A dependency checking structure is provided within the microprocessor. The dependency checking structure compares memory accesses performed from the execution stage of the instruction processing pipeline to memory accesses performed from the decode stage. The decode stage performs memory accesses to a stack cache, while the execution stage performs its accesses (address for which are formed via indirect addressing) to the stack cache and to a data cache. If a read memory access performed by the execution stage is dependent upon a write memory access performed by the decode stage, the read memory access is stalled until the write memory access completes.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: February 20, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thang M. Tran, David B. Witt, William M. Johnson
  • Patent number: 6192463
    Abstract: A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.
    Type: Grant
    Filed: October 7, 1997
    Date of Patent: February 20, 2001
    Assignee: Microchip Technology, Inc.
    Inventors: Sumit K. Mitra, Joseph W. Triece
  • Patent number: 6192464
    Abstract: In one aspect the present invention provides for a method for executing a sequence of instructions in a processor. The method comprises decoding a first the instructions into one or more first micro-ops, renaming destination registers identified in a first portion of the first micro-ops by reassigning available additional physical registers for the destination registers, and decoding a second portion of the first micro-ops into one or more second micro-ops. The act of renaming has renamed a destination register of at least one micro-op of the second portion of the first micro-ops. The method executes a third portion of the first and the second micro-ops.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: February 20, 2001
    Assignee: Intel Corporation
    Inventor: Millind Mittal
  • Patent number: 6192465
    Abstract: A microprocessor capable of out-of-order instruction decoding and in-order dependency checking is disclosed. The microprocessor may include an instruction cache, two decode units, a reorder queue, and dependency checking logic. The instruction cache is configured to output cache line portions to the decode units. The decode units operate independently and in parallel. One of the decode units may be a split decoder that receives all instruction bytes from instructions that extend across cache line portion boundaries. The split decode unit may be configured to reassemble the instruction bytes into instructions. These instructions are then decoded by the split decode unit. A reorder queue may be used to store the decoded instructions according to their relative cache line positions. The decoded instructions are read out of the reorder queue in program order, thereby enabling the dependency checking logic to perform dependency checking in program order.
    Type: Grant
    Filed: September 21, 1998
    Date of Patent: February 20, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventor: James S. Roberts
  • Patent number: 6192466
    Abstract: A pipeline control system, in accordance with the present invention, includes a plurality of operation stages for processing instructions, the operation stages including at least one instruction issue stage wherein instructions wait to be issued. A mechanism for analyzing an issued instruction is included to determine if the issued instruction is successful without requiring stall cycles. If instructions cannot be completed successfully due to resource conflicts or exception conditions, they are aborted and reissued by the at least one instruction issue stage. A mechanism is also included for directly returning the aborted instructions to be reissued to the at least one instruction issue stage such that the instruction is reissued while the operational stages continue to process instructions. A method for pipeline control is included.
    Type: Grant
    Filed: January 21, 1999
    Date of Patent: February 20, 2001
    Assignee: International Business Machines Corporation
    Inventor: Michael K. Gschwind
  • Patent number: 6192467
    Abstract: A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, each of the instructions in the second set of instructions specify operations to be performed on only a subset of the data element stored in the one or more specified registers.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: February 20, 2001
    Assignee: Intel Corporation
    Inventors: Mohammad A. Abdallah, Vladimir Pentkovski, James Coke
  • Patent number: 6192468
    Abstract: A superscalar microprocessor implements a microcode instruction unit with sequence control fields appended to each microcode line. The sequence control fields indicate whether a subsequent line contains a branch instruction, whether a subsequent line is the last line in a microcode sequence, and other sequence control information. The sequence control information is accessed one cycle before the microcode line. This allows the next address to be calculated in parallel with the accessing of the microcode instruction line. By generating the next address in parallel with accessing the microcode line, the time delay from accessing one microcode line to accessing the next microcode line is reduced. The sequence control field additionally indicates how many microcode instructions are in the last line of the microcode sequence.
    Type: Grant
    Filed: October 27, 1999
    Date of Patent: February 20, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rupaka Mahalingaiah, Paul K. Miller
  • Patent number: 6192469
    Abstract: A method and apparatus for providing relocatable code storage in a multifunction controller or other integrated circuit which includes an embedded microprocessor and an internal memory. The relocatable code is initially stored in an external memory which is shared by the embedded microprocessor and other system processing elements such as a host CPU. During a system initialization, power-on reset or other predetermined event, a memory multiplexing circuit connects the address inputs of the internal memory to a read/write address bus, and connects the output of a jump data storage circuit to a code data output bus. The jump data storage circuit uses code addresses received from the embedded microprocessor to generate a jump instruction code which is supplied to the embedded microprocessor via the code data output bus.
    Type: Grant
    Filed: September 17, 1996
    Date of Patent: February 20, 2001
    Assignee: Standard Microsystems Corporation
    Inventors: Kenneth George Smalley, Ian Fraser Harris
  • Patent number: 6192470
    Abstract: A computer system is implemented according to the invention when an computer process allows a user to determine a desired computer configuration by in part determining performance relative to price candidate configurations.
    Type: Grant
    Filed: July 29, 1998
    Date of Patent: February 20, 2001
    Assignee: Compaq Computer Corporation
    Inventors: Keith L. Kelley, Charles A. Bartlett, Manoj J. Varghese, Christoph Schmitz
  • Patent number: 6192471
    Abstract: A system which builds an operating system-independent environment for executing utility programs is created by establishing a virtual drive that resides on a physical disk drive within the native file system of a native operating system. A virtual drive is a set of files on a physical disk drive that is configured to emulate a physical disk drive. The virtual drive can be deleted by a computer user and similarly can be re-established by the computer user. The virtual drive is bootable and activates an operating system that makes all system resources accessible to the utility programs and also allows the computer user to use the disk space that is allocated for the virtual drive, if desired.
    Type: Grant
    Filed: January 26, 1996
    Date of Patent: February 20, 2001
    Assignee: Dell USA, LP
    Inventors: John J. Pearce, Anthony L. Overfield
  • Patent number: 6192472
    Abstract: A solution to the general problem of Secure Storage and Retrieval of Information (SSRI) guarantees that also the process of storing the information is correct even when some processors fail. A user interacts with the storage system by depositing a file and receiving a proof that the deposit was correctly executed. The user interacts with a single distinguished processor called the gateway. The mechanism enables storage in the presence of both inactive and maliciously active faults, while maintaining (asymptotical) space optimailty. This mechanism is enhanced with the added requirement of confidentiality of information; i.e., that a collusion of processors should not be able to learn anything about the information. Also, in this case space optimality is preserved.
    Type: Grant
    Filed: June 23, 1999
    Date of Patent: February 20, 2001
    Assignee: International Business Machines Corporation
    Inventors: Juan Alberto Garay, Rosario Gennaro, Charanjit Singh Jutla, Tal D. Rabin
  • Patent number: 6192473
    Abstract: A method is provided for establishing mutual authentication and secure communications between an microprocessor-based transaction evidencing device and a microprocessor-based server coupled thereto. A session key KS is generated at the transaction evidencing device and encrypted with a first key K1 to form a first message. The first message is sent to the server and decrypted using a second key K2. In response to the first message a second message is generated at the server and encrypted using the session key KS. The encrypted second message is sent to the transaction evidencing device and decrypted using the session key KS. A response to the second message is generated at the transaction evidencing device and is signed using a third key K3. The signed response is encrypted with the session key KS and transmitted to the server. The encrypted signed response is decrypted using the session key KS and the signature is verified using a fourth key k4.
    Type: Grant
    Filed: December 24, 1996
    Date of Patent: February 20, 2001
    Assignee: Pitney Bowes Inc.
    Inventors: Frederick W. Ryan, Jr., Robert W. Sisson
  • Patent number: 6192474
    Abstract: In the password protocol, the communicating parties exchange calculation results, which each include an exponential, to generate a key. In generating the calculation results, each party adds the password to their respective exponential. If the authorizing information previously sent by one party is acceptable to the other party, then this other party uses the key established according to the password protocol. The channel authorizing information is sent over a secure communication channel. The secure communication channel is also used in other embodiments to verify a hash on at least one calculation result sent between the parties. If the hash is verified, then a key is established using the calculation results sent between the parties.
    Type: Grant
    Filed: July 31, 1998
    Date of Patent: February 20, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Sarvar Patel, Adam L. Berenzweig
  • Patent number: 6192475
    Abstract: A system and method for rewriting software into a protected form, called cloaked software, such that this cloaked form is protected from analysis or reverse engineering while at the same time the cloaked software is executable. Further, said cloaked software may be set up so that it requires a correct key or keys to be supplied, when it is to be run, for it to execute correctly. Cloaking modifies the basic operations within the software so that the logical connections or data flow among the program operations is no longer visible. In fact, cloaking makes the correct dataflow among operations dependent on a complex interrelated set of addressing operations within the cloaked program. These addressing operations are designed so that their analysis is equivalent to a computationally intractable NP-complete problem. This situation prevents reverse-engineering and unauthorized tampering.
    Type: Grant
    Filed: March 25, 1998
    Date of Patent: February 20, 2001
    Inventor: David R. Wallace
  • Patent number: 6192476
    Abstract: A method and system are provided for determining whether a principal (e.g. a thread) may access a particular resource. According to one aspect of the invention, the access authorization determination takes into account the sources of the code on the call stack of the principal at the time the access is desired. Because the source of the code on the call stack will vary over time, so will the access rights of the principal. Thus, when a request for an action is made by a thread, a determination is made of whether the action is authorized based on permissions associated with routines in a calling hierarchy associated with the thread. The determination of whether a request is authorized is based on a determination of whether at least one permission associated with each routine encompasses the permission required to perform the requested action. Support for “privileged” routines is also provided.
    Type: Grant
    Filed: December 11, 1997
    Date of Patent: February 20, 2001
    Assignee: Sun Microsystems, Inc.
    Inventor: Li Gong
  • Patent number: 6192477
    Abstract: A method for performing secure communication between a first user's computer and second remote computer over a computer network is described. According to one embodiment of this aspect, the data space of the first computer is partition into a first secure portion and a second network interface portion. Communication is established between the first and a second computer, and redirection and filter mechanisms are initialized. An instruction is received by the first computer, analyzed by the redirection mechanism, and passed to the filter if the instruction is a protected instruction. The protected instruction is verified by the filter and processed if the verification is successful.
    Type: Grant
    Filed: February 2, 1999
    Date of Patent: February 20, 2001
    Assignee: Dagg LLC
    Inventor: David Corthell
  • Patent number: 6192478
    Abstract: An embodiment of the present invention provides a facility for securing the use of a distinguished operation, such as a computer system administration operation, to authorized users. The facility first displays an ornamental image to a user. The displayed ornamental image contains a visual key feature that the facility uses to discern the authority of the user to perform the distinguished operation. The facility then determines whether the user has selected the key feature within the ornamental image. The facility invokes the distinguished operation only in response to a determination that the user has selected the key feature. In this way, only authorized users informed to select the key feature may invoke the distinguished operation.
    Type: Grant
    Filed: March 2, 1998
    Date of Patent: February 20, 2001
    Assignee: Micron Electronics, Inc.
    Inventor: Dennis D. Elledge