Abstract: A method and apparatus for operating a local server computer of a client-server network includes a technique to receive a request from a client computer of the client-server network. A determination is made whether the request requires dynamically generated information from a servlet object of the client-server network. If so, a specified servlet object corresponding to the request may be uploaded from a remote server computer of the client-server network. The specified servlet object is then executed to obtain dynamically generated information corresponding to the request.

Abstract: A plurality of user terminals regularly accessing Internet Relay Chat (IRC) services are also in communication with a service selecting host. The service selecting host is configured to collect data from the plurality of user terminals. The collected data includes information about the users at the user terminals and information about the user terminals activity in the accessing of the IRC services. The service selecting host compiles and sorts the collected data concerning IRC services to produce information provided to the user terminals. The information provided to the user terminals allows users at the user terminals to more easily select sorted IRC services.

Abstract: Network Distributed Caches (“NDCs”) (50) permit accessing a named dataset stored at an NDC server terminator site (22) in response to a request submitted to an NDC client terminator site (24) by a client workstation (42). In accessing the dataset, the NDCs (50) form a NDC data conduit (62) that provides an active virtual circuit (“AVC”) from the NDC client site (24) through intermediate NDC sites (26B, 26A) to the NDC server site (22). Through the AVC provided by the conduit (62), the NDC sites (22, 26A and 26B) project an image of the requested portion of the named dataset into the NDC client site (24) where it may be either read or written by the workstation 42. One NDC (50) of a pair of NDC sites (26A and 26B) which share memory (314A-B) returns a pointer to an NDC buffer (129) in response to a request for data from the other NDC (50).

Abstract: A communication apparatus, a communication system, and a communication method are provided for relaying and receiving data from an information source which presents data services such as video data services via a network such as Internet. With this configuration, the service data can be dynamically changed and a digest corresponding to such a change can be presented. Also with this configuration, a communication apparatus, a communication system, and a communication method are provided which are capable of reducing the load of the whole network and relaying and receiving data at high efficiency.

Abstract: A method and apparatus providing voice-interactive access to the internet via wireless networks enabling a subscriber, while driving or performing other tasks, to input commands to the internet using a voice input function, such as voice recognition, and retrieve the information from the internet using a voice output function, such as voice synthesis. The present invention allows a subscriber to enter voice commands at an internet terminal, as well as commands through other external interfaces, such as a key pad or touch screen. The internet terminal can also display and store the received data from the internet. in addition to the output by voice synthesis. The present invention may utilize a hands-free kit, allowing the subscriber to drive a car or perform other tasks and receive the internet information without any additional action on the part of the subscriber.

Abstract: The present invention manages a messaging network having messaging platforms interconnecting through a switched backbone such as the Internet. The master platform monitors each messaging platform on the messaging network and administers the addition, deletion, and updating of messaging platforms by modifying a master global routing table in the event the master platform encounters changes to the status of the messaging platforms. In the event that the master global routing table is updated, the global routing table held at each messaging platform is also updated, ensuring version consistency between said master global routing table and each of the global routing tables. This enables the master platform and each messaging platform to determine the operational status of another messaging platform. The present invention may also provide a cost tracking scheme when delivering messages between messaging platforms that are owned by different entities.

Abstract: A Web server is provided having a multi-homed, modular framework. The modular framework allows extensions to the Web server to be easily compiled into the Web server, allowing the extensions to run natively as part of the server instead of incurring the overhead typical of CGI scripts, for example. The multi-homing capabilities of the Web server provide the appearance to Web users of multiple distinct and independent servers, allowing a small company or individual to create the same kind of Web presence enjoyed by larger companies. In effect, multiple virtual servers run on the same physical machine. The Web server as a whole is easily extensible to allow additional capabilities to be provided natively within the Web server itself. Furthermore, each virtual server is independently configurable in order to turn different capabilities on or off or to modify operation of the virtual server.

Abstract: A file transmission acknowledgement system and method that indicates the success or failure of a file transfer from a content provider to client computers using a data distribution system. A transmitting processor transmits a file processed by a transmitting processor. One or more personal computers and/or server computers simultaneously receive the transmitted file by way of respective receivers. A reception algorithm on the server or personal computers determines if the file was successfully or unsuccessfully received by the respective computer. A receipt generation algorithm on the one or more server or personal computers generates a receipt acknowledgement or a receipt non-acknowledgement. A return path communication circuit is provided between the server or personal computers and the transmitting processor for delivering the acknowledgements to the transmitting processor. An algorithm on the transmitting processor collates the receipt transmissions.

Abstract: Systems and methods for implementing site specific message dispatch in an object-oriented environment are provided. Receiver type information may be saved at a message dispatch site in order to provide site specific message dispatch. By allowing message dispatch to vary at different call sites, object-oriented systems may be more efficient and flexible.

Abstract: A storage media for automating a control and a computer system including the storage media, which abolishes the restriction between the hardware models and the software processes, and in which a desired software process can be simply utilized in any hardware models, and a computer system including the storage media are provided. In the intelligent disk 1 having the disk 3 for storing information and the electronic circuit portion 2 for processing the information, wherein the disk stores a plurality of information to be used in an external system, and wherein the electronic circuit portion distinguishes the information stored in the disk, which matches with the external system. Also, the disk unit or the electronic circuit further includes an emulator for matching the system program with the external system.

Abstract: A handheld computer which contains an LCD display having a digitizing surface to allow pen input. Internal storage takes several forms, such as a large flash ROM area, battery-backed up RAM and an optional hard disk drive. Several alternative communication paths are available, such as the previously mentioned modem, a parallel printer port, a conventional serial port, a cradle assembly connected to the host computer, and various wireless short distance techniques such as radio frequency or infrared transmission. The computer can readily communicate with other sources, particularly to a host desktop computer, to allow automated synchronization of information between the host and the handheld system. Preferably the remote synchronization is performed at several user selectable levels. When the handheld computer is in a cradle and actively connected to the host computer, automatic capture of updated data in the host computer is performed.

Abstract: A method for avoiding data collision in a half-duplex mode using a DMA logic for multi-point linked processors is disclosed. According to the disclosed method, a transmitting processor holds a request-to-send (RTS) signal in an active state for a prescribed period of time so that a transmitting DMA logic of a receiving processor can be initiated after the operation of a receiving DMA logic of the receiving processor is terminated. Since the Tx DMA logic of the receiving processor starts data transmission after the Rx DMA logic of the receiving processor completes receiving of data, data collisions occurring in the receiving processor due to the concurrent operation of the Tx DMA logic and the Rx DMA logic can be prevented.

Abstract: A method of and apparatus for capturing and processing continuous media-based data streams transmitted over an IEEE 1394 serial bus manages the use of both receive buffers and process buffers in order to minimize the amount of captured data that is discarded due to unavailable process buffers. When receiving a stream of continuous data, the data is captured and stored within a current receive buffer. When the current receive buffer is full, the captured data within the receive buffer is then read out, processed and stored within a process buffer, if a process buffer is available on a cached list of process buffers. When full of processed data, the process buffer is then transferred to an application for utilization or further processing of the processed data. If the process buffer is not completely filled, then the process buffer is added back to the cached list of process buffers.

Abstract: A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.

Abstract: The present invention encompasses an apparatus for bridging a first computer interface bus and a second computer interface bus, where each of the first and second computer interface buses have a number of parallel multiplexed address/data bus lines and operate at a clock speed in a predetermined clock speed range having a minimum clock speed and a maximum clock speed.

Abstract: In a modular data acquisition system (4), a module comprises at least one analog-to-digital converter (12) for converting an analog input signal (IN1, IN2, IN3, IN4) into a digital signal (OUT1, OUT2, OUT3, OUT4), and a clock generating circuit (20) for supplying an internal clock signal (209). The module further comprises a connector for plugging in a removable connecting element (3) on the front side of the module (1) in order to connect it to a synchronization bus connecting several modules in said system.

Abstract: A data server having a plurality of hot replaceable processing unit modules. Each module includes a motherboard having plugged therein: a CPU; a main memory; an I/O adapter card, and an interconnect printed board, electrically connected to the motherboard. A backplane has a first connector adapted for coupling to a DC power supply. The interconnect printed circuit board has a DC to DC converter connected to a second connector adapted to mate with the first connector to enable the processing unit module to be hot plugged into, or removed from, the backplane. The backplane has formed thereon a strip transmission line adapted to provide an Ethernet bus for interconnecting a plurality of the modules. A cable management system for a cabinet used to house the module includes at least one vertically extending channel disposed in the cabinet and a fastener adapted to open and enable the a cable to be inserted into the channel and close to retain such cable within the channel.

Abstract: The present invention is an apparatus and method for providing power management apparatus for a circuit in a processor-based system. The apparatus comprises a memory to store instruction sequences by which the processor-based system is processed and a processor coupled to the memory. The stored instruction sequences cause the processor to: (a) determine a system access time of the circuit; (b) determine if the system access time is less than a first predetermined value, if so, increasing an accessibility period of the circuit, during which the circuit is active. Various embodiments are described.

Abstract: A data storage apparatus in which an interface for a pre-existing floppy disc and another interface for a large-capacity floppy disc compatible with the pre-existing floppy disc are provided and can be operated effectively independently of each other. A disc sort discriminating circuit discriminates the type of the disc loaded on the apparatus to send the results of discrimination to a controller. The controller is responsive to the results of discrimination to control a FDD interface which is an interface for the pre-existing floppy disc and an IDE interface which is an interface for the large-capacity floppy disc. The interface pertinent to the type of the loaded disc is controlled to perform a recording/reproducing operation corresponding to the accessing, while the interface pertinent to the type of the non-loaded disc is controlled to return a disc-absent response to a host computer.

Abstract: A data retrieval system receives a data address identifying data to be retrieved. A portion of the received data address is communicated to a data storage device during a first clock cycle. The system determines a second address portion based on the received data address. The second address portion is communicated to the data storage device during a second clock cycle. Data is then retrieved from the data storage device based on the address portions communicated to the data storage device. The portion of the received data address communicated to the data storage device during the first clock cycle is a set address and the second address portion communicated to the data storage device during the second clock cycle is a way address. A read cycle can be initiated after communicating a portion of the received data address to the data storage device during the first clock cycle.

Abstract: A status register for a memory device. The status register provides a programming suspend status signal and a protection status signal. The programming suspend status signal indicates whether a programming operation is suspended. If the processor knows that a programming operation to a specific memory location is suspended, then the processor may request that a data modification operation to another memory location be performed while the programming operation is suspended. The protection status signal indicates whether an attempted data modification operation failed due to a protected memory block versus another type of device failure. Protecting or locking a memory block prevents the modification of data stored in a particular memory block.

Abstract: Write data, when given from a host via an interface, are temporarily stored in a buffer memory of a disk control unit. A number-of-chips managing unit manages the number of memory chips executing writing operations. If the number of memory chips in the process of writing operations does not reach a fixed number, the write data are transferred to the memory chips allocated to, corresponding write areas. Whereas if the number of memory chips in the process of writing operations reaches the fixed number, the write data are transferred after an end of the writing operations to the memory chips in the process of writing operations. An entire electric current during the writing operation of a disk card can be thereby restricted.

Abstract: An architecture for a state machine used to control the data processing operations performed on the memory cells contained in a memory array. The architecture is designed to control the performance of the operations and sub-operations used to erase and program the memory array. The architecture of the present invention does not utilize separate state machines for each primary operation, but instead is based on a single state machine which is capable of controlling the various functions common to the data processing operations carried out on the memory cells. A sequencer which acts upon commands input from an external microprocessor is used to determine which set of sub-operations or functions needs to be performed to implement the commanded operation. The sequencer activates a timer which acts to trigger the functions controlled by a loop controller as they are needed for a particular operation.

Abstract: Conventional information storage systems are subject to numerous practical constraints such as contiguity in the physical locations of blocks and the requirement that storage blocks be created in advance. Information retrieval in these systems has required the creation of indices, which take a long time to generate, and the structure of these systems makes them prone to deadlock since the indices are updated and the range of exclusion broadened when the referent information is modified. This invention utilizes the random access facilities of semiconductors to achieve high speeds and minimize the maintenance load. This invention introduces location tables and alternate-key tables to replace these indices. It also stores multiple records in a single block and can handle variable-length records and spanned records. The location tables manage the storage blocks.

Abstract: A memory subsystem for a computer system includes a memory controller that has a data strobe generator. The memory subsystem further includes a DRAM array coupled to the memory controller and a data path coupled to the data strobe generator and the DRAM array. The DRAM array is separated into two DRAM sets coupled to a common output bus. Access to the DRAM array begins with access to the first DRAM set. After a first CAS is applied to the first DRAM set, a data strobe is asserted which causes data from the first DRAM set to be latched into the data path. On the next clock cycle after the data strobe is asserted, the data strobe and first CAS are de-asserted. A second CAS is then applied to the second DRAM set on the next clock cycle after the first CAS is de-asserted.

Abstract: A disk device having a read/write processing device to improve the efficiency of operations between write commands that have overlapping data, and to prevent delays in execution processing of starting commands. A read command advance processor unit that processes in advance the read commands for which there are unprocessed write commands in the command queue and a write command overlap data processor overwrites the existing write command write data overlap part when the new write command write data overlaps the write data from an existing write command.

Abstract: A method, apparatus and computer program for controlling data migration in an information processing system which includes a central processing unit (CPU), a new storage system connected to the CPU and an old storage system connected to the new storage system. In the information processing system data migration is conducted to transfer data from the old storage system to the new storage system. The invention operates by permitting access by the CPU to the storage systems during data migration. When an access by the CPU is generated the invention determines whether the access is to a region where data migration has been completed or to a region where data migration has not been completed. If the access is to a region where data migration has been completed, then processing of the access is handled by the new storage system.

Abstract: A disk caching method for an intermediary controller is disclosed. Requests for data blocks are made and then disk caching is performed according to a most expedient cache method. The disk caching method may be performed by asynchronously requesting a data record from both a intermediary controller disk storage and from a intermediary controller cache and using a first received copy of the data record, the first received copy being a copy received first from the intermediary controller disk storage.

Abstract: A processing unit for carrying out specified data processing operations while performing read/write operations on data in an internal memory is coupled to a memory control unit for performing read/write operations on data in an external memory. Data exchange is carried out between the internal and external memories through the memory control unit. Data requiring a longer processing time or data frequently accessed is mapped into the internal memory in accordance with the data exchange, thereby improving overall memory system performance.

Abstract: The present invention provides a shared instruction cache for multiple processors. In one embodiment, an apparatus for a microprocessor includes a shared instruction cache for a first processor and a second processor, and a first register index base for the first processor and a second register index base for the second processor. The apparatus also includes a first memory address base for the first processor and a second memory address base for the second processor. This embodiment allows for segmentation of register files and main memory based on which processor is executing a particular instruction (e.g., an instruction that involves a register access and a memory access).

Abstract: A method and apparatus for controlling compartmentalization of a cache memory. A cache memory including a plurality of storage components receives one or more externally generated cache compartment signals. Based on the one or more cache compartment signals, cache compartment logic in the cache memory selects one of the plurality of storage compartments to store data after a cache miss.

Abstract: A method and apparatus for clearing memory, or portions thereof, in a fast and efficient manner begins by representing a group of memory locations by a representative value. When a particular group of memory locations is accessed, a determination is made as to whether the corresponding representative value is in first state. If so, a clear value is stored in each corresponding memory location of a cache memory. Note that the corresponding memory locations of the cache memory correspond to the group of memory locations. The processing continues by setting a dirty bit for the corresponding memory locations of cache when the representative value is in the first state. If, however, the representative value is in a second state, data is read from the group of memory locations into the corresponding memory locations of the cache memory. When a cache write-back command is received, the data, or clear values, stored in memory are written from the cache memory into the main memory.

Abstract: The present invention provides a mechanism whereby caching operations, such as prefetch and copyback operations, can be initiated by an external direct memory access (DMA) controller. This allows the DMA controller to govern the inclusion as well as exclusion of data from a processor cache in such as way as to avoid unnecessary cache faults, and to thereby improve system performance. Thus, the present invention effectively provides a synchronization mechanism between an external DMA controller and a processor cache.

Abstract: In fault-tolerant systems it is known to write data into two separate disk drives. It is also known to duplex computers so that when one computer fails, the other computer can continue operating. In such a system, the active unit usually controls both disk drives. It is also known to cache in the main memory of the computer the most recently used areas in the disk drive, since it is likely that these areas (e.g. directories) must be read again soon. A problem occurs when using duplexed computers each of which is to be provided with a possibility of using the disk drive (14, 24) while the operation is expedited by caching in the main memories of the computers (10, 20). If one computer modifies the data in the disk drive, the other computer is not necessarily aware of this, but it uses the outdated data in its memory. According to the invention, the computer (10) desiring to control the disk drive (14) reserves it for itself. If the reservation is successful, a disk talk is performed.

Abstract: N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of host computers 10, 20, 30; upon startup of the host computers 10, 20, 30, when the storage controller 40 receives a frame issued, then the microprocessor 42 operates to perform comparison for determining whether the N_Port_Name information stored in the frame has been already set in the microprocessor 42 and registered to the N_Port_Name list within a control table maintained. When such comparison results in match, then continue execution of processing based on the frame instruction; if comparison results in failure of match, then reject any request.

Abstract: N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of host computers 10, 20, 30; upon startup of the host computers 10, 20, 30, when the storage controller 40 receives a frame issued, then the microprocessor 42 operates to perform comparison for determining whether the N_Port_Name information stored in the frame has been already set in the microprocessor 42 and registered to the N_Port_Name list within a control table maintained. When such comparison results in match, then continue execution of processing based on the frame instruction; if comparison results in failure of match, then reject any request.

Abstract: An addressable memory device for storing blocks of varying length, utilises a write pointer (18) to indicate the address of the next location to which data are to be written and an erase pointer (16) to indicate the address of the next location from which data are to be erased. It has a sector header (20) appended to each group of data containing information (38) indicating the length of the corresponding sector of data, and the location stored by the write pointer (14), which is selected to ensure that there is always at least one erased block adjacent to the current write block.

Abstract: A method in a data processing system for managing data within the data processing system. A discardable page that is to be removed from the memory is identified. A determination is made as to whether performance will increase by storing the discardable page in a paging device located within the data processing system. If it is determined that performance will increase, the discardable page is marked as a paged discardable page and stored in the paging device locally, wherein this page may be retrieved from the paging device.

Abstract: A digital image management system is described which facilitates image archival with a unique method for grouping customer images and information. As applied to medical environments, the system creates a virtual film jacket and implements the unique method by modeling convention hospital film archival procedures. The invention facilitates archival to a variety of devices including a redundant array of independent disks, magneto-optical storage devices and digital linear tapes and eliminates the need for hospital staff to retrieve several tapes from archive in order for a radiologist to review a patient's study. The invention is applicable to any environment where customer images and information are continuously archived and retrieved.

Abstract: A semiconductor memory such as a flash memory having addressable sectors of stored data with access to the stored data being controlled by control logic includes a register coupled to the control logic and having bits corresponding to data sectors to be protected and a protection code indicating that access to the identified sectors is to be controlled. The protection code can be identified by a single bit in the register to prevent either access to identified sectors or to prevent alteration of data in identified sectors. A plurality of memory sectors can be identified for protection in a single write cycle of the memory thereby improving system performance and simplifying firmware requirements.

Abstract: A system and method for dynamically allocating memory in a computer system at the application level. The application examines a heap data structure and a free list, identifies an unallocated region of memory that is appropriately sized, and allocates the memory to the application. The application deallocates a memory region by placing the memory region in the free list and modifying the heap data structure.

Abstract: The present invention provides a method and apparatus for allowing developers to develop software for their product. In one aspect of the present invention, a method is provided that includes providing a first mode signal to a processor to operate in a development mode. The method also includes executing instructions stored in a first region of the memory in response to the first mode signal, providing data to the processor, and writing the data into a second region of the memory.

Abstract: The central processing unit is provided with an instruction queue storage section. This central processing unit is made of a memory, such as FIFO memory, that adopts first-in first-out method. A counter counters each time an instruction datum is stored in the instruction queue storage section. When the value of the counter is 0 or 1 and instruction fetch is not suppressed, a fetch request is issued.

Abstract: A system with a network interconnecting a server and a plurality of user stations. The server stores a plurality of user applications for downloading to user stations and further stores access permissions for the applications for each user. When a user attempts to log onto the system, the server uses the user's log-on identifier to build a list of applications for which the user has access permission. The server downloads to the station a list of applications to which the user has access permission. The user station uses the list to build a folder containing only the applications from the list to which the user has access permission. The system further verifies from the list that the user has access to applications that are represented by objects that the user may have added to his or her desktop at an earlier time.

Abstract: A reconfigurable register file integrated in an instruction set architecture capable of extended precision operations, and also capable of parallel operation on lower precision data is described. A register file is composed of two separate files with each half containing half as many registers as the original. The halves are designated even or odd by virtue of the register addresses which they contain. Single width and double width operands are optimally supported without increasing the register file size and without increasing the number of register file ports. Separate extended registers are also employed to provide extended precision for operations such as multiply-accumulate operations.

Abstract: A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A tag is assigned to each instruction in the variable advance instruction window. The tag of each instruction to leave the window is assigned to the next new instruction to be added to it. The results of instructions executed by the processor are stored in a temp buffer according to their corresponding tags to avoid output and anti-dependencies. The temp buffer therefore permits the processor to execute instructions out of order and in parallel. Data dependency checks for input dependencies are performed only for each new instruction added to the variable advance instruction window and register renaming is performed to avoid input dependencies.

Abstract: A plurality of units identified by respective addresses are disposed in a register file. Each of the units has a data register for storing data representative of a result of an arithmetic operation, a register for storing an overflow flag indicating the presence or absence of an occurrence of overflow in the arithmetic operation, and a register for storing a sign flag providing an indication of which one of a positive and a negative saturation value should replace the arithmetic operation result in the presence of an occurrence of overflow in the arithmetic operation. Each of the flags is updated in response to a write signal concerning its corresponding register. If at the moment when a data register is fed a read signal, a corresponding overflow flag is set, then either a positive or a negative saturation value, whichever corresponds to the sign flag, is generated on the input side of an arithmetic unit.

Abstract: In a logic integrated circuit such as an FPGA, a controller reads in an instruction, and then directly transmits ON/OFF information for each of bits composing microcode included in the instruction, to registers and data memories that are allocated to each of the bits through control lines, to thereby control the registers and data memories. Thus, processing executed by the controller is simplified in this construction. This allows makings the controller having a simple structure, thereby making it possible to construct a simple CPU core on the logic integrated circuit such as the FPGA, decreasing a space of analytic logic, and eliminating necessity for re-integrating a hardware circuit every time the logic is renewed.

Abstract: A branch prediction method includes the steps of: a) determining branch prediction data indicating a state of branch prediction according to whether a branch is actually made or not; b) performing branch prediction according to the branch prediction data; and c) correcting the branch prediction data according to whether a branch is actually made or not.

Abstract: A system for loading upgraded, that is, new boot code and/or main firm ware has a programmable memory that has two boot code regions. One of the regions holds the active boot code while the other region holds the inactive boot code. During a boot code upgrade, the boot code in the inactive region, is under control of the boot code in the active region, replaced with the new boot code. Once the replacement process is verified as having been successful and the vector table in the new boot code is copied to the processor vector table in the memory, the processor can be reset so that the new boot code becomes the active boot code and the previously active boot code becomes the inactive boot code.