Abstract: A high voltage flyback power supply provides slope-based primary feedback to control the off-time of the power supply. When a negative slope is detected at a low side of a primary winding of the power supply, an off-time cycle is terminated and a next on-time cycle is initiated. The slope-based off-time primary feedback helps to keep the off-time of the power supply in sync with ringing of the primary leakage inductance and the primary-side capacitance of the power supply. Such a power supply is particularly useful for battery-powered systems with low voltage rails. The power supply can also include on-time feedback to shorten the on-time of the power supply after the secondary-side voltage rises beyond a certain relatively high voltage level. In this way, the transformer of the power supply is charged less when the power supply is driving relatively light loads.

Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.

Abstract: In a semiconductor memory device, a die architecture is provided that arranges memory arrays into a long, narrow configuration. Bond pads may then be placed along a long side of a correspondingly shaped die. As a result, this architecture is compatible with short lead frame “fingers” for use with wide data busses as part of high speed, multiple band memory integrated circuits.

Abstract: System modules are described which include a stack of interconnected semiconductor dies. The semiconductor dies are interconnected by micro bump bonding of coaxial lines that extend through the thickness of the various dies. The coaxial lines also are selectively connected to integrated circuits housed within the dies. In one embodiment, a number of memory dies are interconnected in this manner to provide a memory module.

Abstract: A memory system comprising memory cells and reference cells each including a programmable resistance element. The resistance state of a memory cell is determined by comparing a sense signal developed by the memory cell with a reference signal developed by one or more of the reference cells. The programmable resistance elements may comprise a phase-change material.

Abstract: A semiconductor memory device includes a plurality of bit lines; a plurality of virtual GND lines; and a plurality of memory cell transistors arranged in an array. The plurality of bit lines includes a selected bit line directly connected to a memory cell transistor to be read among the plurality of memory cell transistors and a non-selected bit line. The plurality of virtual GND lines includes a selected virtual GND line directly connected to the memory cell transistor to be read and a non-selected virtual GND line. The non-selected bit lines include a charge non-selected bit line to be charged and a non-selected dummy bit line to be grounded. The non-selected virtual GND lines include a charge non-selected virtual GND line to be charged. The non-selected dummy bit line is connected between the selected virtual GND line and one of the charge non-selected bit line and the charge non-selected virtual GND line.

Abstract: It is an object of the present invention to provide a sequential circuit having nonvolatile characteristics capable of holding data therein even when the power supply is shut-off. An inverter circuit INV1 is formed by replacing a pair of transistors consisting the conventional CMOS inverters with transistors NT and PT both having an MFMIS structure. A polarization state corresponding to an ON state is held in a ferroelectric layer 32 of the transistor NT even when the power supply thereof is shut off, and another polarization state corresponding to an OFF state is held in a ferroelectric layer 32 of the transistor PT. The transistors NT and PT are turned into ON and OFF state respectively according to the polarization states held in their ferroelectric layers 32 when the power supply is turned ON again. In this way, the inverter circuit INV1 recovers its state to the state right before the shut-off by turning the power supply into the ON state again.

Abstract: A semiconductor memory device comprising a write transistor with a gate connected to a write word line and with a first impurity region forming a source or drain connected to a bit line, a read transistor with a gate connected to a second impurity region forming a source or drain of the write transistor, a first impurity region connected to a read word line, and a second impurity region connected to a bit line, and a capacitor connected between the gate and the second impurity region of the read transistor.

Abstract: One electrode of each storage capacitor C of the memory cells MC is connected via the associated memory transistor T to one of the bit lines BLi and another electrode is connected to one of the plate segments PLA, PLB; PLC, PLD. A control terminal of each selection transistor T is connected to one of the word lines WLi. In a normal operating mode, the potential of only one of the plate segments in each case is pulsed in the event of accesses to the memory cells MC. In a test operating mode, the potentials of both plate segments are pulsed simultaneously.

Abstract: A molecular-wire crossbar interconnect for signal routing and communications between a first level and a second level in a molecular-wire crossbar is provided. The molecular wire crossbar comprises a two-dimensional array of a plurality of nanometer-scale switches. Each switch is reconfigurable and self-assembling and comprises a pair of crossed wires which form a junction where one wire crosses another and at least one connector species connecting the pair of crossed wires in the junction. The connector species comprises a bi-stable molecule. Each level comprises at least one group of switches and each group of switches comprises at least one switch, with each group in the first level connected to all other groups in the second level in an all-to-all configuration to provide a scalable, defect-tolerant, fat-tree networking scheme. The primary advantage is ease of fabrication, because an active switch is formed any time two wires cross.

Abstract: One or more multi-state magnetoresisitive memory elements (MRMEs) are used as the primary building block for various analog functional components implemented in corresponding analog functional modules. The MRMEs are configured into a memory array to create a programmable resistive element, a programmable voltage source, a programmable current source, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a phase lock loop (PLL) and various other analog functional modules. The magnetoresistive analog functional modules are coupled together with at least one other logic module in a system to perform a process. When implemented on an IC, each module may each be implemented with the same or with different manufacturing processes. The other logic modules may be implemented in any desired manner, such as with magnetoresistive memory technology or any other type of technology providing complete system design flexibility.

Abstract: All source regions belonging to a row are electrically connected to one another through a silicon layer (4) in a portion between a bottom surface of a partial-isolation insulating film (5) and an upper surface of a BOX layer (3). These constitute source lines (SL1 to SL5) extending like strips in a row direction. The isolation insulating film (5) between the source regions adjacent to each other in the row direction is removed and in the silicon layer (4) of the portion exposed by removing the isolation insulating film (5), an impurity introduction region (10) having the same conductivity type as the source region has is formed. With this structure, a nonvolatile semiconductor memory device which causes no malfunction due to driving of a parasitic bipolar transistor can be provided.

Abstract: A nonvolatile semiconductor memory device including a plurality of memory cells connected in parallel with each other, each of which has a memory transistor and a selecting transistor connected in series between a bit line and a source electrode, in such a configuration that information may be, via that bit line, input to and output from any one of the memory cells which is selected by a word line connected to gate electrodes of these two transistors, wherein transistor driving force of one of these two transistors of the memory cell whichever faces the bit line is enhanced. That transistor which faces the bit line is the one which lies on a drain side of the memory cell, that is, a memory transistor.

Abstract: An integrated circuit device using electrically programmable non-volatile memory cells, such as a single polysilicon having a single polysilicon level, for identifying and enabling the integrated circuit device. Such as an integrated circuit device having a memory array having rows and columns, and including redundant elements. The redundant elements include a selected one of redundant rows, redundant columns, and redundant rows and columns; and the redundant elements are selected and enabled by electrically programmable non-volatile memory cells. In another embodiment, an integrated circuit device having an electrical chip identification device including electrically programmable non-volatile memory cells.

Abstract: A computer apparatus comprises a read-only memory, a non-volatile memory, a random access memory and a controller. The read-only memory is a memory in which a program composed of a plurality of modules each have a particular function is written. The non-volatile memory is a writable memory which stores a replacing module which is formed by correcting an error within a defective module of the program. The random access memory is readable and writable. The controller transfers the replacing module from the non-volatile memory into the random access memory, executes the program written in the read-only memory, reads and executes the replacing module stored in the random access memory, instead of reading the defective module.

Abstract: A non-volatile semiconductor memory includes: multiple write pipelines, each including a memory array; a timing circuit which sequentially starts programming operations in the pipelines; and a shared charge pump and voltage regulation circuit that drives a current through the memory cells being programmed. Staggering the starts of programming operations reduces the current demand on the charge pump because spikes that occur at the starts of programming operations, for example, when using channel hot electron injection, are distributed over time rather than occurring all at once. Noise, which can reduce the accuracy of write operations, is also reduced because the total current required from the charge pump is more nearly constant. As further aspect of the invention, each write pipeline can perform a write operation as alternating programming cycles and verify cycles.

Abstract: With a local self boost (LSB) technique, the distribution of threshold voltages after data erase is set toward a higher side and the distribution width is narrowed sufficiently within the range in which cell erase states can be read. To this end, block write is carried out on a memory cell array. Next, setting a predetermined voltage as a start voltage, soft erase is carried out for each block. After carrying out erase verification read, the threshold voltages of the cells are compared with a determination reference value. As a result of this comparison, if the threshold voltages of the cells do not reach the determination reference value, soft erase is repeated. In that case, the predetermined voltage during the soft erase is changed from the start voltage. When the threshold voltages of all the cells have reached the determination reference value, the soft erase is ended.

Abstract: The flash memory device according to the present invention includes an erase control circuit, used as a state machine, having embodied erase algorithm which can prevent flash memory cells from being over-erased. The erase control circuit, first, checks whether or not threshold voltages of selected cells reach a predetermined pre-verify voltage higher than the maximum value of a target threshold voltage range corresponding to the erased state. When at least one of the selected cells has its threshold voltage higher than the pre-verify voltage, a high voltage generator generates a bulk voltage that is increased step by step by a predetermined voltage level. And, when the selected cells all have threshold voltages equal to or less than the pre-verify voltage, the high voltage generator generates a constant bulk voltage. According to this bulk voltage control scheme, the number of flash memory cells over-erased at the erase operation is reduced reducing the total erase time.

Abstract: The amount of charge supplied to a high level sense power supply line by a level control circuit is monitored. Charge of an equal amount is drawn out from a low level sense power supply line according to the monitoring result. In a memory of a boosted sense ground scheme, the boosted sense ground voltage can be maintained at a predetermined voltage level stably.

Abstract: A semiconductor memory device having input/output sense amplifiers capable of varying gains using a column address and block selection signals. The input/output sense amplifiers can compensate for reduction of transfer rate according to distance between a selected memory block or sub memory block and the sense amplifiers. A semiconductor memory device of the present invention includes: a plurality of sub memory blocks divided by a column address in a memory block; a plurality of data input/output line pairs coupled to the sub memory blocks, for transmitting data in a selected sub memory block; and a plurality of input/output sense amplifiers for sensing and amplifying data from the data input/output line pairs, wherein each of the input/output sense amplifiers has a variable gain characteristic depending on distance between the selected sub memory block and the input/output sense amplifiers so as to minimize a difference in delay characteristic according to position of the selected sub memory block.

Abstract: A memory device having a segmented row repair architecture that provides the benefits of single bit repair, thereby efficiently utilizing redundant rows of the memory device, is disclosed. The rows of a memory device are segmented into four segments and segmented row repair is provided by selectively disabling a wordline driver for only one segment of the primary row in which a defective memory cell is located and enabling a redundant wordline driver with a redundant term signal provided by the redundancy matching circuit, thereby substituting a redundant row segment for only a specific segment of the entire row length. By selectively disabling only the wordline driver associated with the defective memory cell and dividing the primary and redundant rows into four segments, localized or single bit repair can be performed, thereby efficiently utilizing the redundant rows of the memory device.

Abstract: The memory device has a selection device which, when required, ensures that backup memory cells or backup memory cell areas are used instead of memory cells or memory cell areas which cannot be written to or read from properly. Information about the location of the memory cells which are possibly not to be used is actually supplied to the selection device at an instant at which it is not yet definite whether memory cells need to be replaced.

Abstract: A memory cell array includes spare elements for saving a defective cell. Fuse sets each contain a defective address and mapping information indicative of the relationship between the fuse sets and the spare elements. When the defective address matches an input address, each fuse set outputs a signal for activating a corresponding spare element. The number of the fuse sets within a chip is smaller than the number of the spare elements.

Abstract: This invention provides a semiconductor memory device with a shift redundancy circuit which has a shortened redundancy operation. The semiconductor memory device of the present invention includes a plurality of shift switches and a changeover signal generating circuit connected to the shift switches. The changeover signal generating circuit may have a plurality of signal generating blocks including a first signal generating block for generating a first group of changeover signals and a second signal generating block for generating a second group of changeover signals.

Abstract: A semiconductor test system for testing semiconductor devices has a plurality of different tester modules and an algorithmic pattern generator (ALPG) for generating an algorithmic pattern specific to an intended memory in the device under test, thereby achieving a low cost and application specific memory test system. The semiconductor test system includes two or more tester modules whose performances are different from one another, an ALPG module for generating an algorithmic pattern which is specific to the memory; a test system main frame to accommodate a combination of tester module and ALPG module, a test fixture for electrically connecting the tester modules and a device under test, a performance board provided on the test fixture for mounting the device under test, and a host computer for controlling an overall operation of the test system by communicating with the tester modules through a tester bus.

Abstract: In a semiconductor memory device a column decoder outputs column select signals which are in turn transmitted to a memory cell block via a transfer gate which turns on when a signal fed through a WBI pad is placed in the inactive state. Even-numbered column select lines are connected via a transfer gate to an even-numbered CSL pad, and odd-numbered column select lines are connected via the transfer gate to an odd-numbered CSL pad.

Abstract: A RAMBUS dynamic random access memory includes a test control circuit that selectively couples a row address latch to either a row sense control signal or a CMD control signal. In a normal operating mode, the test control circuit couples the row address latch to the row sense control signal so that the row sense control signal both latches a row address and senses a row of memory cells corresponding to the latched address. Prior to conducting a core noise test, the test control circuit couples the row address latch to the CMD control signal so that the row address is latched by the CMD control signal, and the row sense control signal only functions during the core noise test to sense a row corresponding to the latched row. The memory also includes a multiplexer that receives a time-multiplexed data/address bus and simultaneously couples a first part of the data/address bus to an internal data bus and a second part of the data/address bus to an internal address bus.

Abstract: In an input buffer circuit, a second stage includes a BiNMOS non-inverter and a CMOS inverter, and a driver circuit includes BiNMOS push-pull circuits.

Abstract: A semiconductor memory includes a memory cell array including a plurality of memory cells, wherein each of the plurality of memory cells outputs a first data signal through an I/O line; an I/O line driving circuit for generating a second data signal by amplifying the first data signal, wherein the I/O line driving circuit is connected to the I/O lines; a data bus driving circuit connected to the I/O line driving circuit to generate a third data signal by amplifying the second data signal; a data bus precharge circuit; and a data bus connecting the data bus driving circuit to the data bus precharge circuit, wherein the data bus precharge circuit precharges the data bus to a predetermined voltage level before the third data signal is generated and transfers a voltage of the data bus to high or low level in accordance with a logic value of the third data signal when the third data signal is generated.

Abstract: A circuit and method characterizes a sense amplifier, such as the type utilized in computer memory systems. The sense amplifier characterization circuit comprises a sense amplifier having one or more inputs and an output, a BIT line connected to one of the one or more inputs of the sense amplifier, a register connected to the output of the sense amplifier; and control logic connected to the BIT line. Optionally, the register is further connected to the control logic, and the register is a scan register connectable to a tester. Preferably, the sense amplifier is a differential sense amplifier, and the circuit further comprises a complement BIT line connected to one of the one or more inputs of the sense amplifier. The method produces one or more signals like an output of a memory cell, operates one or more sense amplifier to produce one or more output states on the basis of the one or more signals, and records the one or more output states.

Abstract: A power-on-reset circuit that may be configured to present a power-on-reset signal in response to a voltage. The power-on-reset circuit may comprise a voltage detector, a first analog delay circuit and a feedback loop. The first analog delay circuit may be coupled to an output of the voltage detector. The feedback loop may be coupled an output of the power-on-reset circuit to an input of the power-on-reset circuit.

Abstract: A SRAM including an array of memory cell lines and columns, each column being supplied between a high supply voltage and a low supply voltage, which includes at least one MOS transistor in series with each column, and circuitry for applying to the at least one MOS transistor a turn-off control signal to enter a stand-by mode, whereby the overall resistance of the column and of the at least one transistor increases in stand-by mode.

Abstract: A memory array is divided into a plurality of memory sub blocks in row and column directions. A column selection line is provided in the column direction in a region between blocks. A block decoding circuit generating a local column selection signal is arranged corresponding to each of the memory sub blocks. A main I/O line pair group is provided for each of the memory sub blocks and each column of the memory sub block is connected to the corresponding main I/O line pair in accordance with the local column selection line. Thus, data with a desired bit width can be produced without any increase in area occupied by the array nor decrease in the speed of column access.

Abstract: Circuit for erasing and rewriting blocks of memory cells and particularly of analog flash cells, including at least one row decoding circuit including at least two adder blocks, suitable to generate a row address signal, at least two decoder blocks, suitable to generate respective pluralities of signals identifying a respective sector of memory to be enabled, at least two shifter blocks, suitable to generate an address signal of another row to be enabled, at least two OR logic blocks, suitable to generate respective signals serving the purpose to simultaneously enable at least two rows of the memory matrix.

Abstract: A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or −1 arithmetic operation are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

Abstract: In accordance with the present invention a semiconductor memory device includes a connection control circuit controlling a connection between a bit line pair and a data input/output line pair. The connection control circuit includes a flip flop. The connection control circuit responds to a sense amplifier activation signal and a column bank address by setting a level of an interlock signal controlling a gate for electrically connecting the bit line pair and the data input/output line pair together.

Abstract: A memory control circuit for writing or reading digital data at a high speed without increasing access speed to the memory circuit. The memory control circuit includes a control signal generation circuit for generating a first write enable signal and a first read enable signal of a first memory circuit, an address generation circuit for generating an address signal designating a data write address of the first memory circuit and a second memory circuit, and a write data supply circuit for supplying write data to the first and second memory circuits. A shift circuit is connected between the control signal generation circuit and the second memory circuit to generate a second write enable signal and a second read enable signal by shifting the first write enable signal and the first read enable signal by one cycle of a data write cycle or read cycle. The write data is written alternately to the first and second memory circuits in response to the first and second write enable signals.

Abstract: Data transfer between multiple processor nodes and multiple static memory storage nodes is made more efficient using a wrapper of logic surrounding a conventional single port static memory function. The wrapper logic comprises FIFO devices which provide buffering between a given processor node and its associated memory function. The added buffering allows the design to trade allowable added read and write latency for a significant reduction in memory complexity. A single port random access memory structure enclosed within the wrapper provides the functional throughput advantage that only a dual port memory device would otherwise make possible.

Abstract: Rapid data transfer and reduction in power consumption can be achieved by reducing the number of row accesses. A pattern of the memory regions to be selected in memory array is changed by word line mode designation of word line mode control circuit. Memory cells in the same row are selected in a line mode, whereas memory cells in different rows are simultaneously selected in a box mode.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. In one embodiment, the synchronous memory device comprises an array of memory cells arranged in rows and columns. A clock connection is provided to receive an externally provided clock signal. The memory does not require a precharge time period during a time period between the first and second externally provided active commands.

Abstract: A data strobe buffer in SDRAM is disclosed. The data strobe buffer for a synchronous dynamic read only memory (SDRAM), comprising: a first dynamic buffer generating a first pulse at a rising edge of a data strobe signal; a second dynamic buffer generating a second pulse at a falling edge of the data strobe signal; and a block for generating an enable signal which is enabled in a range between a rising edge of an external clock signal and a logic high state of the second pulse, and providing the second dynamic buffer with the enable signal. The data strobe buffer ensures a minimum value of tDQSS parameter in DDR SDRAM even if speed of the chip increases or operation condition of the chip becomes tight, thereby preventing the data strobe buffer from being misoperated due to the damping and the fluctuation of the data strobe signal.

Abstract: A memory device having a plurality of memory cells, the memory device comprising clock receiver circuitry to receive an external clock signal, and input receiver circuitry to sample, in response to a write request, a first portion of data after a number of clock cycles of the external clock signal transpire. The first portion of data is sampled synchronously with respect to the external clock signal.

Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

Abstract: A process for making it possible to detect moving objects by an active sonar operating by the Dopper effect. The process uses, as a transmission signal, a burst of N pulses encoded so as to present a spectrum having a comb-of-lines structure. In this way, the “signal/reverberation” ratio of the useful signal intensity to the reverberated intensity is increased, thereby increasing the efficiency of the sonar. The process allows objects moving in a reverberating transmission medium to be detected more easily.

Abstract: An apparatus for detecting labels on a carrier material has a transmitter that emits ultrasonic waves and a receiver that receives ultrasonic waves. The carrier material is located, with the labels, between the transmitter and the receiver. For detecting the labels, the received signal is compared to a threshold value at the output of the receiver. The threshold value is determined automatically, as a function of the received signal registered during a balancing procedure when the carrier material and/or labels are located between the transmitter and the receiver. In an alternative embodiment of the invention, the apparatus is used to distinguish between single and multiple sheets.

Abstract: A system is provided for determining range to a wave energy source. The system includes a transmitter for transmitting a burst of pulses of wave energy in response to a trigger signal. A receiver is provided for determining a time of arrival of the burst and from such determined time of arrival, the range to the wave energy source. The receiver includes: an envelope detector for detecting an envelope of the burst; a network for producing an output in response to an early point on the detected envelope occurring prior to a peak in the detected envelope; a timer, responsive to the trigger signal and the network output for determining the time of arrival of the burst; and a processor, responsive to such determined time of arrival, for determining the range of the wave energy source from the transmitter.

Abstract: A system and method are provided for converting an electrical signal to an optical signal for a fiber optic system. The electrical signal produced by a sensor (10) based upon a parameter being measured is connected across a material (12, 34, 40) that changes dimension responsive to an applied electrical signal. An optical fiber (14, 30, 38) is coupled to the material (12, 34, 40) where dimension changes of the material (12, 34, 40) produce strain in the optical fiber (14, 30, 38). This strain is operable to affect light traveling through the optical fiber (14, 30, 38) to produce an optical signal for a fiber optic system. In one embodiment, the sensor (10) can be a geophone sensor that produces an electrical signal proportional to motion of the geophone sensor. In another embodiment, the sensor (10) can be a hydrophone sensor that produces an electrical signal proportional to acoustic pressure incident on the hydrophone sensor.

Abstract: A plurality of applications for a micro-machined ultrasonic transducer (MUT) including an improved MUT array containing optimized transmit MUT elements and optimized receive MUT elements, a MUT array in which staggered MUT elements increase the sensitivity of the array, and a MUT array for multiple plane scanning.

Abstract: A health watch is disclosed which has various functions such as atmospheric air thermometer, body thermometer, cardiac beat meter, displaying of beating sound waves, display of cardiac beating sounds, blood pressure meter and the like. An IC counting element is provided for each of the functions, and a plurality of display windows are provided to display the respective measured data. For this purpose, sensors are installed on the watch in contact with the wrist. Thus the various functions are combined in one wrist watch, so that a convenience would be ensured by eliminating the troubles of carrying and storing the various conventional separate health checking devices. Therefore, one's own health state can be checked at any place, thereby making it possible to prevent assault of any disease.

Abstract: A timepiece includes a mechanical energy source, a generator, and a train wheel connecting the mechanical energy source and the generator. The mechanical energy source drives the train wheel to cause the generator to rotate thereby creating electrical power. A rotation controller coupled to the generator controls the rotation of the generator, and includes a rotation detector for detecting the rotation of the generator and generating a rotation signal corresponding to the rotation and a reference signal generator for generating a reference signal based on a signal from a time reference source. The brake controller counts the reference signal and produces a first count, counts the rotation signal and produces a second count, and brakes the rotation of the generator when the first count is less than the second count.