Patents Issued in November 8, 2001
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Publication number: 20010038070Abstract: The invention relates to the simultaneous analysis of variations in distinct nucleic acid sequences within a complex nucleic acid mixture. The invention consists in the use of chips with spatially separated fields of photocleavable oligonucleotide probes which are commonly processed together with the target sequences and thereby modified in a sequence-dependent way. The probes are cleaved and analyzed by laser desorption mass spectrometry. This allows highly parallel and nevertheless sequence-specific reactions within a single reaction mixture. Since the photocleavable oligonucleotide probes are placed on a substrate in a spatially defined manner, e.g. in the form of an array, a specific target sequence can be assigned a unique position on the oligonucleotide chip. Since the photocleavable probes are covalently immobilized on the solid surface, the detection reaction can be performed directly on the chip while preserving the probe position pattern.Type: ApplicationFiled: March 26, 2001Publication date: November 8, 2001Inventors: Felix Hausch, Andres Jaschke
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Publication number: 20010038071Abstract: While a large primary stream (24) of analytes flow from a chromatographic column (20) to containers of a receiver (108), small samples of the analytes are diverted for flow to a mass spectrometer (54) for analysis, by use of a transfer module (102). The transfer module includes a stator (110) and a rotor or shuttle (114). The shuttle has an aliquot passage (120) that initially lies in a first position where the primary stream flows through it so the aliquot passage receives a small sample. The shuttle then moves to a second position where the aliquot passage (at 122) is aligned with a pump (134) that pumps fluid out of the aliquot passage to the mass spectrometer.Type: ApplicationFiled: April 13, 2001Publication date: November 8, 2001Inventors: Jon A. Nichols, Marc D. Foster
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Publication number: 20010038072Abstract: An apparatus and method are provided for processing the images obtained from an atomic force microscopy when profiling high aspect ratio features. A deconvolution technique for deconvolving the sample image includes the use of multiple images but does not require exact calibration of the scanning probe. In one embodiment, erosion and dilation techniques are used to obtain an undistorted image of the sample being measured. In another embodiment, Legendre transforms are used to obtain an undistorted image of the sample being measured. Also described is a technique for measuring the tip radius of the scanning probe.Type: ApplicationFiled: February 21, 2001Publication date: November 8, 2001Inventors: Bernardo D. Aumond, Kamal Youcef-Toumi
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System and method for automatically tensioning wires and for retaining tensioned wires under tension
Publication number: 20010038073Abstract: A wire tensioning apparatus and method tensions one or more wires by moving the tensioning function from a wire module to an apparatus external to the wire module. Within the wire module, the wire is placed between a movable member and a stationary member. Tension is placed on the wire and adjusted until the desired tension and/or vibrational frequency is met. Once the desired tension and/or vibrational frequency is met, the wire is clamped between the movable and stationary members within the wire module in order to maintain the achieved tension and/or vibrational frequency.Type: ApplicationFiled: March 6, 2001Publication date: November 8, 2001Applicant: XEROX CORPORATIONInventors: Leopold B. Dondiz, Timothy C. Warren, Patricia Moran -
Publication number: 20010038074Abstract: A system for emitting and detecting terahertz frequency electromagnetic pulses. The system comprises a single transceiver device, which may be an electro-optic crystal or photoconductive antenna, for both emitting and detecting the pulses. A related method comprises using a single transceiver device to both emit and detect electromagnetic terahertz frequency pulses. The transceiver device is excited by a pump pulse to emit a terahertz output pulse, which is modulated with a chopper. An object reflects the terahertz pulse and the reflected pulse is detected in the transceiver using a probe pulse. A lock-in amplifier set to the same frequency of the chopper is used to reduce noise in the signal detected by the transceiver. An image of the object may be created using the intensity or the timing of the peak amplitude of the terahertz pulses reflected from the object.Type: ApplicationFiled: April 5, 2001Publication date: November 8, 2001Inventors: X.-C. Zhang, Masahiko Tani, Zhiping Jiang, Qin Chen
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Publication number: 20010038075Abstract: An electromagnetic wave detector or an area image sensor comprises a number of pixel units arranged into a matrix form and each pixel unit includes a conversion element for converting incident electromagnetic waves or high energy radiations into an electric charge, a storage capacitor for storing the electric charge produced by the conversion element, a thin film read transistor connected to the storage capacitor, and a thin film reset transistor also connected to the storage capacitor. The pixel units are operated in a storage-read-reset cycle on a row by row basis so that any electric charge left after the read period is expelled in the reset period.Type: ApplicationFiled: March 26, 2001Publication date: November 8, 2001Inventor: Masakazu Morishita
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Publication number: 20010038076Abstract: In a radiation detector: a CsI:Tl (or CsI:Na) scintillator receives a number X of radiation quantums for each pixel, and emits a number L of photons constituting fluorescent light in response to each radiation quantum; photoelectric converters containing Si (or Se) as a main component are arranged corresponding to respective pixels to receive the fluorescent light with an entrance efficiency T, and generate charges when the fluorescent light is detected; and a capacitor is connected to each photoelectric converter, and stores the charges generated by the photoelectric converter. When the radiation detector receives a 10 to 300 mR dose of the radiation, the numbers X and L, the entrance efficiency T, the fill factor F and the photoelectric conversion efficiency &eegr; of each photoelectric converter, and the maximum storable charge amount Q of the capacitor satisfy a relationship X·L·T·F·&eegr;≦Q.Type: ApplicationFiled: April 16, 2001Publication date: November 8, 2001Inventor: Takao Kuwabara
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Publication number: 20010038077Abstract: The present invention provides an improved electron ionizer for use in a quadrupole mass spectrometer. The improved electron ionizer includes a repeller plate that ejects sample atoms or molecules, an ionizer chamber, a cathode that emits an electron beam into the ionizer chamber, an exit opening for excess electrons to escape, at least one shim plate to collimate said electron beam, extraction apertures, and a plurality of lens elements for focusing the extracted ions onto entrance apertures.Type: ApplicationFiled: July 10, 2001Publication date: November 8, 2001Applicant: California Institute of Technology, a non-profit organizationInventors: Ara Chutjian, Murray R. Darrach, Otto J. Orient
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Publication number: 20010038078Abstract: Device and method of treatment of light obtained from X-rays, comprising a means of filtering the light with a cutoff frequency such that a first part of the spectrum of the light emitted by a light emitter is preserved, the first part of the spectrum being independent of temperature, and a second part of the light spectrum is stopped, the second part of the spectrum presenting a shift dependent on temperature. The invention also concerns an imaging cassette, a dose measuring module and a radiology apparatus.Type: ApplicationFiled: April 4, 2001Publication date: November 8, 2001Inventor: Uwe Wiedmann
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Publication number: 20010038079Abstract: Disclosed are a method and an apparatus for irradiating low energy ion beam on polymer. The method prepares polymer products having a surface electric conductivity range, in surface electric resistance, from 106 to 1011 &OHgr;/sq, by vacuum-irradiating the ions under relatively low energy of 50-100 keV from ion sources which generates high-current ions of several tens mA or higher, to polymer materials, such as PPO and MPPO, which are electrically insulator; precisely controls temperature so as not to thermally deform molecular configuration of the polymers; produces the products with uniform and stable conductivity in a large area; and treats the surface which improves surface hardness and modifies mechanical properties. Further, the mass-production apparatus for irradiating the ion beams is capable of commercially realizing said method. Accordingly, ions, inert gases (nitrogen, oxygen, argon, xenon, helium, etc.Type: ApplicationFiled: February 23, 2001Publication date: November 8, 2001Inventors: Jang-Ho Ha, Byoung-Ho Choi, Yong-Sub Cho, Jae-Hyung Lee, Jae-Sang Lee, Po-Guk Joo
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Publication number: 20010038080Abstract: Charged-particle-beam (CPB) optical systems (especially projection-lens systems for use in CPB microlithography apparatus) are disclosed that exhibit excellent control of geometric aberration and the Coulomb effect while exhibiting low combined aberration and blur. As the column length of the projection-lens system is increased, geometric aberration is reduced but the Coulomb effect increases, which degrades overall optical characteristics. Conversely, as the column length is decreased, the Coulomb effect is reduced but geometric aberration increases, which degrades overall optical characteristics. Hence, the projection-lens system, exhibiting a magnification of 1/M and having a column length (distance in mm between reticle and wafer) of 250×M0.63±110% (wherein 0<M; e.g., 0<M<4 or 4<M) exhibits blur and geometric distortion of about 70 nm or less and about 4 nm or less, respectively.Type: ApplicationFiled: April 26, 2001Publication date: November 8, 2001Applicant: Nikon CorporationInventors: Atsushi Yamada, Hiroyasu Simizu, Koichi Kamijo
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Publication number: 20010038081Abstract: An optocoupler driver circuit comprises an optocoupler (OC) with a light-emitting device (D) and a photosensitive device (T). A current source (CS) supplies a current (Is) to both the light-emitting device (D) and an impedance (Z). The ratio of the current (Id) through the light-emitting device (D) and the resulting current (Ic) through the photosensitive device (T) decreases if the temperature increases. The voltage (Vd) across the light-emitting device (D) also decreases if the temperature increases. The decrease of the voltage (Vd) across the light-emitting device (D) causes the current (Iz) through the impedance (Z) to decrease. Consequently, the current (Id) through the light-emitting device (D) increases and counteracts the decreasing ratio.Type: ApplicationFiled: April 5, 2001Publication date: November 8, 2001Applicant: KONINKLIJKE ELECTRONICS N. V.Inventor: Erik Maria Hendrik De Wulf
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Publication number: 20010038082Abstract: An electrically controlled fluid control valve comprises an electrical position controller governed by a signal proportional to the position of a movable element of the valve to regulate current to a shape memory alloy (SMA) valve actuator to position the movable element to a desired position. The control valve may also include a temperature controller governed by a signal provided by a temperature-sensing element in proximity to the valve actuator to activate a cooling device for reducing the surrounding temperature. A digital selector switch may be used for generating a digital code of a selected heating rate which may govern the electrical controller to regulate current to the SMA drive element. The electrical controller may also be governed by both position measurement and a temperature signals to regulate current to the SMA valve actuator and to control the cooling device to position the movable element to a desired position.Type: ApplicationFiled: April 11, 2001Publication date: November 8, 2001Inventors: Antonio Hines, Theodore J. Gausman, William H. Glime, Steven H. Hill, Bruce S. Rigsby
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Publication number: 20010038083Abstract: The piezoelectric element laminate 20 which expands due to application of a voltage is disposed between a diaphragm valve 11 applied with elastic force in a valve opening direction and a valve spring mechanism 25, a distortion amount a of the piezoelectric element laminate 20 in expansion is set to be larger than an opening/closing stroke b of the diaphragm valve 11, and a spring seat 28 separates from a second stopper 30 due to a difference c between the distortion amount a and the opening/closing stroke b. As a result, when the piezoelectric element laminate 20 expands to seat the diaphragm valve 11 on a valve seat 10, the valve spring 29 is compressed and repulsing force of the valve spring 29 acts on the diaphragm valve 11 through the piezoelectric element laminate 20 and the diaphragm valve 11 is pressed against the valve seat 10 by the repulsing force.Type: ApplicationFiled: April 18, 2001Publication date: November 8, 2001Applicant: SMC CorporationInventor: Toyonobu Sakurai
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Publication number: 20010038084Abstract: A valve for controlling the flow of a fluid comprises a housing, a flow-control element disposed within the housing, at least one seat operably engaging the flow-control element, and a biasing device for urging the seat and the flow-control element relative toward each other. In some embodiments, the valve also includes an actuating device operably engaging the flow-control element. The flow-control element, the seat, and the biasing device are comprised of a refractory material, and at least the biasing device is formed of a toughened refractory or ceramic material that is fully annealed so that porosity in the material is substantially eliminated and such that the material is substantially homogenous. In some embodiments, the seat, the flow-control element, the biasing device, and/or other components may be advantageously fabricated together as a unitary structure. An associated fabrication method is also provided.Type: ApplicationFiled: February 1, 2001Publication date: November 8, 2001Applicant: University of AlabamaInventors: James Edwin Smith, George O. Ellis, David Todd Ellis
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Publication number: 20010038085Abstract: An aqueous leather coating composition and a method for coating leather with the aqueous coating composition are provided. The aqueous coating composition contains an aqueous emulsion polymer which includes from 0.4% to 10% by weight of a copolymerized acetoacetate or acetoacetamide monomer and has a glass transition temperature from −20° C. to 10° C. In an alternative embodiment the aqueous coating composition contains an aqueous emulsion polymer which includes from 0.1% to 6% by weight of a copolymerized acetoacetate or acetoacetamide monomer and from 2% to 15% by weight of copolymerized carboxylic acid monomer and has a glass transition temperature from −40° C. to 0° C., the polymer having been contacted with a transition metal oxide, hydroxide, or carbonate at a pH less than 9 in an amount greater than 0.20 equivalent of transition metal per equivalent of copolymerized carboxylic acid monomer.Type: ApplicationFiled: May 31, 2001Publication date: November 8, 2001Inventors: Patricia Marie Lesko, Frederick James Schindler
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Publication number: 20010038086Abstract: In a composite magnetic body comprising flat soft magnetic powder dispersed in an organic binding agent, bio-composable plastic is used as the organic binding agent so that the composite magnetic body is free of possibility of pollution due to disposal thereof. As the bio-composable plastic, any of a microbe type, a chemical synthesis type and a natural high molecular type is used.Type: ApplicationFiled: March 27, 2001Publication date: November 8, 2001Inventors: Shigeyoshi Yoshida, Norihiko Ono
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Publication number: 20010038087Abstract: A novel chemical species, called magnecules, which is composed of clusters of molecules, and/or dimers, and/or atoms formed by internal bonds due to the magnetic polarization of the orbits of at least some of the peripheral atomic electrons present in the cluster, the intrinsic magnetic field of nuclei present in the cluster, and the intrinsic magnetic fields of valence electrons present in the cluster that are not correlated in singlet couplings to other electrons to form valence bonds is disclosed.Type: ApplicationFiled: April 4, 2001Publication date: November 8, 2001Applicant: Hadronic Press, Inc.Inventor: Ruggero Maria Santilli
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Publication number: 20010038088Abstract: A high quality lubricant for compressors operated during at least part of their compression cycle at temperatures above normal human comfort temperatures, such as most automotive air conditioners, especially those using chlorine free hydro-fluorocarbon refrigerant working fluids, is provided by mixed esters of hindered polyols, most desirably pentaerythritol, with a mixture of carboxylic acids including at least some iso-pentanoic acid along with one or more of iso-nonanoic acid, isooctanoic acid, and dibasic acids such as adipic. When the mixture includes about 7% adipic and amounts of branched C8-9 and C5 monobasic acids in a ratio of at least 0.75:1.00, the esters formed have excellent solubility for paraffinic and naphthenic mineral oils and are therefore especially well suited for lubricating vehicle air conditioners formerly containing chlorine containing heat transfer fluids and mineral oil lubricants.Type: ApplicationFiled: January 30, 2001Publication date: November 8, 2001Inventor: Nicholas E. Schnur
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Publication number: 20010038089Abstract: Ashing of an organic film from a substrate is carried out by providing a plasma comprising a gas or gas mixture selected from the following groups: (a) sulfur trioxide alone; (2) sulfur trioxide plus one supplemental gas; and (3) sulfur trioxide plus at least two supplemental gases. Any of the following gases may be employed as the supplemental gas: oxygen, ozone, hydrogen, nitrogen, nitrogen oxides, helium, argon, or neon. Also, a process is provided for forming a plasma in a reaction chamber from reactant gases containing suffur trioxide. The process includes introducing the sulfur trioxide into the reaction chamber from a storage vessel through a delivery manifold by independently heating the storage vessel and the delivery manifold to a temperature sufficient to maintain the sulfur trioxide in its gaseous state or liquid state and by heating the reaction chamber to control the reaction rate of the sulfur trioxide and also control condensation of the sulfur trioxide to maintain a stable plasma state.Type: ApplicationFiled: March 30, 2001Publication date: November 8, 2001Applicant: Anon, Inc.Inventors: Eric O. Levenson, Ahmad Waleh
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Publication number: 20010038090Abstract: The present invention is directed to a novel etching process for a semiconductor material which inhibits corrosion of metal comprised of pretreating the material, preferably with a surfactant, and then exposing the material to a mixture comprising salt, a buffered oxide etch, and optionally a surfactant.Type: ApplicationFiled: September 8, 1998Publication date: November 8, 2001Inventors: ROBERT T. RASMUSSEN, SURJIT S. CHADHA, DAVID A. CATHEY
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Publication number: 20010038091Abstract: The present invention provides a liquid crystal composition comprising the compounds represented by the following formulas (I) and (II) 1Type: ApplicationFiled: March 15, 2001Publication date: November 8, 2001Inventors: Motoki Yanai, Yasuhiro Kubo, Etsuo Nakagawa
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Publication number: 20010038092Abstract: The present invention provides liquid crystalline compounds having a high voltage holding ratio and a low threshold voltage, little variation of these properties with temperature change, high &Dgr;n, and good compatibility with other liquid crystal materials particularly under a low temperature; liquid crystal compositions containing these crystalline compounds; and liquid crystal display devices made using these liquid crystal compositions.Type: ApplicationFiled: April 18, 2001Publication date: November 8, 2001Applicant: CHISSO CORPORATIONInventors: Tomoyuki Kondou, Shuichi Matsui, Kazutoshi Miyazawa, Hiroyuki Takeuchi, Yasuhiro Kubo, Fusayuki Takeshita, Etsuo Nakagawa
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Publication number: 20010038093Abstract: An interface material comprising a resin mixture and at least one solder material is herein described. The resin material may comprise any suitable resin material, but it is preferred that the resin material be silicone-based comprising one or more compounds such as vinyl silicone, vinyl Q resin, hydride functional siloxane and platinum-vinylsiloxane. The solder material may comprise any suitable solder material, such as indium, silver, copper, aluminum and alloys thereof, silver coated copper, and silver coated aluminum, but it is preferred that the solder material comprise indium or indium-based compounds and/or alloys. The interface material, or polymer solder, has the capability of enhancing heat dissipation in high power semiconductor devices and maintains stable thermal performance. The interface material may be formulated by mixing the components together to produce a paste which may be applied by dispensing methods to any particular surface and cured at room temperature or elevated temperature.Type: ApplicationFiled: May 7, 2001Publication date: November 8, 2001Applicant: Honeywell International Inc.Inventor: My Nguyen
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Publication number: 20010038094Abstract: A portable, compact cart easily lifts and maneuvers heavy vehicle wheels for removal, repair, transportation, and the like. The cart includes a U-shaped bracket with opposing arms slidably interconnected along a straight center section. In addition to wheels beneath the cart, rollers are mounted atop the arms. For example, each arm may include a paired set of rollers forming a V-shape when viewed from the cart's top or end. When an upright wheel is cradled by opposing arms, the rollers help keep the wheel upright. A user-activated push/pull assembly is attached to both arms to slidably lengthen and shorten the center section, thereby drawing the arms together (lifting the wheel) or spreading the arms apart (releasing the wheel). The push/pull assembly may use a lever whose distal end is pivotally coupled to one of the arms along the straight center section.Type: ApplicationFiled: May 4, 2000Publication date: November 8, 2001Applicant: Execair Maintenance Inc.Inventors: Donald Eugene Lundy, Donald Eugene Lundy
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Publication number: 20010038095Abstract: In a case where a thinning operation is implemented at the point when signal charges are read out from each of pixels to thin out pixel information by lines (row), the thinning may be performed only in the vertical direction, but not in the horizontal direction. In an all-pixel-read-out type CCD image pickup element, a discharge controlling section is provided in each of VH transfer stage sections transferring signal charges from vertical CCDs to a horizontal CCD, and where a thinning mode is selected, among those signal charges transferred from a plurality of the vertical CCDs, those of a given set of columns are stopped and discharged at the respective discharge controlling sections, and those of the rest of columns are transferred to the horizontal CCD, and at the same time, those of a given set of lines (rows) are stopped and discharged for all columns, thereby performing the thinning operation over the pixel information in both the vertical and horizontal directions at the VH transfer stage.Type: ApplicationFiled: February 23, 2001Publication date: November 8, 2001Inventor: Masaharu Hamasaki
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Publication number: 20010038096Abstract: A circuit-incorporating light receiving device comprises a first semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of the first conductivity type, a diffusion region of the second conductivity type, provided in a first portion of the second semiconductor layer of the first conductivity type, a circuit element provided in the first portion of the first semiconductor layer of the first conductivity type and a second portion of the second semiconductor layer of the first conductivity type. The second semiconductor layer of the first conductivity type and the diffusion region of the second conductivity type form a light detection photodiode portion, and the diffusion region of the second conductivity type has a diffusion depth less than or equal to a penetration depth of short-wavelength signal light.Type: ApplicationFiled: March 29, 2001Publication date: November 8, 2001Inventors: Toshihiko Fukushima, Masaru Kubo, Shigeki Hayashida
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Publication number: 20010038097Abstract: In a TFT including on the surface side of a substrate a channel region opposed to a gate electrode, with a gate insulating film provided therebetween, and a source-drain region connected to the channel region, and a TFT including a source-drain wiring layer electrically connected to the source-drain region, and a gate wiring layer electrically connected to the gate electrode, at least one component part composed of a conductive film or a semiconductor film, among the component parts of each TFT, is provided with a heat-radiating extension extended from the component part itself for enhancing the heat-radiating efficiency from the component part.Type: ApplicationFiled: May 26, 1998Publication date: November 8, 2001Inventor: SATOSHI INOUE
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Publication number: 20010038098Abstract: There is provided an EL light-emitting device with less uneven brightness.Type: ApplicationFiled: February 27, 2001Publication date: November 8, 2001Inventors: Shunpei Yamazaki, Jun Koyama, Mai Osada
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Publication number: 20010038099Abstract: Two kinds of a thin film semiconductor unit are disposed over a substrate. A first thin film semiconductor unit includes a polycrystalline semiconductor thin film, and a second thin film semiconductor unit includes an amorphous semiconductor thin film.Type: ApplicationFiled: March 19, 2001Publication date: November 8, 2001Applicant: Semiconductor Energy Laboratory Co., Ltd. a Japanese corporationInventors: Shunpei Yamazaki, Toshiji Hamatani, Takeshi Fukada
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Publication number: 20010038100Abstract: An application-specific rf optoelectronic integrated circuit having a generic chip member and a defining substrate in communication with at least one generic chip member. The generic chip member contains passive building block components that are independent from each other and being connected by paths external to the generic chip member. The external connection paths are defined by a defining substrate member having passive components for providing optical and electrical interconnection between selected building block components on the generic chip member to define the specific function of the integrated circuit. It is possible to use the same design of the generic chip for several applications merely by altering the interconnect paths on a defining substrate.Type: ApplicationFiled: May 25, 2001Publication date: November 8, 2001Applicant: Hughes Electronics CorporationInventor: Daniel Yap
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Publication number: 20010038101Abstract: A semiconductor light emitting device having a plurality of semiconductor light emitting elements of different emission wavelengths capable of reducing the number of parts and simplifying the configuration of an optical system, comprising a substrate and at least two stacks each comprised of an epitaxial growth layer comprised of at least a first conductivity type clad layer, an active layer, and a second conductivity type clad layer on the substrate, the stacks being spatially separated, the compositions of at least the active layers being different between the stacks, and a plurality of types of light having mutually different wavelengths being emitted from the active layers in parallel with the substrate and in substantially the same direction, and a method for producing the same.Type: ApplicationFiled: December 17, 1999Publication date: November 8, 2001Inventor: KAZUHIKO NEMOTO
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Publication number: 20010038102Abstract: A light emitting device comprising a substrate having first and second regions, a first non-transparent electrode formed on the substrate in the first region, a layer of organic light emitting material provided over the first non-transparent electrode in the first region, a layer of organic light emitting material provided over the substrate in the second region, the light emitting materials each having at least one planar surface which is corrugated, a second non-transparent electrode formed over the light emitting material in the first region, and a mirror formed over the light emitting material in the second region. A device having a stacked structure of electrodes and light emitting layers is also disclosed, as are various methods of fabricating the devices.Type: ApplicationFiled: April 12, 2001Publication date: November 8, 2001Inventor: Takeo Kawase
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Publication number: 20010038103Abstract: An electrode of a metal, which is one of Group IV and VI elements, is deposited on an n-type InxAlyGa1-x-yN layer. Alternatively, after an electrode material of carbon, germanium), selenium, rhodium, tellurium, iridium, zirconium, hafnium, copper, titanium nitride, tungsten nitride, molybdenum or titanium silicide, is deposited on an n-type InxAlyGa1-x-yN layer or a p-type InxAlyGa1-x-yN layer, an impurity for increasing the carrier concentration of the semiconductor layer is ion-implanted, and the annealing is carried out. Thus, it is possible to provide a light emitting semiconductor device, which has a low contact resistance and a sufficient bond strength to the InxAlyGa1-x-yN layer while maintaining the crystallinity of the InxAlyGa1-x-yN layer.Type: ApplicationFiled: July 2, 2001Publication date: November 8, 2001Applicant: Kabushiki Kaisha ToshibaInventors: Koichi Nitta, Haruhiko Okazaki, Tokuhiko Matsunaga
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Publication number: 20010038104Abstract: In a multilayer logic device or processor device with a plurality of individually matrix-addressable stacked thin layers of an active material, the active material in each layer is provided between a first electrode set and a second electrode set wherein the electrodes in the first set realize the columns and the electrodes in the second set the rows in an orthogonal array. The intersections between the electrodes in the array define logic cells in the layer of active material, and the stacked layers of active material are provided on a common supporting substrate. A separation layer with determined electrical or thermal properties is provided between each layer of active material.Type: ApplicationFiled: February 22, 1999Publication date: November 8, 2001Inventors: HANS GUDE GUDESEN, PER-ERIK NORDAL
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Publication number: 20010038105Abstract: The state of a polysilicon film formed by excimer laser annealing an amorphous silicon film is to be evaluated. When the amorphous silicon film is annealed to form a polysilicon film, linearity or periodicity presents itself in the spatial structure of the film surface of the polysilicon film formed depending on the energy applied to the amorphous silicon during annealing. This linearity or periodicity is processed as an image and represented numerically from the image by exploiting the linearity or periodicity. The state of the polysilicon film is checked based on the numerical results.Type: ApplicationFiled: January 8, 2001Publication date: November 8, 2001Inventors: Hiroyuki Wada, Yoshimi Hirata, Ayumu Taguchi, Koichi Tatsuki, Nobuhiko Umezu, Shigeo Kubota, Tetsuo Abe, Akifumi Ooshima, Tadashi Hattori, Makoto Takatoku, Yukiyasu Sugano
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Publication number: 20010038106Abstract: The invention teaches a technique for A C equilibration of the signaling levels and time of 1—>h and h—>1 transitions of CMOS drivers as received at CMOS receivers, so as to improve the rate at which data can be communicated between two CMOS devices.Type: ApplicationFiled: March 27, 2001Publication date: November 8, 2001Inventors: Paul William Coteus, Alan Gene Gara
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Publication number: 20010038107Abstract: In a gate array, a gate length is measured by dividing gate electrodes into groups according to their materials to distinguish between those groups. The shape of a contact pad portion (5) of a gate electrode (4) differs according to the groups. A difference described here appears as shape such as cutouts (6a-6c) or projections (6d-6f), which is distinguishable by a scanning electron microscope, for example.Type: ApplicationFiled: July 17, 2001Publication date: November 8, 2001Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Shigenobu Maeda
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Publication number: 20010038108Abstract: There are provided a field effect transistor with a high withstand voltage and low loss and a method of manufacturing the same. The field effect transistor includes an n-type substrate, an n-type semiconductor layer formed on the n-type substrate, a p-type semiconductor layer formed on the n-type semiconductor layer, a p-type region embedded in the n-type semiconductor layer, an n-type region embedded in the n-type semiconductor layer and the p-type semiconductor layer, an n-type source region disposed in the p-type semiconductor layer on its surface side, an insulating layer disposed on the p-type semiconductor layer, a gate electrode disposed on the insulating layer, a source electrode, and a drain electrode. The n-type semiconductor layer, the p-type semiconductor layer, and the p-type region are made of wide-gap semiconductors with a bandgap of at least 2eV, respectively.Type: ApplicationFiled: April 3, 2001Publication date: November 8, 2001Inventors: Makoto Kitabatake, Toshiya Yokogawa, Osamu Kusumoto, Masao Uchida, Kunimasa Takahashi
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Publication number: 20010038109Abstract: A resistive ferroelectric memory cell includes a selection transistor having first and second zones of a first conduction type. A storage capacitor has one electrode at a fixed cell-plate voltage and another electrode connected to the first zone of the selection transistor. A semiconductor substrate has a second conduction type opposite the first conduction type. The storage capacitor and the selection transistor are disposed in the semiconductor substrate. A resistor is disposed between the other electrode of the storage capacitor and the fixed cell-plate voltage. The resistor has a resistance R2 such that R3<<R2<<R1, in which R1 is a reverse resistance of a pn junction between the first zone of the selection transistor and the semiconductor substrate and R3 is a resistance between the first zone and the second zone of the selection transistor, in a turned-on state.Type: ApplicationFiled: January 22, 2001Publication date: November 8, 2001Inventors: Oskar Kowarik, Kurt Hoffmann
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Publication number: 20010038110Abstract: A dynamic random access memory (DRAM) includes a plurality of memory cells aligned with one another along a pair of wordlines with each wordline being connected to access alternate ones of the memory cells. The DRAM has aligned memory cells having cell areas of 6F2 yet exhibiting substantially the same superior signal-to-noise performance found in DRAM's having staggered 8F2 memory cells. The DRAM memory cells are formed by transistor stacks which are aligned along and interconnected by wordlines extending between and included within the transistor stacks. By forming the wordlines as a part of the transistor stacks, the wordlines are narrow ribbons of conductive material. During formation of the transistor stacks, the wordlines are connected so that a first wordline controls access transistors of every other one of the memory cells and a second wordline controls the access transistors of the remaining memory cells.Type: ApplicationFiled: December 11, 2000Publication date: November 8, 2001Inventors: Darwin A. Clampitt, James E. Green
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Publication number: 20010038111Abstract: An etching method includes providing a first insulating material layer on a substrate assembly surface and a second insulating material layer on the first insulating material layer. The first insulating material layer has an etch rate that is greater than the etch rate of the second insulating material layer when exposed to an etch composition. Portions of the first insulating material layer and the second insulating material layer are removed using at least the etch composition. Various types of structures (e.g., contacts, capacitors) are formed with use of the method.Type: ApplicationFiled: May 23, 2001Publication date: November 8, 2001Applicant: Micron Technology, Inc.Inventors: Scott J. DeBoer, Terry L. Gilton, Ceredig Roberts
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Publication number: 20010038112Abstract: Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of intrinsically conductive recrystallization barrier layers. The intrinsically conductive layers are preferably used adjacent to conductive strap features in trench capacitors to act as recrystallization barriers.Type: ApplicationFiled: June 21, 2001Publication date: November 8, 2001Applicant: International Business Machines CorporationInventors: Jeffrey P. Gambino, Rajarao Jammy, Jack A. Mandelman, Carl J. Radens
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Publication number: 20010038113Abstract: A dynamic random access memory (DRAM) cell comprising a deep trench storage capacitor having an active transistor device partially disposed on a side wall of the trench. The side wall is aligned to a first crystallographic plane having a crystallographic orientation along a single crystal axis. A process for manufacturing such a DRAM cell comprises: (a) forming a deep trench in a substrate, (b) forming a faceted crystal region along the trench side wall having a single crystallographic orientation, and (c) forming a transistor device partially disposed on the faceted crystal region in the side wall. The faceted crystal region may be formed by growing an oxide collar, such as by local thermal oxidation under oxidation conditions selected to promote a higher oxidation rate along a first family of crystallographic axes than along a second family of crystallographic axes.Type: ApplicationFiled: June 28, 2001Publication date: November 8, 2001Inventors: Gary Bronner, Ulrike Gruening, Jack A. Mandelman, Carl J. Radens
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Publication number: 20010038114Abstract: Plug electrodes of silicon are formed being buried in the through holes in a first insulating film, the plug electrodes being electrically connected to the source and drain regions of a MISFET on the main surface of a semiconductor substrate. Then, a second insulating film is deposited thereon and holes are formed therein such that the plug electrodes of silicon are exposed. A barrier film is formed on the surfaces of the silicon plugs, and in the holes are formed a dielectric to form lower electrodes of the capacitor elements and an upper electrode therefor.Type: ApplicationFiled: February 5, 2001Publication date: November 8, 2001Inventors: Shinpei IIjima, Yoshitaka Nakamura, Masahiko Hiratani, Yuichi Matsui, Naruhiko Nakanishi
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Publication number: 20010038115Abstract: A capacitive element structure in a semiconductor device having an interconnection structure. The capacitive element structure includes a capacitive element having a capacitive dielectric film made of an oxide compound. The capacitive element structure is above at least a bottom level interconnection of the interconnection structure.Type: ApplicationFiled: July 12, 2001Publication date: November 8, 2001Applicant: NEC Corporation of Tokyo, JapanInventor: Kazushi Amanuma
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Publication number: 20010038116Abstract: A silicon structure is formed that includes a free-standing wall having opposing roughened inner and outer surfaces using ion implantation and an unimplanted silicon etching process which is selective to implanted silicon. In general, the method provides a recess in a layer of insulating material into which a polysilicon layer is formed. A layer of HSG or CSG polysilicon is subsequently formed on the polysilicon layer, after which ions are implanted into both the layer of HSG or CSG polysilicon and the underlying polysilicon layer. The aforementioned selective etching process is then conducted to result in a relatively unimplanted portion being etched away and a highly implanted portion being left standing to form the free-standing wall. The free-standing wall has an inner surface that is roughened by the layer of HSG or CSG polysilicon. The free-standing wall also has a roughened outer surface to which has been transferred a near-impression image topography of the opposing inner surface.Type: ApplicationFiled: July 2, 2001Publication date: November 8, 2001Inventors: Thomas A. Figura, Zhiqiang Wu, Li Li
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Publication number: 20010038117Abstract: A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric layer. In addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are configured between the source/drain regions. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.Type: ApplicationFiled: March 7, 2001Publication date: November 8, 2001Inventors: Thomas Peter Haneder, Hans Reisinger, Reinhard Stengl, Harald Bachhofer, Hermann Wendt, Wolfgang Hnlein
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Publication number: 20010038118Abstract: A trench region 14 is formed in a memory cell P-type well 13. Two NAND-type memory cell units ND1 and ND2 are respectively formed along both side wall portions of this trench region 14. A floating gate FG and a control gate CG in these NAND-type memory cell units ND1 and ND2 are formed self-aligningly without using a photoresist. One bit line BL connected to the two NAND-type memory cell units ND1 and ND2 is formed via an interlayer dielectric 30. The bit line pitch of this bit line BL is set at 2 F. Hence, the size of a nonvolatile semiconductor memory can be reduced.Type: ApplicationFiled: March 23, 2001Publication date: November 8, 2001Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koji Sakui, Toshiharu Watanabe
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Publication number: 20010038119Abstract: A method of manufacturing a semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions. By this method, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but, however, a lower dose of arsenic is introduced in the formation of the second semiconductor region. The first semiconductor region is formed to have a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. Carriers stored in the floating gate electrode are transferred between the floating gate electrode and the first semiconductor region by tunneling through the insulating film beneath the floating gate electrode. The method further features the formation of MISFETs of peripheral circuits.Type: ApplicationFiled: June 5, 2001Publication date: November 8, 2001Inventors: Kazuhiro Komori, Toshiaki Nishimoto, Satoshi Meguro, Hitoshi Kume, Yoshiaki Kamigaki