Abstract: InxGa1−xAs structures with compositionally graded buffers grown with organometallic vapor phase epitaxy (OMPVE) on GaAs substrates. A semiconductor structure and a method of processing such a structure including providing a substrate of GaAs; and epitaxially growing a relaxed graded layer of InxGa1−xAs at a temperature ranging upwards from about 600° C.

Abstract: When a device using GaN semiconductors is made on a hard and chemically stable single-crystal substrate such as sapphire substrate or SiC substrate, a semiconductor device and its manufacturing method ensure high-power output or high-frequency operation of the device by thinning the substrate or making a via hole in the substrate. When a light emitting device using GaN semiconductors is made on a non-conductive single-crystal substrate such as sapphire substrate, the semiconductor device and its manufacturing method reduce the operation voltage of the light emitting device by making a via hole to the substrate. More specifically, after making a GaN FET by growing GaN semiconductor layers on the surface of a sapphire substrate, the bottom surface of the sapphire substrate is processed by lapping, using an abrasive liquid containing a diamond granular abrasive material and reducing the grain size of the abrasive material in some steps, to reduce the thickness of the sapphire substrate to 100 &mgr;m or less.

Abstract: There are provided a GaN field effect transistor (FET) exhibiting an excellent breakdown voltage owing to the high quality of GaN crystal in a region where the electric lines of force concentrate during operation of the same, and a method of manufacturing the same. The FET has a layer structure formed of a plurality of GaN epitaxial layers. A gate electrode and a source electrode are disposed on the surface of the layer structure, and a drain electrode is disposed on the reverse surface of the same. A region of the layer structure in which the electric lines of force concentrate during operation of the FET has a reduced dislocation density compared with the other regions in the layer structure.

Abstract: A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.

Abstract: In a sensor having a membrane structure, a sensor chip (silicon substrate) is provided with a through hole that is open on both upper and lower surfaces of the silicon substrate. A sensor element having a membrane structure is formed on the upper surface of the silicon substrate to close the through hole on the upper surface. The lower surface of the silicon substrate is bonded to a stem through adhesive to define a communication passage through which an inside and an outside of the through hole communicate with each other. Accordingly, the sensor can exhibit high reliability.

Abstract: A ferroelectric capacitor with a multilayer ferroelectric film to prevent degradation of its ferroelectric characteristics. The ferroelectric film is made of a lower PZT layer formed on a lower electrode and an upper titanium rich PZT or PbTiO3 layer. An upper electrode is formed on the second ferroelectric layer and a protection layer is formed to cover the ferroelectric capacitor.

Abstract: Process for fabricating electronic components, of the variable capacitor or microswitch type, comprising a fixed plate (1) and a deformable membrane (20) which are located opposite each other, which comprises the following steps, consisting in:

Abstract: There is described a high-integration, superior-power-efficiency semiconductor device having a storage node, whose structure is suitable for enabling high-yield and inexpensive manufacture. A plurality of transfer gates are formed on a silicon substrate. An interlayer film is provided so as to cover the transfer gates. A hollow node is formed from conductive material on the interlayer film. A contact hole is formed so as to penetrate through the interlayer film without exposing the transfer gate, as well as to expose the surface of the silicon substrate within the hollow node. A conductive layer is formed so as to cover the interior surface of the contact hole to a predetermined thickness in the region ranging from the interior surface of the hollow node to the exposed portion of the silicon substrate.

Abstract: Described is a semiconductor device having a silicon oxide (Sio2) film into which nitrogen atoms, in a range between approximately 2×1020 atoms/cm3 or more and 2×1021 atoms/cm3 or less, are introduced, used as an insulator film in the semiconductor device. For example, the device can be a nonvolatile memory device, and the silicon oxide film can be used as an insulator film between, e.g., a floating gate electrode and control gate electrode of the nonvolatile memory device. Stable operations and a retention capability of a nonvolatile memory device are obtained even if the nonvolatile memory device is scaled. Moreover, a programming voltage can be lowered. Also described are methods of fabricating the semiconductor device.

Abstract: A gate insulating film composed of silicon oxide and a floating gate electrode composed of polysilicon are formed sequentially on a P-type silicon substrate. A capacitance insulating film composed of silicon oxide and a control gate electrode composed of polysilicon are formed on the floating gate electrode. First spacer films, each composed of silicon oxide and formed over the respective side faces of individual components, and second spacer films, each composed of silicon nitride and formed on the respective first spacer films, are also provided. Even when a high-temperature heat treatment is performed in an oxidizing atmosphere, oxygen is prevented from being supplied to both end portions of the capacitance insulating film and the control gate electrode, which suppresses an increase in thickness of the capacitance insulating film at both end portions thereof.

Abstract: A reference voltage supply circuit is provided with a PNP transistor. The PNP transistor has an N-type well for a base formed at a surface of a P-type semiconductor substrate. The reference voltage supply circuit is further provided with a resistor element connected to an emitter of the PNP transistor. The resistor element has an N-type well for a resistor at the surface of the P-type semiconductor substrate. The well is fabricated at the same time as when the N-type well for a base is fabricated.

Abstract: A p-type impurity layer is formed in an n-type semiconductor substrate. Since the p-type impurity layer has a low impurity concentration and a sufficiently shallow depth of 1.0 &mgr;m or less, the carrier injection coefficient can be reduced. In the p-type impurity layer, a p-type contact layer of a high impurity concentration is formed for reducing a contact resistance. Since the p-type contact layer has a sufficiently shallow depth of 0.2 &mgr;m or less, it does not influence the carrier injection coefficient. Further, a silicide layer is formed between the p-type contact layer and an electrode such that the contact-layer-side end of the silicide layer corresponds to that portion of the p-type contact layer, at which the concentration profile of the contact layer assumes a peak value. The silicide layer further reduces the contact resistance.

Abstract: In accordance with an aspect of the invention, a semiconductor processing method of forming field effect transistors includes forming a first gate dielectric layer over a first area configured for forming p-type field effect transistors and a second area configured for forming n-type field effect transistors, both areas on a semiconductor substrate. The first gate dielectric layer is silicon dioxide having a nitrogen concentration of 0.1% molar to 10.0% molar within the first gate dielectric layer, the nitrogen atoms being higher in concentration within the first gate dielectric layer at one elevational location as compared to another elevational location. The first gate dielectric layer is removed from over the second area while leaving the first gate dielectric layer over the first area, and a second gate dielectric layer is formed over the second area. The second gate dielectric layer is a silicon dioxide material substantially void of nitrogen atoms.

Abstract: In a CMOS circuit, impurity regions are formed in the channel forming region of each of an n-channel and p-channel transistors alone the channel direction. The intervals between the impurity regions in the n-channel transistor is set narrower than those between the impurity regions in the p-channel transistor so as to make the absolute values of the threshold voltages of the n-channel and p-channel transistors approximately equal to each other. Where active layers are formed by utilizing a crystal structural body that is a collection of needle-like or columnar crystals, the same effect can be attained by controlling the width of the needle-like or columnar crystals.

Abstract: Dual gate dielectric constructions and methods therefor are disclosed for different regions on an integrated circuit. In the illustrated embodiment, gate dielectrics in memory array regions of the chip are formed of silicon oxide, while the gate dielectric in the peripheral region comprises a harder material, specifically silicon nitride, and has a lesser overall equivalent oxide thickness. The illustrated peripheral gate dielectric has an oxide-nitride-oxide construction. The disclosed process includes forming silicon nitride over the entire chip followed by selectively etching off the silicon nitride from the memory array region, without requiring a separate mask as compared to conventional processes. After the selective etch, oxide is grown over the entire chip, growing differentially thicker in the memory array region.

Abstract: An objective of the present invention is to realize a comparator which uses MOS transistors and has a reduced offset voltage and occupies a small surface area. This is characterized in that an impurity is introduced into a channel region of a MOS transistor, the mobility of a load side MOS transistor is made smaller than the mobility of a differential side MOS transistor, and the mutual conductance of the load side MOS transistor is made smaller than the mutual conductance of the differential side MOS transistor.

Abstract: A SRAM includes a plurality of high-resistance memory cells each having a point symmetric structure. The memory cell has a pair of load resistors each implemented by a contact plug. Each of the contact plugs connects the drain of a first drive transistor and the gate of a second drive transistor with a source line. The source/drain region of each transfer transistor is connected to a bit line implemented by a fourth layer alumninum via a contact plug received in a through-hole having a side wall for insulating the contact plug from the ground line implemented as a third layer polysilicon film.

Abstract: The present invention relates to an integrated circuit wiring capable of reducing the contact resistance between lines and a fabricating method thereof. The wiring in accordance with the present invention includes a gate oxide film formed on the upper surface of a semiconductor device. A first line including a first silicon film pattern that is formed on an upper surface of the gate oxide film and has a certain width; and a silicide film pattern that is formed on the upper surface of the first silicon film and has a smaller width than that of the first silicon film pattern to thereby expose a certain region of the first silicon film pattern. A second line is formed to contact the silicide film pattern and the exposed certain region of the silicon film pattern.

Abstract: The present invention provides a semiconductor sensor chip, which comprises a physical quantity sensing part provided on a silicon substrate, and a wiring part for transmitting a physical quantity, sensed by the physical quantity sensing part, as an electric signal, the semiconductor sensor chip comprising: a silicon cap covering the physical quantity sensing part and a part of the wiring part; a junction layer where an end of the silicon cap and the silicon substrate are tightly joined; wherein the silicon cap has an end and a cavity and also has a substantially U-shaped section, and there is provided a predetermined clearance between the junction layer and the physical quantity sensing part.

Abstract: In fabricating a microlens array, a transparent resin layer is formed on surfaces of microlenses by coating a phenol resin layer that chemically reacts with the microlenses and thereafter removing the phenol resin layer. Since the transparent resin layer is generated by chemical reaction with the microlenses, the transparent resin layer can be uniformly formed on the surfaces of the microlenses without deformation of the microlens and deterioration in material thereof. Therefore, the microlens array has the uniform microlenses in shape and quality, a short lens interval and a small ineffective region between the microlenses to obtain a high light condensation rate.

Abstract: A method of forming a multi-layer structure over an insulating layer comprises the steps of: selectively depositing a barrier layer on a predetermined region of an insulating layer by use of a first deposition mask; selectively depositing a metal seed layer made of a metal which is different in substance from the barrier layer by use of a second deposition mask, so that the metal seed layer extends not only on an entire surface of the barrier layer but also a peripheral region positioned outside the predetermined region of the insulating layer; and forming a metal plating layer made of the metal as the seed layer, so that the metal layer is adhered on the metal seed layer whereby the metal plating layer is separated from the barrier layer and also from the insulating layer.

Abstract: A semiconductor device and method of manufacturing the semiconductor device including a semiconductor substrate of a first conductivity type. A scribe lane area formed in the substrate to define chip formation areas. A deep well area formed in each chip formation area. The deep well area has a second conductivity type which is opposite the first conductivity type. Also, at least one well area is formed within the deep well area.

Abstract: An integrated circuit includes junction insulation on a substrate of semiconductor material. The integrated circuit comprises active regions of a first type of conductivity, and insulation regions which separate the junction-forming active regions from one another and from the substrate. The integrated circuit also includes electrical contacts for reverse-biasing the junctions. In order to obtain highly efficient insulation, at least one of the active regions is separated from the active regions adjacent to it and from the substrate by insulation regions which form an inner insulation shell, including regions of a second conductivity type. These regions contain the active region. An outer insulation shell includes regions of the first conductivity type which contain the inner insulation shell.

Abstract: A first insulating layer (12) overlying semiconductor substrate (10) has a plurality of conductive paths (14, 16) disposed thereon. Each of the plurality of conductive paths has at least a major portion thereof overlied with a second insulating layer (20). A third insulating layer (26), having air gap ports (28) formed therein, overlies adjacent conductive paths and extends from one to another such that an air gap (34) is formed. A passivation layer (30) overlies third insulating layer and seals the plurality of air gaps ports to form an insulation structure (40) for a semiconductor integrated circuit, and method thereof.

Abstract: A method and apparatus for forming a junctionless antifuse semiconductor structure comprises forming an antifuse in non-active areas of a semiconductor wafer. In one embodiment, the antifuse is formed over a polysilicon layer, which is coupled to a field oxide layer. In a further embodiment, the polysilicon layer comprises a bottom conductor layer in the antifuse. In another embodiment, a refractory metal silicide layer is formed between the polysilicon layer and the antifuse. In yet a further embodiment, the refractory metal silicide layer comprises the bottom conductor layer in the antifuse.

Abstract: According to a first aspect of the present invention, a plurality of PN junctions are formed at the surface of a semiconductor substrate under a belt-like conductive film having a spiral shape which constitutes an inductance device. An inverted bias voltage is applied to the PN junctions, and the surface of the substrate is completely depleted. Since the inverted bias voltage is applied to the PN junctions, even though the impurity density of the surface of the substrate is high and the adjacent PN junctions are separated to a degree, the extension of the depletion layers can be increased and complete depletion of the surface of the substrate can be achieved.

Abstract: An IC including a resistor which is coupled to a metal wiring level through metal contacts, said resistor including a discrete metal-insulator-metal stack, wherein said metal contacts are in contact to one of said metals of said film stack. In the above IC design, current flows laterally through either the top metal electrode, the bottom metal electrode, or both, and any unused electrode is disconnected from the circuit.

Abstract: An interposer adapted to be used between a mounting board and a semiconductor chip which is to be mounted on the mounting board. The interposer comprises: a heat-resistant insulator having first and second surfaces, the insulator being provided with a plurality of through-holes opened at the first and second surfaces; wiring patterns formed on the first and second surfaces of the insulator electrically connected to each other by means of a conductor provided on an inner wall of at least one of the through-holes; and a capacitor. The capacitor comprises first electrode formed on the insulator and having a connecting portion formed on an inner wall of at least one of the other through-holes, a dielectric layer formed on the first electrode, and a second electrode formed on the dielectric layer.

Abstract: A semiconductor device comprises one or more field effect devices (FD) having source and drain regions (5 and 6) spaced apart by a body region (3a). A gate structure (7a, 7b), preferably in a trench (4), controls a conduction channel in a portion (3b) of the body region (3a) between the source and drain regions. The device has one or more mesa structures (100) having end and side walls (100a to 100d). The body region (3a) extends between and meets at least the side walls (100c and 100d) of the mesa structure. The gate structure (7a, 7b) extends along and between the side walls such that the conduction channel accommodating portion (3b) extends along and between the side walls (100c and 100d). The source and drain regions (5 and 6) meet respective end walls (100a and 100b) of the mesa structure and/or its side walls (100c and 100d). At the mesa walls, a source electrode (S) contacts the source region (5) and a drain electrode (D) contacts the drain region (6).

Abstract: Two adjacent lines are formed in parallel to a signal line in a wiring layer where the signal line is formed. Intersection lines are formed respectively in wiring layers above and under the wiring layers where the signal line and the adjacent lines are formed, along areas which are enclosed by the adjacent lines. Entire-line-area through-holes for connecting each of the adjacent lines with a corresponding one of the intersection line are formed along the entire area of the adjacent lines, in an insulating layer between the adjacent lines and the intersection lines. The signal line is completely covered by the adjacent lines, the intersection lines and the entire-line-area through-holes. The adjacent lines, the intersection lines and the entire-line-area through-holes are maintained at a constant potential, or their electric potentials have the same phase as that of the signal line.

Abstract: Boron ions are implanted in the boundary of the field oxide film and P type well, and a first high energy boron implantation P layer is formed. Further boron ions are implanted near the center of the field oxide film in the thickness direction, and a second high energy boron implantation P layer is formed. The first and second high energy boron implantation P layers are formed away from the N type diffusion layer.

Abstract: A lead frame for a semiconductor device. The lead frame has a layer defining a first unit lead frame including a first support for a semiconductor chip and a plurality of leads spaced around the first support. The first support has a peripheral edge. The layer further defines a guide rail extending along at least a portion of the peripheral edge and connected to at least one of the leads. At least one notch is formed in the layer between the at least one lead and a part of the guide rail so as to define a first tie bar.

Abstract: A semiconductor package contains a plurality of sheet metal leads that are attached to one or more terminals on a top side of a semiconductor die. A heat sink is attached to a terminal on a bottom side of the die. Each of the leads extends across the die and beyond opposite edges of the die and is symmetrical about an axis of the die. At the locations where the leads pass over the edges of the die notches are formed on the sides of the leads which face the die, thereby assuring that there is no contact between the leads and the peripheral portion of the top surface of the die. Particularly in power MOSFETs the peripheral portion of the top surface normally contains an equipotential ring which is directly connected to the backside (drain) of the MOSFET, and hence a short between the leads on the top of the die and the equipotential ring would destroy the device. The result is a package that is extremely rugged and that is symmetrical about the axis of the die.

Abstract: BLP stack is disclosed which has a higher reliability and a less area of mounting for providing a denser package, including a first package having external power connection leads each started to be exposed through a bottom thereof and extended to a top surface through a side surface inclusive of bottom lead portions on a bottom surface, side lead portions on a side surface, and upper lead portions on a top surface, and a second package having external power connection leads started to be exposed through a bottom thereof and brought into contact with the external power connection leads on the first package to be electrically connected thereto.

Abstract: Apparatus and methods of packaging and testing die. In one embodiment, a stacked die package includes a packaging substrate having a first surface with a recess disposed therein and a plurality of conductive leads coupled thereto, a first die attached to the packaging substrate within the recess and having a plurality of first bond pads electrically coupled to at least some of the conductive leads, and a second die attached to the first die and having a plurality of second bond pads that are electrically coupled to at least some of the conductive leads. When the stacked die package is engaged with, for example, a circuit board, the first surface of the packaging substrate is proximate the circuit board so that the packaging substrate at least partially encloses and protects the first and second die. The properties and dimensions of the packaging substrate are tailored to optimize the operational environment of the die, including improving thermal dissipation and enhancing performance of the die.

Abstract: In a semiconductor apparatus comprising a semiconductor chip, a wiring substrate having the semiconductor chip mounted thereon, an under-fill resin sheet interposed between the semiconductor chip and the wiring substrate, and a resin sealing body for sealing the semiconductor chip, the under-fill resin sheet and the wiring substrate, the under-fill resin sheet is greater than the semiconductor chip in size, and its end is exposed from at least one side face of the resin sealing body. Since an end of the under-fill resin sheet is exposed from at least one side face of the resin sealing body, then the water contained in the under-fill resin sheet escapes from an exposed end of the under-fill resin sheet to the outside of the resin sealing body, thus making it possible to improve re-flow resistance of the semiconductor apparatus.

Abstract: A multi-chip integrated circuit, and an associated method, provides an interface of substantially reduced levels of capacitance and inductance relative to conventional connections formed of bond wires. One of the chips of the integrated circuits comprises a memory device, such as a DRAM, and another of the chips of the integrated circuit is formed of a logic chip, such as a CPU or graphics controller. The memory chip is mounted upon the logic chip utilizing chip-on-chip technology. Because of the reduced levels of capacitance and inductance of the interface connecting the chips together, the resultant integrated circuit can be operated at increased speeds and at reduced levels of power consumption.

Abstract: A stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of an integrated circuit (IC) device mounted to the FBGA. The conductive elements also are of sufficient size so that they extend beyond the bottom or top surface of the IC device, including the wiring interconnect and encapsulate material, as the conductive elements make contact with the FBGA positioned below or above to form a stack. The IC device, such as a memory chip, is mounted upon a first surface of a printed circuit board substrate forming part of the FBGA. Lead wires are used to attach the IC device to the printed board substrate and encapsulant is used to contain the IC device and wires within and below the matrix and profile of the conductive elements.

Abstract: A resin molding die includes: a cavity; a resin inlet through which a liquid resin to be cured is injected into the cavity; and an air vent through which air is released to an exterior space of the resin molding die during injection of the resin, the air vent being provided on an opposite side from the resin inlet with respect to the cavity.

Abstract: A LOC type semiconductor device comprises a semiconductor chip having a main surface in which semiconductor elements and a plurality of bonding pads are formed, and a back surface opposite the main surface; a plurality of leads each having an inner part and an outer part, and including a plurality of first leads having inner end portions extended on the main surface of the semiconductor chip and a plurality of second leads having inner end portions terminating near the semiconductor chip; bonding wires electrically connecting the bonding pads to bonding portions of the inner parts of the first and the second leads; and a sealing member sealing the semiconductor chip therein. A first bending portion is formed in the inner part of each second lead to prevent the sealing member from transformation by forming the sealing member in satisfactory resin balance between an upper portion and a lower portion of the sealing member.

Abstract: The present invention provides a quality and reliable high-density package (Chip Size Package) semiconductor device without problems related to the manufacturing process. The semiconductor device includes the first semiconductor substrate piece having electrode pads formed on its principle surface, and a second semiconductor mounting piece mounted thereon via a first insulating film and a die-attaching material. On the surface opposite the first semiconductor substrate piece of the second semiconductor substrate piece, formed are wiring patterns and a second insulating film for protecting the wiring patterns. The wiring patterns include electrode pads, wires, and lands where external connection terminals are provided.

Abstract: Disclosed is a semiconductor device which comprises a semiconductor element having a plurality of electrodes, a plurality of external electrodes disposed around the periphery of the semiconductor element, a fine wire electrically connected between at least one of surfaces of each of the plural external electrodes and at least one of the plural electrodes of the semiconductor element, and an encapsulating resin which encapsulates the semiconductor element, the plural external electrodes, and the fine wires and whose external shape is a rectangular parallelepiped, wherein a bottom surface of the semiconductor element and a bottom surface of each of the plural external electrode are exposed from a bottom surface of the encapsulating resin and a top surface of the semiconductor element and a top surface of each of the plural external electrode are located substantially coplanar with each other.

Abstract: A surface mount package is composed of a package body and first and second terminals. The package body has first and second surfaces intersecting with each other. Also, the package body has an installing portion for an element to be installed. The first terminal is connected to the first surface, and the second terminal is connected to the second surface.

Abstract: A semiconductor chip is attached on a package substrate so as to be electrically connected to it and sealed. A ring member is attached to the package substrate and surrounds the semiconductor chip. A lid member is attached to the ring member and covers the semiconductor chip. The lid member is formed so as to be able to be removed from the ring member without impairing the attachment of the ring member to the package substrate.

Abstract: A semiconductor device includes a semiconductor chip having a bump electrode over its main surface. The bump electrode has at least one protrusion on the top surface thereof. A lead is electrically connected to the top surface of the bump electrode, and is positioned adjacent to the protrusion.

Abstract: The invention provides a method for readily forming a bump with a desired width, a semiconductor device and a method for making the same, a circuit board, and an electronic device. A method for forming a bump includes forming an opening in an insulating film which exposes at least a part of a pad, and forming the bump so as to be connected to the pad. A resist layer 20 defines a through hole which extends over at least a part of the pad in plan view. A metal layer is formed in the opening so as to connect to the exposed portion of the pad.

Abstract: The present invention is a semiconductor device with improved adhesion properties of a resin with a wiring pattern, comprising a film fragment 14 having a patterned wiring pattern 16 including a projection 17, a semiconductor chip 12 having electrodes 13 bonded to the projection 17, and a resin 19 provided to the wiring pattern 16 in the region other than that of the projection 17; and the wiring pattern 16 has its surface of contact with the resin 19 roughened.

Abstract: During selective epitaxial growth processing using LPCVD equipment, a SiGe epitaxial layer and a Si epitaxial layer are sequentially formed so that lateral overgrowth that could occur in formation of only Si epitaxial layer can be effectively restricted. By adjusting Ge density, SiGe migration is induced at selective epitaxial growth temperatures for forming the conventional Si epitaxial layer. And, by utilizing the internal stress of SiGe and lattice mismatch between the SiGe epitaxial layer and the Si epitaxial layer, the lateral overgrowth is restricted. Furthermore, by hydrogen thermal processing, surface topology of the epitaxial layer is improved.

Abstract: A semiconductor device having a contact layer and a diffusion barrier layer is fabricated by preparing a semiconductor substrate, forming a layer of titanium/aluminum alloy on the surface of the substrate, and then heating the resultant structure in a nitrogen ambient to form a contact layer of titanium silicide interposed between the substrate and a diffusion barrier layer consisting of titanium/aluminum/nitride.

Abstract: A novel dielectric composition is provided that is useful in the manufacture of electronic devices such as integrated circuit devices and integrated circuit packaging devices. The dielectric composition is prepared by crosslinking a thermally decomposable porogen to a host polymer via a coupling agent, followed by heating to a temperature suitable to decompose the porogen. The porous materials that result have dielectric constants less than about 3.0, with some materials having dielectric constants less than about 2.5. Integrated circuit devices, integrated circuit packaging devices, and methods of manufacture are provided as well.