Abstract: A method and structure for textured surfaces in non volatile floating gate tunneling oxide (FLOTOX) devices, e.g. FLOTOX transistors, are provided. The present invention capitalizes on using “self-structured masks” and a controlled etch to form nanometer scale microtip arrays in the textured surfaces. The microtips in the array of microtips have a more uniform size and shape and higher density (˜1012/cm2) at the substrate/tunnel oxide (Si/Si02) interface than in current generation FLOTOX transistors. This higher density is four orders of magnitude greater than that which has been in use with FLOTOX transistor technology. In result, the new method and structure produce significantly larger tunneling currents for a given voltage than attained in prior work. The new method and structure are advantageously suited for the much higher density, non volatile FLOTOX transistors desired for use in flash memories and in electronically erasable and programmable read only memories (EEPROMs).

Abstract: A MIS type semiconductor device comprises a semiconductor layer provided with a recess portion having a side wall with an obtuse angle at least at a portion of the recess portion, a gate electrode formed over a bottom surface of the recess portion, with a gate insulating film interposed, a source region and a drain region formed on sides of the gate electrode with an insulating film interposed, such that boundary planes between the source region and the drain region, on one hand, and the insulating film, on the other hand, are formed in the semiconductor layer at an angle to a surface of the semiconductor layer, and wiring portions for contact with the surface of the semiconductor layer.

Abstract: A trench-gated power MOSFET contains a highly doped region in the body region which forms a PN junction diode with the drain at the center of the MOSFET cell. This diode has an avalanche breakdown voltage which is lower than the breakdown voltage of the drain-body junction near to the wall of the trench. Thus the MOSFET breaks down in the center of the cell avoiding the generation of hot carriers that could damage the gate oxide layer. The drain-body junction is located at a level which is above the bottom of the trench, thereby avoiding any deep diffusion that would increase the cell width and reduce the cell packing density. This compact structure is achieved by limiting the thermal budget to which the device is exposed after the body region is implanted. As a result, the body and its highly doped region do not diffuse significantly, and dopant from the highly doped region does not get into the channel region of the device so as to increase its threshold voltage.

Abstract: A semiconductor body has source and drain regions (4 and 5; 4′ and 5′) spaced apart by a body region (6; 6′) and a drain drift region (50; 50′) and both meeting the same surface (3a) of the semiconductor body. An insulated gate structure (7; 70′; 700) is provided within a trench (80; 80′; 80″) extending in the semiconductor body. The gate structure has a gate conductive region (70b; 70′b; 70″b) separated from the trench by a dielectric layer (70a; 70′a) such that a conduction channel accommodation portion (60; 60′) of the body region extends along at least side walls (80a; 80′a; 80a) of the trench and between the source (4; 4′) and drain drift (50; 50′) regions.

Abstract: A method of fabricating a semiconductor device including MOS elements comprising the steps of forming: a gate insulation layer on a semiconductor substrate; forming a gate electrode on the gate insulation layer; and implanting impurity ions into source and drain forming regions, wherein the ion implantation into said source and drain forming regions is performed in separate ion implantation steps. In at least either one of the ion implantation steps for the source forming region or for the drain forming region, a resist layer used for blocking impurities is provided with a wall extending to said gate insulation layer at a location distant from said gate electrode, said wall allowing charges to flow to the substrate.

Abstract: An SOI layer is formed on a silicon substrate with a buried insulating layer therebetween. An SOI-MOSFET is formed including a drain region and a source region that are formed to define a channel formation region at the SOI layer and including a gate electrode layer opposite to the channel formation region with an insulating layer therebetween. An FS isolation structure is formed to have an FS plate opposite to a region of the SOI layer in the vicinity of the edge portion of the drain region and the source region, and to electrically isolate the SOI-MOSFET from other elements by applying a prescribed potential to the FS plate to fix the potential of the region of the SOI layer opposite to the FS plate. The channel formation region includes two edge portions on both sides and a central portion between the edge portions in a direction of a channel width, and a channel length at the edge of a prescribed region is smaller than a channel length at the central portion.

Abstract: An SOI layer is formed so thick that a body region is not fully depleted under conditions of floating and a zero potential. When a MOSFET operates, a negative body potential is applied to the body region through a body electrode. Thus, the body region is fully depleted. The MOSFET is formed equivalently to a conventional MOSFET of a PD mode as to the thickness of the SOI layer, and is equivalent to a MOSFET of an FD mode as to its operation. Therefore, both of advantages of a PD mode MOSFET such as low resistance in source/drain regions, easiness in formation of a contact hole for a main electrode and stability of a silicide layer and an advantage of an FD mode MOSFET such as excellent switching characteristics are compatibly implemented.

Abstract: There is disclosed a hybrid circuit in which a circuit formed by TFTs is integrated with an RF filter. The TFTs are fabricated on a quartz substrate. A ceramic filter forming the RF filter is fabricated on another substrate. Terminals extend through the quartz substrate. The TFTs are connected with the ceramic filter via the terminals. Thus, an RF module is constructed.

Abstract: A semiconductor device having an MODFET and at least one other device formed on one identical semiconductor substrate, in which an intrinsic region for the MODFET is formed by selective growth in a groove formed on a semiconductor substrate having an insulation film on the side wall of the groove, and single-crystal silicon at the bottom of the groove, is disclosed. The step between the MODFET and the at least one other device mounted together on one identical substrate can be thereby decreased, and each of the devices can be reduced in the size and integrated to a high degree, and the interconnection length can be shortened to reduce power consumption.

Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.

Abstract: In a method for fabricating a semiconductor device, a silicide material is formed at least on the surface of an area to be silicided. Then, a first RTA (Rapid Thermal Annealing) process is performed to form a first-reacted silicide region. Next, a supplemental silicon layer is formed over the entire surface; and a second RTA process is performed to form a second-reacted silicide region.

Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with-recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.

Abstract: A method for forming a high-speed device in an integrated circuit is disclosed. The approaches include reduction of gate-size and cutback on device capacitance and resistance. In the present invention, poly-trench etching followed by silicone selective growth and dielectric spacer formation are used to define gate length. A reduced gate size is therefore obtained. As with a dielectric buffer layer positioned below the source and drain regions, the proposed device possesses a largely decreased junction capacitance area. The design of air-gap spacer is to cut down on the overlap capacitance between gate and source/drain. Finally, with the application of raised polysilicon source and drain layers to behave as silicide consumption layer and the utilization of the buffer layer to provide diffusion protection, the silicide layer can be thickly formed to reduce sheet resistance without any increment on the junction leakage current.

Abstract: A semiconductor device includes a semiconductor substrate having an oxide layer thereon. A gate conductor is provided on the oxide layer, the gate conductor including a layer of polysilicon on the oxide layer, a tungsten silicide layer on the polysilicon layer, and a nitride cap layer on the tungsten silicide layer. The polysilicon layer has a length greater than length of the silicide layer and the nitride layer. Dielectric spacers on the gate conductor overlay the nitride cap layer and the tungsten silicide layer to provide a sidewall substantially flush with the polysilicon layer. Exposed polysilicon on the polysilicon layer is oxidized.

Abstract: The micro-machined surface structure includes a substrate 1, a circuit 10 comprising an n-layer or a p-layer diffused after ion implantation of impurities onto the substrate, an oxide film 5 for protecting the circuit 10 and a nitride film 6 formed on the oxide film. A circuit connection portion 11 is electrically connected with the circuit 10 and a structural body comprising polysilicon is formed on the circuit connection portion 11 and on the nitride film 6 in which the nitride film is formed between the oxide film 5 and the circuit connection portion 11 on the substrate.

Abstract: A circuit includes a substrate having a dielectric layer with a first surface and a second surface. A conductive layer is formed on the first surface. A beveled via is formed in a dielectric layer of the substrate. The via has a first opening of a first width in the first surface, and a second opening of a second width in the second surface, the second width being greater than the first width. A conductive plug is connected to the conductive layer. The plug is formed in the via and extends from adjacent the first opening toward the second opening, and terminates adjacent the second opening at a plug interface surface. A conductive solder ball is connected to the plug interface surface and extends to protrude from the second surface.

Abstract: The invention relates to a method of forming an insulating zone (14) around an active zone (12) in a semiconductor substrate, which method includes the following steps:

Abstract: A silicon substrate has area-selectively formed porous silicon in which porosity, pore size, and pore size distribution of a porous silicon region and a shape of the porous silicon are controlled. In a silicon forming method of immersing the silicon substrate coated with a mask layer having an opening area into a solution to which forming current is applied, and anodically forming a part of the silicon substrate from the opening area of the mask layer so as to form a porous silicon area in the silicon substrate, the forming current is increased according to degree of growth of the porous silicon such that the interface current density between a growing end part of the porous silicon and silicon substrate in the anodizing process may be substantially kept at constant.

Abstract: A bonded wafer 100 has a device substrate 16 with isolation trenches 30 defining device regions 18. Oxide dogbone structures are removed before filling trenches 30. Voids 36 in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer 30 and filled with polysilicon 34. A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride 50 cover the trenches and the adjacent device substrate regions.

Abstract: An integrated circuit is provided in which a relatively low band gap material is used as a semiconductor device layer and in which an underlying high (wide) band gap material is used as an insulating layer. The insulating material has a high thermal conductivity to allow heat dissipation in conjunction with dielectric isolation. The integrated circuit includes one or more semiconductor wells which are each surrounded on their sides by an insulating material. The bottom of the semiconductor wells are disposed atop the high band gap material which provides both electrical isolation and thermal conductivity. A semiconductor substrate may be provided to support the high band gap material. A layer of insulating material may also be provided between the high band gap material and the semiconductor substrate.

Abstract: An inductor is formed above an element isolation region in a semiconductor substrate, and a grounded shield layer is interposed between the inductor and element isolation region. The shield layer is formed of high-resistance polysilicon, monocrystalline silicon or amorphous silicon doped with low-concentration impurities whose conductivity type is opposite to that of the semiconductor substrate. An impurity diffusion region which is formed in a well under the element isolation region and whose conductivity type is opposite to that of the well, can be used as the shield layer.

Abstract: An inductor has a spiral aluminum track deposited on an oxide layer over a silicon substrate. The substrate is etched away to form a trench, which extends around beneath the track and provides an air gap having a low dielectric constant. The oxide layer has an inner region within the track, an outer region outside the track and a bridging region extending between the other regions. The bridging region is comprised of intact bridges and gaps therebetween, which are open to the trench and through which an etchant has access to the silicon substrate to form the trench by etching.

Abstract: The present disclosure is directed to the use of non-ion-implanted silicon oxynitride films as resistive elements. Such films have been traditionally used in semiconductor processing as antireflective coatings, but their utility as highly resistive circuit elements has heretofore not been realized. Such films find specific utility when used as the load resistors in a 4-T SRAM cell.

Abstract: The invention relates to an essentially discrete semiconductor device comprising a semiconductor body (10) having a first, preferably bipolar, transistor (T1) with a first region (1) forming a collector (1) of T1, and a second, preferably also bipolar, transistor (T2) with a second region (2) forming a collector (2) of T2, which transistors (T1, T2) are in a cascode configuration wherein the collector (1) of T1 is connected to the emitter (4) of T2. Such a device cannot suitably be used in a base station for mobile communication.

Abstract: An improved method for producing a semiconductor device in which overpolishing is prevented at a chemical mechanical polishing time to eliminate the influence of peripheries on the object part. A plasma oxide film is formed on a semiconductor substrate so as to fill a recess and a trench. With the use of a resist film as a mask, the plasma oxide film is selectively etched to leave an overpolish-preventing support member in a neighborhood of the recess, which is a photo-related mark, for providing a support against overpolishing at a chemical mechanical polishing time. The surface of the semiconductor substrate is polished by chemical mechanical polishing. Thereafter, a nitride film and an oxide film are removed.

Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer si reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the GaAs single crystal can be made uniform.

Abstract: In a semiconductor integrated circuit having a functional macro, plural first and second power lines extending over the functional macro and supplying first-level and second-level voltages respectively to the functional macro are electrically connected through plural first and second power terminal patterns to plural third and fourth power lines extending over the semiconductor integrated circuit in the second direction and supplying the first-level and second-level voltages respectively to the semiconductor integrated circuit.

Abstract: A plurality of lower-level metal interconnects are formed over a semiconductor substrate. A first fluorine-containing insulating film, made of a fluorine-doped insulator, is formed to fill in gaps between adjacent ones of the lower-level metal interconnects over the semiconductor substrate. An interlevel insulating film is formed over the lower-level metal interconnects and the first fluorine-containing insulating film. And a plurality of upper-level metal interconnects are formed on the interlevel insulating film. The interlevel insulating film includes: a second fluorine-containing insulating film made of a fluorine-doped insulator; and a silicon-rich insulating film containing a larger quantity of silicon than a quantity defined by stoichiometry.

Abstract: A plurality of optimized diode chips are connected in series with each other to provide a high-voltage silicon diode rectifying device. Each chip has an improved withstand voltage and inverse surge resistance which improves the overall usefulness and efficiency of high-voltage silicon diodes. This invention also reduces costs by requiring fewer individual diode chips. The specific resistance of the (n)-type silicon substrate is in a critical range of between 20 to 50 &OHgr;cm. The diffusion depth of the p+ anode layer is in a critical range of between 30 to 200 &mgr;m. The thickness of the n− base layer is 0.54×(&rgr;·Vsr)½ or greater. In another embodiment, the specific resistance of the silicon substrate is in the range of 32 to 40 &OHgr;cm, and diffusion depth of the p+ anode layer is in the range of 70 to 200 &mgr;m. In yet another embodiment, a cathode layer is diffused on the semiconductor base material.

Abstract: By forming a flat member 10 forming a conductive film 11 having substantially same pattern with a second bonding pad 17, a wiring 18, and an electrode 19 for taking out, or forming a flat member 30 half-etched through the conductive film 11, it is possible to manufacture a semiconductor device 23 of BGA structure using a back process of a semiconductor maker.

Abstract: In an integrated circuit package, a resistance film as an electric resistance part which is electrically independent is provided on a dielectric substrate at an opposed position to an integrated circuit chip. A thickness of the substrate is specified to be almost a quarter of a signal wavelength which is decided by a frequency used in an integrated circuit of the chip and the specific inductive capacity of the substrate, and the surface resistance value of the resistance film is specified to become equal to the characteristic impedance of air. Being structured as above, an unnecessary electromagnetic wave which is emitted from the integrated circuit of the integrated circuit chip is absorbed with extremely high efficiency, and stabilization of the operation of a circuit can be realized.

Abstract: A semiconductor device package has a lead frame with four or more die receiving pads. The first pad is large enough to receive two or more of the die, laterally spaced from one another, while the other pads receive at least one die each. The die may be arranged in a single straight path, or in spaced parallel paths. The tops of selected ones of the die are bonded to lead frame elements of adjacent pads to complete bridge type circuits within the package. The die and pads are enclosed by a molded plastic housing and short sections of the pads protrude through the housing wall.

Abstract: A frame F for semiconductor package has die-pads 3 supported with suspending leads 2 of individual lead frames 10. Semiconductor devices are arranged on die-pads 3. These semiconductor devices are collectively molded with molding compounds, and then the collectively molded semiconductor packages are cut into individual packages by means of dicing saw. In the frame F, suspending leads are formed into fish tails, wherein at least one of longitudinal grid-lead and transverse grid-lead is eliminated within areas enclosed with fish tails of the suspending leads 2. Accordingly, whether R-shape generated by producing frame for semiconductor package by etching process is large or small, to exist metal piece at edges of semiconductor packages in dicing becomes almost nothing.

Abstract: A semiconductor device assembly including a semiconductor device having a plurality of bond pads on the active surface thereof and a lead frame having a portion of the plurality of lead fingers of the lead frame located below the semiconductor device in a substantially horizontal plane and another portion of the plurality of lead fingers of the lead frame located substantially in the same horizontal plane as the active surface of the semiconductor device. Both pluralities of lead fingers of the lead frame having their ends being located substantially adjacent the peripheral sides of the semiconductor device, rather than at the ends thereof.

Abstract: A frame F for semiconductor package has die-pads 3 supported with suspending leads 2 of individual lead frames 10. Semiconductor devices are mounted on die-pads 3. These semiconductor devices are collectively molded with molding compounds, and then the collectively molded semiconductor packages are cut into individual packages by means of dicing saw. In the frame F, thin parts are formed in areas corresponding to neighborhood of the roots of individual terminals, the thin parts being formed by half-cutting by etching metal of the areas from the front or back thereof. Or, hollows are formed in areas corresponding to neighborhood of the roots of individual terminals, Accordingly, it is inhibited that increased sectional area of terminals is formed, so that intervals between adjacent terminals 5 are sufficiently kept. Accordingly, accidents such as soldered bridge do not occur.

Abstract: A semiconductor device includes a two-part, coplanar, interdigitated decoupling capacitor formed as a part of the conductive lead frame. For down-bonded dice, the die attach paddle is formed as the interdigitated member. Alternatively, an interdigitated capacitor may be placed as a LOC type lead frame member between electrical bond pads on the die. The capacitor sections comprise Vcc and Vss bus bars.

Abstract: A semiconductor chip package and a fabrication method therefor are disclosed. The semiconductor chip package includes a semiconductor chip having a plurality of pads, a passivation film formed on the semiconductor chip and opened in the pads, a metallic film first pattern formed on the upper surfaces of the pads, a metallic film second pattern extended from a corresponding one of the metallic film first patterns formed on one pad among the pads to the passivation film and having a predetermined size which is two times compared to the area of one of the pads, and a plurality of leads formed on the metallic film first pattern.

Abstract: An integrated circuit die and/or package. An apparatus is described having a substrate with a central region and an outer region. A first plurality of electrical connections is spaced apart by a first distance on the outer region of the substrate. A second plurality of electrical connections is spaced apart by a second distance, smaller than the first distance, on the central region of the substrate.

Abstract: Disclosed is a semiconductor package including: a pad having one power semiconductor device mounted thereon, and a plurality of lead frames including unbent inner frames only, the inner frame being formed on the same line as the pad and electrically connected to the power semiconductor device via a wiring, the lead frames having a first face connected to the wiring, and a second face opposite to the first face. The semiconductor package further includes a molding part formed from an insulating and heat-conductive material and surrounding the power semiconductor device, the pad, and the lead frames. The pad is electrically connected to the power semiconductor device and thereby separated from the lead frames. The lead frames include only inner leads connected to the wiring, and the bottom surface of the lead frames opposite to the top surface connected to the wiring is exposed outwardly together with the bottom surface of the pad, thereby being electrically connected to the printed circuit board via soldering.

Abstract: A flip-chip MOSFET structure has a vertical conduction semiconductor die in which the lower layer of the die is connected to a drain electrode on the top of the die by a diffusion sinker or conductive electrode. The source and gate electrodes are also formed on the upper surface of the die and have coplanar solder balls for connection to a circuit board. The structure has a chip scale package size. The back surface of the die, which is inverted when the die is mounted may be roughened or may be metallized to improve removal of heat from the die. Several separate MOSFETs can be integrated side-by-side into the die to form a series connection of MOSFETs with respective source and gate electrodes at the top surface having solder ball connectors. Plural solder ball connectors may be provided for the top electrodes and are laid out in respective parallel rows. The die may have the shape of an elongated rectangle with the solder balls laid out symmetrically to a diagonal to the rectangle.

Abstract: The present invention provides a resin-sealed semiconductor IC package of a large integration size having a size substantially equal to that of its component semiconductor IC chip. The resin-sealed semiconductor IC package comprises a semiconductor IC chip, a plurality of leads arranged on the semiconductor IC chip and having end portions bent so as to extend perpendicularly to the major surface of the semiconductor IC chip, a resin molding sealing the semiconductor IC chip and the leads therein so that the tips of the end portions of the leads are exposed on one surface thereof, and conductive elements connected respectively to the exposed tips of the leads.

Abstract: The electrical connections of an integrated circuit chip assembly comprised of an integrated circuit chip attached to a substrate are encapsulated and reinforced with a high viscosity encapsulant material by dispensing the encapsulant material through an opening in the substrate into the space between the integrated circuit chip and the substrate. An integrated circuit chip assembly having a reinforced electrical interconnection which is more resistant to weakening as a result of stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.

Abstract: Providing a method of producing a semiconductor device wherein semiconductor element are sealed with a resin by using the same lead and other means regardless of the specifications of the semiconductor elements, and a semiconductor device which can be reduced in size and weight and has good heat dissipation performance and high-frequency performance.

Abstract: A power wiring structure realizes low inductance and is applicable to a semiconductor device.

Abstract: A semiconductor chip (15) is bonded on a die pad (13) of a leadframe, and inner leads (12) are electrically connected to electrode pads of the semiconductor chip (15) with metal fine wires (16). The die pad (13), semiconductor chip (15) and inner leads are molded with a resin encapsulant (17). However, no resin encapsulant (17) exists on the respective back surfaces of the inner leads (12), which protrude downward from the back surface of the resin encapsulant (17) so as to be external electrodes (18). That is to say, since the external electrodes (18) protrude, a standoff height can be secured in advance for the external electrodes (18) in bonding the external electrodes (18) to electrodes of a motherboard. Thus, the external electrodes (18) may be used as external terminals as they are, and no ball electrodes of solder or the like need to be provided for the external electrodes (18). Accordingly, this process is advantageous in terms of the number of manufacturing process steps and the manufacturing costs.

Abstract: The invention relates to a device and a method for packaging electronic components (11) having semiconductor chips (5) by means of a mounting frame (1), which is additionally provided with a plastic grid (6) that is disposed on a plastic intermediate substrate (2), which surrounds each semiconductor chip (5) in framelike fashion and which for packaging the plurality of semiconductor chips (5) with a plastic casting composition (7) between semiconductor chips (5) and the plastic grid (6).

Abstract: The invention disclosed herein is a semiconductor die assembly and method of making the same having a die and insert substrate that are electrically interconnected by diffusing gold bumps attached to the connecting surface of the substrate to aluminum-based bond pads on the die to form a permanent die-to-insert connection. The process for diffusing the gold bumps into the bond pads preferably occurs during a burn-in process wherein pressure and heat are applied to the die/substrate assembly without melting the gold bumps until a permanent die-to-insert substrate connection is properly made.

Abstract: A semiconductor device includes an elastic member which has an adhesive contact with at least one other member. The adhesive contact forces said elastic member to stay in a deformed shape different from an original shape to which said elastic member tries to return, wherein a force generated by said elastic member trying to return to the original shape serves to counteract a heat-generated stress applied to said semiconductor device.

Abstract: A semiconductor package having heat sink at the outer surface is constructed on a lead frame. The package comprises a chip, a die pad, a plurality of leads, a plurality of bonding wires, and a molding compound. The die pad has a first surface and a second surface, and the chip has its active surface bonded to the first surface of the die pad. The area of the die pad is smaller than the area of the chip in order to expose the bonding pads on the active surface of the chip. The leads having an inner lead portions and an outer lead portions are disposed at the periphery of the die pad, and the inner lead portions are electrically connected to the bonding pads by a plurality of bonding wires. The molding compound encapsulates the chip, the die pad, the inner lead portions of the leads, and the bonding wires. The second surface of the die pad is exposed on the top surface of the package structure while the outer lead portion of the leads is exposed at the side edge of the package structure.

Abstract: A plurality of semiconductor chips with the same structure are stacked to construct a multichip semiconductor device. In each of the semiconductor chips, an optional circuit is formed. In the optional circuit, fuses corresponding to the stacked-stage number of each chip are formed and the fuses are selectively cut off so as to permit each chip to individually receive a chip control signal.