Abstract: A process and system for electrical extraction of intracellular matter from biological matter, and intracellular matter products formed thereby, based on preparing a mixture of biological matter featuring cells, and an electro-conductive liquid, and electrifying the mixture by transmitting controlled cycles of pulses and pauses of electrical current into the mixture by using electrodes, whereby the pulses of electrical current pierce holes into or perforate the cell membranes of the cells, enabling the release of intracellular matter for collecting and separating into target intracellular matter extract and solid waste. Pauses included in each cycle of transmitting pulses of electrical current enable firm control of electrical extraction processing conditions, including extent of extraction, temperature effects, and pressure effects, during the electrical extraction process.

Abstract: A novel isolate of Bacillus isolated from white pine is described. The isolate is used to produce monoterpene derivatives. Also described is a pinene hydroxylase enzyme from the isolate. The enzyme is a general allylic oxidizer.

Abstract: The method for preparing an optically active (R)-amino compound characterized by the method comprising stereoselectively carrying out amino group transfer by action of an (R)-form-specific transaminase in the co-presence of a ketone compound (amino acceptor), and an amino compound (amino donor) of a racemic form or an (R)-form, to give an optically active (R)-amino compound. According to the present invention, it is made possible to easily prepare at a high yield the optically active (R)-amino compounds and the like having an aryl group and the like at their 1-position, which have been conventionally difficult to prepare.

Abstract: The present invention provides amino acid sequences of peptides that are encoded by genes within the human genome, the protease peptides of the present invention. The present invention specifically provides isolated peptide and nucleic acid molecules, methods of identifying orthologs and paralogs of the protease peptides, and methods of identifying modulators of the protease peptides.

Abstract: The present invention provides amino acid sequences of peptides that are encoded by genes within the human genome, the protease peptides of the present invention. The present invention specifically provides isolated peptide and nucleic acid molecules, methods of identifying orthologs and paralogs of the protease peptides, and methods of identifying modulators of the protease peptides.

Abstract: The invention provides replication of high growth influenza virus strains, derived from clinical isolates, in cultured mammalian cells by infecting the mammalian cells with the high growth strains to obtain infected cells, and culturing the cells while maintaining a trypsin concentration range of 0.05-1.0 &mgr;g/ml in the culture medium, where the resulting replicated virus is suitable for use in mammalian influenza vaccines and vaccination methods, which are also provided by the invention.

Abstract: Liquid chemical compositions are disclosed for anaerobic biodegradation, detoxification, and transformation of toxic organic and inorganic compounds in a contaminated geologic media under reducing conditions, including, but not limited to, denitrifying, manganese-reducing, iron-reducing and sulfate-reducing conditions. One such liquid chemical composition includes sodium nitrate in the range of one-fifth (0.2) to four (4) pounds per gallon of the chemical composition; sodium hexametaphosphate or other biologically hydrolyzable ring or linear polyphosphate in the range of one twentieth (0.05) to five (5) pounds per gallon of the chemical composition; a surfactant in the range of 0.01% to 10% by volume of the chemical composition; and a diluent in the form of water. A bioremediation apparatus is disclosed for anaerobic biodegradation, detoxification, and transformation of toxic organic and inorganic compounds in a contaminated geologic media.

Abstract: A method for DNA reassembly after random fragmentation, and its application to mutagenesis of nucleic acid sequences by in vitro or in vivo recombination is described. In particular, a method for the production of nucleic acid fragments or polynucleotides encoding mutant proteins is described. The present invention also relates to a method of repeated cycles of mutagenesis, shuffling and selection which allow for the directed molecular evolution in vitro or in vivo of proteins.

Abstract: Provided is a method for introducing a substance into a cell, which method comprises: (a) contacting the cell with a recognition agent to bind the recognition agent to a recognition site on the surface of the cell; and (b) separating the recognition agent from the cell thereby forming a hole in the surface of the cell. Kits for use in such methods are also provided.

Abstract: The present invention relates to an agent for the expression of long-term potentiation of synaptic transmission, which contains a compound having a brain somatostatin activation property as an active ingredient and to a screening method of an agent for the expression of long-term potentiation of synaptic transmission, which uses a soniatostatin releasing property as an index. The present invention is useful for the prophylaxis and/or treatment of cerebral diseases of dementia, amnesia, manic-depressive psychosis, schizophrenia, Parkinson's disease, psychosomatic disease and the like.

Abstract: A rapid colorimetric assay is provided for determining the concentration of vanadyl and vanadate ion species, and total vanadium concentration, in a sample. A sample suspected of containing vanadium in one or more of these oxidation states is combined with a colorimetric substrate that will provide for different absorption spectra with vanadyl and vanadate complexes. Suitable colorimetric substrates include halogenated hydroxyquinolines, e.g. broxyquinoline (DBHQ). The solvent and assay conditions are chosen to minimize oxidation of the vanadium. The absorbance of the sample is then read at two wavelengths, one that indicates the presence of both vanadyl and vanadate, and one that indicates the presence only of one species, generally vanadate. By comparison to a standard curve, the total concentration and the species concentration of vanadium in the sample is determined.

Abstract: Compositions and methods for determining the presence or concentration of an analyte in a sample by exposing the sample to an indicator molecule comprising a fluorescent lanthanide metal chelate complex. The presence or concentration of the analyte in the sample is determined by observing and/or measuring the change in intensity of fluorescence emitted by the lanthanide metal chelate complex upon binding of the analyte to one or more recognition elements in the complex. The fluorescent indicator molecules can be used in various types of fluorescent sensing devices and are useful in various fields, including energy, medicine and agriculture.

Abstract: A film-type vaporizer in a vaporization enclosure, for example the upper column of a double air-distillation column, is associated with a measurement and analysis box where a polished surface and a spillway reconstruct the flow of liquid in the vaporizer in order to check for the absence of the deposition of impurities in the liquid that is to be evaporated. If deposition occurs, the impurities involved are quantified and analyzed and appropriate action taken on the settings of the machine.

Abstract: Disclosed herein are uses of a recombinant protein as a receptor for a hepatitis virus. Also disclosed are a nucleic acid coding for the receptor, a vector comprising a nucleic acid encoding the receptor, a host cell transformed or transfected with the nucleic acid, and a new recombinant protein having the biological property to act as a receptor for a hepatitis virus and a transgenic animal expressing the recombinant protein.

Abstract: A ferroelectric film is formed on a principal surface of an underlying substrate. By the vapor deposition using high density plasma, an insulating protection film is deposited so that the ferroelectric film is covered therewith. The deposited protection film can prevent the ferroelectric film from deteriorating.

Abstract: In one aspect, the invention includes a method of etching, comprising: a) forming a material over a substrate, the material comprising a lower portion near the substrate and an upper portion above the lower portion; b) providing a quantity of detectable atoms within the material, the detectable atoms being provided at a different concentration in the lower portion than in the upper portion; c) etching into the material and forming etching debris; and d) detecting the detectable atoms in the debris. In another aspect, the invention includes a method of etching, comprising: a) providing a semiconductor wafer substrate, the substrate having a center and an edge; b) forming a material over the substrate, the material comprising detectable atoms; c) etching into the material and forming etching debris; d) detecting the detectable atoms in the debris; and e) estimating a degree of center-to-edge uniformity of the etching from the detecting.

Abstract: A new method and apparatus is provide whereby light diffusion within the light measurement toll has been eliminated. A layer of Anti Reflective Coating is deposited on the outside of the second surface of a quartz mask thereby preventing light that is reflected internally to the quartz mask from exiting the mask. All reflected light is therefor eliminated and, with that, the source of light diffusion is eliminated.

Abstract: Systems and methods are described for fabrication of highly textured lithium cobalt oxide films by rapid thermal annealing. A method of forming a lithium cobalt oxide film includes depositing a film of lithium cobalt oxide on a substrate; rapidly heating the film of lithium cobalt oxide to a target temperature; and maintaining the film of lithium cobalt oxide at the target temperature for a target annealing time of at most, approximately 60 minutes. The systems and methods provide advantages because they require less time to implement and are, therefore less costly than previous techniques.

Abstract: A first resist layer (21) and a second resist layer (22) are formed on a base material (11) in the recited order, the first resist layer (21) being removable by etching and the second resist layer (22) being a photosensitive resist layer in which either exposed or unexposed regions become soluble in a developing solvent upon emission of light. Near-field light is then emitted to the second resist layer (22) by means (24) for emitting near-field light (27) according to a diffraction grating pattern upon reception of the light. Next, the diffraction grating pattern is formed in the second resist layer (22) by developing the second resist layer (22). The first resist layer (21) is etched with the pattern in the second resist layer (22) as an etching mask, and a diffraction grating pattern consisting of the first and second resist layers (21, 22) is formed.

Abstract: The present invention is related to a method for forming a CMOS image sensor device. A CMOS image device has a first MOS device acting as a source follower of an active pixel, a second MOS device acting as a row select of the active pixel. An amorphous silicon layer acts as a photo-diode area for collecting incident light over the first MOS device and the second MOS device. The amorphous silicon layer has both N-type and P-type dopants.

Abstract: A process for forming a color image sensor cell, in which a bonding pad structure is protected from exposure to alkaline developer solution, used for definition of color filter elements, and also used to open a contact hole to the bonding pad structure, has been developed. The process features the use of a passivation layer, comprised of an overlying silicon nitride layer, and an underlying silicon oxide layer, located on the top surface of the bonding pad structure. The passivation layer protects the underlying bond pad structure from alkaline developer solutions used to define overlying color filter elements, of the color image sensor cell. After definition of the color filter elements the contact hole opening to the bond pad is finalized using a dry etching procedure, applied to the passivation layer.

Abstract: In a method of the present invention for fabricating a two-dimensional image detector in which a light/radiations detection element is applied, an upper electrode, a first charge blocking layer, and a semiconductor layer having photoconductivity are provided on support substrate in the stated order, and thereafter, a surface of the semiconductor layer is sprayed with ceramic particles by means of an abrasive grain jet nozzle. The abrasive grain jet nozzle repeatedly makes a high-speed reciprocating motion in an X direction at constant cycles while jetting the ceramic particles to the entirety of the surface of the semiconductor layer of the counter substrate moving in a Y direction, so that the surface of the semiconductor layer is subjected to a flattening treatment. This enables to provide a two-dimensional image detector in which a light/radiations detection element that provides effective improvement of a charge blocking effect and suppression of deterioration of reliability is applied.

Abstract: A dimensionally stable core for use in high density chip packages is provided. The stable core is a metal core, preferably copper, having clearances formed therein. Dielectric layers are provided concurrently on top and bottom surfaces of the metal core. Metal cap layers are provided concurrently on top surfaces of the dielectric layers. Blind or through vias are then drilled through the metal cap layers and extend into the dielectric layers and clearances formed in the metal core. If an isolated metal core is provided then the vias do not extend through the clearances in the copper core. The stable core reduces material movement of the substrate and achieves uniform shrinkage from substrate to substrate during lamination processing of the chip packages. This allows each substrate to perform the same. Additionally, a plurality of chip packages having the dimensionally stable core can be bonded together to obtain a high density chip package.

Abstract: In a semiconductor device including a substrate which has a primary surface, a conduction wire formed on the primary surface, a semiconductor element which has a secondary surface, a projective electrode formed on the secondary surface, an insulative resin for adhesion which is applied between the primary surface and the secondary surface and which shrinks by hardening thereof, the substrate and the semiconductor element are adhered to each other by the hardening of the insulative resin with the projective electrode and the conduction wire corresponding with each other, so that an electrical connection between the projective electrode and the conduction wire is achieved and that a residual stress is generated in the insulative resin. The residual stress has a maximum value thereof around the projective electrode.

Abstract: According to the preferred embodiment, an antifuse structure and method for personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment antifuse comprises a two layer transformable insulator core between two electrodes. The transformable core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes. The two layer core preferably comprises an injector layer and a dielectric layer. The injector layer preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer and dielectric layer are non-conductive. When a sufficient voltage is applied the core fuses together and becomes conductive.

Abstract: The present invention discloses a method of forming an isolation region in a silicon-containing substrate. The method includes forming a mask layer on the silicon-containing substrate. A window is subsequently formed in the mask layer to expose the isolation area to be formed in the substrate. An oxygen-containing region is formed in the substrate by introducing oxygen-containing ions through the window in the mask layer. Then, the oxygen-containing region is subjected to a thermal treatment, thereby resulting in a silicon oxide insulator (SiOx) for isolating electronic devices.

Abstract: A substrate containing a compound semiconductor layer comprises a substrate layer 11, a first semiconductor layer 12 formed on the substrate layer 11, and a second semiconductor layer 13 made of a Group III nitride-based compound semiconductor formed on the first semiconductor layer 12. The semiconductor layer 12 is provided with a plurality of pores 14. Thus, a compound semiconductor layer containing a Group III nitride-based compound semiconductor with excellent surface planarity and crystallinity can be provided, as well as a method for manufacturing the same, and a semiconductor device using the same.

Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing.

Abstract: A semiconductor device includes a substrate and a first layer of a first conductive material on the substrate, the first layer having a first etching rate. A second layer of a second conductive material has a first hole on a portion of the first layer, the second layer having a second etching rate higher than the first etching rate. A third layer includes a combination of the first and second layers between the first and the second layers, the third layer having a third etching rate lower than the second etching rate. An insulating layer has a second hole on the third layer, the insulating layer having a fourth etching rate higher than the first etching rate. A transparent conductive layer is on the third layer through the first and second holes.

Abstract: The present invention includes field effect transistors, field emission apparatuses, thin film transistors, and methods of forming field effect transistors. According to one embodiment, a field effect transistor includes a semiconductive layer configured to form a channel region; a pair of spaced conductively doped semiconductive regions in electrical connection with the channel region of the semiconductive layer; a gate intermediate the semiconductive regions; and a gate dielectric layer intermediate the semiconductive layer and the gate, the gate dielectric layer being configured to align the gate with the channel region of the semiconductive layer. In one aspect, chemical-mechanical polishing self-aligns the gate with the channel region. According to another aspect, a field emission device includes a transistor configured to control the emission of electrons from an emitter.

Abstract: A transistor (30) uses a single continuous base region (40) with an undulating structure. The semiconductor device is an insulated gate field effect transistor having a semiconductor substrate with a plurality of doped base branches, which extend into the semiconductor substrate, form into a single base region for the entire transistor. Each of the plurality of base branches (82) is undulating and of substantially constant width, and each of the base branches undulates in-phase with the immediately adjacent base branches. A continuous gate layer (34) overlies the semiconductor substrate and is self-aligned to the plurality of base branches. The undulating structure of the base region improves channel density, and thus lowers on-resistance, and the use of a single base region ensures that all portions of the base region throughout the device will be at a substantially constant electric potential.

Abstract: A gate electrode structure of a semiconductor device and a manufacturing method thereof are provided. The gate electrode structure includes a first silicon layer pattern formed of a polycrystalline silicon layer and a second silicon layer pattern having surface roughness lower than that of the first silicon layer pattern formed on the first silicon layer pattern.

Abstract: A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N+ and P+ diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N+ diffusion to said P+ diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P+ diffusion is formed in the N well in the pillar adjacent the distal end and a N+ diffusion is formed in the P well in the pillar adjacent the distal end.

Abstract: Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

Abstract: The present invention provides an integrated circuit which comprises a substrate having a plurality of device regions formed therein, said plurality of device regions being electrically isolated from each other by shallow trench isolation (STI) regions and said plurality of device regions each having opposing edges abutting its corresponding STI region; selected ones of said devices regions having a preselected first device width such that an oxide layer formed thereon includes substantially thicker perimeter regions, along said opposing edges, compared to a thinner central region that does not abut its corresponding STI region; and selected other ones of the device regions having a preselected device width substantially narrower in width than the first device width such that an oxide layer formed thereon includes perimeter regions, along opposing edges, that abut each other over its central region thereby preventing formation of a corresponding thinner central region.

Abstract: A method of production of a semiconductor device able to be miniaturized by preventing the decline of the hfe at a low current caused by an increase of a surface recombination current of a bipolar transistor and forming the external base region by self-alignment with respect to emitter polycrystalline silicon in the BiCMOS process. An intrinsic base region of a first semiconductor element is formed, an insulating film having an opening at an emitter formation region of part of the intrinsic base region is formed, and then an emitter electrode of the first semiconductor element and a protective film are formed on an insulating film having the opening. Next, a sidewall insulating film is left on the gate electrode side portion. Simultaneously, the insulating film is removed while partially leaving the emitter region forming-use insulating film under the emitter electrode.

Abstract: Described are structures for a device with a controllable dummy layer which can provide a low controllable trigger voltage and can be used as a first triggered device in ESD protection networks. A controllable dummy layer diode is provided which is structured as a butting diode with a dummy polysilicon layer above the butting region. The dummy polysilicon layer functions as an STI block to remove the STI between the n+ and p+ regions of the diode. In one embodiment the diode has the function of a controllable gate with a punchthrough-like-trigger, in which a capacitor-couple circuit couples a portion of the ESD voltage into the gate of the diode to provide a gate voltage. By changing the channel length under the gate of the diode as well as the gate voltage, the reverse-biased voltage of the diode is readily adjusted to a predetermined level. In a second embodiment the p+ region of the diode overlaps the n+ region turning the diode into a zener diode.

Abstract: A CMOS transistor and a memory cell transistor are formed without causing deterioration to reliability and performance. A step of covering a memory cell region with an HTO film and forming sidewalls in the CMOS transistor while exposing a diffusion region of the CMOS transistor, a step of depositing titanium, and a step of reacting the diffusion region with the titanium, forming a titanium silicide in the CMOS, transistor source and drain are provided.

Abstract: A wafer boat that supports a plurality of semiconductor wafers at a predetermined pitch, which are to be processed by a vertical thermal processing furnace, comprises a plurality of support columns; wafer support grooves formed in the support columns for supporting the peripheral edges of the wafers; and a film thickness equalization plate that is substantially the same size as the wafers, or is larger than the wafers, and is provided in wafer support grooves that are adjacent to one another in the vertical direction. This configuration ensures the same type of film is formed on the surface facing the surface of the wafer, achieving uniformity of the thus-formed film thickness.

Abstract: In a method of manufacturing a semiconductor device capable of reducing gate resistance by increasing the width of a conductive layer formed on a gate electrode without increasing the gate length, an extension is formed in an upper surface of a silicon substrate, and thereafter a silicon oxide film and a silicon nitride film are deposited on the overall surface. Then, the silicon nitride film and the silicon oxide film are anisotropically etched in this order. Then, another silicon oxide film is deposited on the overall surface and thereafter anisotropically etched. Then, ion implantation is performed through a gate electrode and a side wall serving as masks, to form an impurity region. Silicon is grown under conditions having selectivity for a silicon oxide film, to form a silicon growth layer. Then, cobalt is deposited on the overall surface and thereafter heat treatment is performed to form a cobalt silicide layer. Thereafter unreacted cobalt is removed.

Abstract: A structure and method for a capacitor-over-bitline integrated circuit device includes forming a device on a substrate, forming a capacitor contact electrically connected to the device, forming a bitline trench using the capacitor contact to align the bitline trench, forming insulating spacers in the bitline trench, forming a conductive bitline in the trench, the bitline being electrically connected to the device, forming an inter-layer dielectric over the bitline, and forming a capacitor above the inter-layer dielectric, such that the capacitor is electrically connected to the capacitor contact.

Abstract: There is disclosed a method of forming a buried strap (BS) and its quantum conducting barrier (QCB) in a structure wherein a doped polycrystalline silicon region is exposed at the bottom of a recess and separated from a monocrystalline region of a silicon substrate by a region of an insulating material. First, a thin continuous layer of undoped amorphous silicon is deposited by LPCVD to coat said regions. The surface of this layer is nitridized to produce a Si3N4 QCB film. Now, at least one dual layer comprised of an undoped amorphous silicon layer and a dopant monolayer is deposited onto the structure by LPCVD. The recess is filled with undoped amorphous silicon to terminate the buried strap and its QCB. Finally, the structure is heated to activate the dopants in the buried strap to allow an electrical continuity between said polycrystalline and monocrystalline regions through the QCB by a quantum mechanical effect. All these steps are performed in situ in the same LPCVD tool.

Abstract: A semiconductor device includes a semiconductor substrate having an active area including first and second impurity regions of a transistor, a gate formed over the active area of the semiconductor substrate and isolated from the semiconductor substrate, a first insulating interlayer formed on the semiconductor substrate and having first and second contact holes exposing the first and the second impurity regions, respectively, a capacitor having a storage electrode and a plate electrode, the storage electrode being connected electrically to the first impurity region through the first contact hole, a bit line contact pad connected electrically to the second impurity region through the second contact hole, a second insulating interlayer formed on the plate electrode and having a third contact hole exposing the bit line contact pad, and a bit line formed on the second insulating interlayer and in contact with the bit line contact pad through the third contact hole.

Abstract: A capacitor core is formed on a semiconductor device with a first conductive layer in contact with a plug. A mold is formed from a stack of alternately doped and undoped silicon dioxide layers on the sublayer with the stack comprising a bottom layer formed on top of the sublayer and each additional layer in the stack formed on a previous one of the layers in the stack. Pattern the silicon dioxide layers in the mold which are alternatingly doped and undoped to form an intercore, capacitor-core-shaping cavity in the stack of silicon dioxide layers reaching down through the stack to be bottom of the stack. Then perform differential etching of the silicon dioxide layers in the mold. Form undercut edges in the doped silicon dioxide layers with the undoped silicon dioxide layers having cantilevered ribs projecting from the stacks into the cavity to complete the mold.

Abstract: A fully recessed device structure and method for low power applications comprises a trenched floating gate and a trenched control gate formed in a single trench etched into a well junction region in a semiconductor substrate to provide a substantially planar topography for low power applications. The trenched floating gate is electrically isolated from the trenched control gate by an inter-gate dielectric layer formed inside the trench and on a top surface of the trenched floating gate. The trenched control gate is formed on a top surface of the inter-gate dielectric layer and preferably, has a top surface which is substantially planar with a top surface of the semiconductor substrate. The fully recessed structure further comprises a buried source region, a buried drain region and a channel region. The buried source region and the buried drain region are formed in the well junction region and are laterally separated by the trench.

Abstract: In the manufacture of a semiconductor memory device having a capacitor formed by arranging a dielectric film including two layers of a silicon oxide film and a silicon nitride film between two electrode films, a thin dielectric film is formed by forming the silicon nitride film on a silicon conductive film by thermally nitriding said silicon conductive film using NO gas, then laminating a silicon oxide film on said silicon nitride film by a CVD method. The erasing/writing speed of semiconductor memory devices, in particular of flash memories or the like, is improved.

Abstract: A method for fabricating a non-volatile memory on the semiconductor substrate is disclosed. First of all, a plurality of trench isolation regions are formed. Then, firstly implanting ions of a first conductivity type and second conductivity type are carried out. Secondly implanting ions of the first conductivity type and second conductivity type are carried out. Then, a first oxide layer is deposited and the first oxide layer is removed. A second oxide layer is deposited. A portion of second oxide is removed, thus, a portion of second oxide layer is remained. A third oxide layer is formed. A first polysilicon layer is formed. The first polysilicon layer is etched. A oxide-nitride-oxide layer is formed. Consequentially, the oxide-nitride-oxide layer are all etched. The second polysilicon on is formed. A portion of the second polysilicon layer, a portion of the first polysilicon layer, a portion of the third oxide layer and a portion of the second oxide layer are all etched. Thus, capacitor columns are formed.

Abstract: Sub-micron-dimensioned, asymmetrically-configured MOS and/or CMOS transistors are fabricated using removable sidewall spacers made of a material, such as UV-nitride, one of which is selectively treated subsequent to deposition, e.g., by ion implantation, to augment the etch rate thereof with a room temperature etchant, e.g., dilute aqueous HF. The treated spacer is removed with the dilute, aqueous HF prior to implantation of asymmetrically-configured, moderately or heavily-doped source/drain regions but prior to any post-implantation annealing processing, in order not to increase the etch resistance of the spacer material by thermally-induced densification.

Abstract: In one illustrative embodiment, the present invention is directed to forming a masking layer (104) above a semiconducting substrate (102), forming an opening (105) in the masking layer (104), forming sidewall spacers (109) that define an exposed surface of said substrate lying between the sidewall spacers (109), and forming a layer of gate dielectric material (108) on the exposed surface of the substrate. The method further comprises forming a layer of polysilicon in the opening (105) and on the gate dielectric layer (108), removing portions of the polysilicon layer lying outside the opening (105) to define a gate electrode (111), forming a layer of refractory metal above the gate electrode (111), converting at least some of the refractory metal layer to a metal silicide region (112) above the gate electrode (111), and removing the masking layer (104).

Abstract: A method for forming transistor devices with different spacer width for mixed-mode IC is provided. The method provides three different kinds of transistor devices on a wafer, two of them have their own spacer with different width, while the remaining one is without a spacer. The method comprises providing a semiconductor substrate having at least a first conductive gate, a second conductive gate and a third conductive gate formed thereon, and forming a first oxide layer over the first conductive gate, the second conductive gate and the third conductive gate. Then, a first etch operation is performed to form an oxide spacer along each sidewall of the first conductive gate, the second conductive gate and the third conductive gate. A first mask is then formed over the first conductive gate, and then the spacer is removed formed along each sidewall of the second conductive gate and the third conductive gate. After that, the first mask over the first conductive gate is removed.