Abstract: The invention relates to liquid-crystal media which comprise at least one compound selected from the group of the compounds of the formulae I to III 1

Abstract: A rare earth oxide in the form of substantially spherical particles having a Fisher diameter Df of 0.5 &mgr;m<Df<2.0 &mgr;m and a photomicrography particle diameter De of 0.5 &mgr;m<De<2.0 &mgr;m is prepared by heating and ripening an aqueous solution of water-soluble rare earth salts at 80° C. or higher while adding urea to the aqueous solution so as to keep a urea concentration of 10-50 g/liter, thereby forming a basic rare earth carbonate, and firing the basic rare earth carbonate.

Abstract: An optical filter comprises a transparent support and a filter layer. The filter layer has at least three absorption maximums in the wavelength region of 750 to 1,100 nm. Each of the three absorption maximums is in the wavelength regions of 750 to 850 nm, 851 to 950 nm, and 951 to 1,100 nm.

Abstract: A universal lifting device for elevating heavy off-the-road vehicles, e.g. mechanical shovels used in mining operations, is proposed to raise the upper revolving section of the shovel and allow for its lower wheeled base to be removed with a view to attending to the maintenance, for instance, of the rotation mechanism of the shovel. The lifting device comprises front and rear lifting beams to which various type of brackets can be removably mounted to ensure a proper positioning of the front and rear lifting beams with respect to the revolving frame of different models of mechanical shovels. Front and rear lifting points are provided to control the vertical displacement of the font and the rear lifting beams, respectively.

Abstract: A window opener is provided. In one embodiment the window opener may include a handle of predetermined width and length, the handle having a grabbing tip and a pivot pin. The window opener may also include a pole, repositionable with respect to the handle, wherein the pole has a first end, a second end, and a cleat in physical communication with the pivot pin. In another embodiment a method of sliding a stuck window within a window frame having a sash is provided. This method may include providing a handle having a proximate end, a distal end, and an opening with a pivot point. It also may include inserting a rigid pole having a plurality of cleats through the opening of the handle, aligning the cleat of the rigid pole with the pivot point of the handle, and applying force to the stuck window section by pivoting the handle in the cleat.

Abstract: A method for constructing a column and panel concrete fence which includes two or more columns, each of which comprises two portions which are separated from one another along one or more planes that are essentially parallel to the longitudinal axis of the column. A first half of a column is placed upon each of two or more footings. Then the ends of concrete panels which run between successive columns are placed upon such footings. Preferably, the panels are composed of two or more panel units which are mirror images of one another. Next a second half of each column is placed upon each of the footings. And, finally, concrete is poured into the resultant column.

Abstract: In a method of manufacturing a semiconductor device having first through third MOS transistors, using a first mask (311), wells (313, 314) and first threshold adjustment regions (315, 316) are formed at transistor areas (306n, 308n) for the second and the third MOS transistors in a semiconductor substrate (301). Next, using a second mask (319), second threshold adjustment regions (320, 321) are formed at transistor areas (304n and 308n) for the first and the third MOS transistors. In the transistor area for the third MOS transistor, both of the first threshold adjustment region and the second threshold adjustment region form a third adjustment region. Thus, using the two masks, three thresholds of the MOS transistors are obtained.

Abstract: A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling layer (520) which invades open surface pores (514) of xerogel (510).

Abstract: A semiconductor substrate, a field effect transistor, a method of forming a SiGe layer and a method of forming a strained Si layer using the same, and a method of manufacturing a field effect transistor are provided, which enable the threading dislocation density of the SiGe layer to be reduced and the surface roughness to be minimized. On top of a Si substrate 1 is provided a SiGe buffer layer 2, 12 constructed of a plurality of laminated layers comprising alternating layers of a SiGe gradient composition layer 2a, 12a in which the Ge composition ratio increases gradually from the Ge composition ratio of the base material, and a SiGe constant composition layer 2b, 12b which is provided on top of the gradient composition layer and in which the Ge composition ratio is equal to that of the upper surface of the gradient composition layer.

Abstract: A display is conducted by using a time gray-scale system, in which one frame period is divided into a plurality of sub-frame periods, and a voltage applied to an EL element of a pixel is varied on a sub-frame period basis. Because of this, a display device is provided in which the fluctuations in brightness caused by an environment temperature of an EL element are suppressed with a gray-scale display method that is unlikely to be influenced by variations in characteristics of TFTs in a pixel portion and that is unlikely to be influenced by variations in a display period.

Abstract: A circuit including at least one strained channel, enhancement mode FET, and at least one strained channel, depletion mode FET. The depletion mode FET includes an ion implanted dopant supply. In exemplary embodiments, the FETs are surface channel or buried channel MOSFETS. In another exemplary embodiment, the FETs are interconnected to form an inverter.

Abstract: An object of the present invention is to provide a pixel structure capable of shielding light between a TFT and a pixel without using a light shielding mask (black matrix) in an electro-optical display device. The present invention has a feature in that, as one of means for shielding light, a lamination film consisting of two colored layers (a lamination layer of a red-colored layer and a blue-colored layer) is formed on an opposing substrate as a light shielding portion so as to overlap with a TFT formed on a device electrode.

Abstract: A new High Dynamic Range charge detection concept useful for CCD and Active Pixel CMOS image sensors uses at least one transistor operating in a punch through mode for the charge detection node reset. The punch through operation significantly reduces the reset feed through which leads to a higher voltage swing available on the node for the signal. This in turn allows building smaller and thus more sensitive charge detection nodes. The undesirable artifacts, associated with the incomplete reset that are induced by the punch through operation, are completely removed by incorporating the CDS signal processing method into the signal processing chain. The incomplete reset artifact removal by the CDS technique is extended to all other resetting concepts that are modeled by a large reset time constant. The punch through concept is suitable for resetting Floating Diffusion charge detection nodes as well as Floating Gate charge detection nodes.

Abstract: A semiconductor diode structure comprising a Schottky junction, where a metal contact and a silicon carbide semiconducting layer of a first conducting type form said junction and where the edge of the junction exhibits a Junction Termination Extension (JTE) laterally surrounding the junction, said JTE having a charge profile with a stepwise or uniformly decreasing total charge or effective sheet charge density from an initial value to a zero or almost zero total charge at the outermost edge of the termination following a radial direction from the centre part of the JTE towards the outermost edge of the termination. The object of the junction termination extension is to control the electric field at the periphery of the diode.

Abstract: A semiconductor device of the present invention comprises Al0.3Ga0.7N layer 4 and Al0.1Ga0.9N layer 5 having different Al contents as an electron supply layer on GaN layer 6 serving as an active layer. An area where Al0.3Ga0.7N layer 4 is formed is used as a low resistance area, while an area where Al0.1Ga0.9N layer 5 is formed is used as a high resistance area. As a result, a distribution of two-dimensional electrons serving as carriers is produced within a horizontal plane perpendicular to the thickness direction of the layers to form a desired device configuration. For example, when the configuration is applied to a transistor configuration, a channel concentration under a gate is reduced to improve withstand voltage between the gate and a drain, and at the same time, a channel concentration in source and drain areas is increased to realize low contact resistance.

Abstract: An amorphous semiconductor film is etched so that a width of a narrowest portion thereof is 100 &mgr;m or less, thereby forming island semiconductor regions. By irradiating an intense light such as a laser into the island semiconductor regions, photo-annealing is performed to crystallize it. Then, of end portions (peripheral portions) of the island semiconductor regions, at least a portion used to form a channel of a thin film transistor (TFT), or a portion that a gate electrode crosses is etched, so that a region that the distortion is accumulated is removed. By using such semiconductor regions, a TFT is produced.

Abstract: A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis. The quantum dot layer is preferably comprised of AlxByInzGa1-x-y-zN, InGaN1-a-bPaAsb, or AlxByInzGa1-x-y-zN1-a-bPaAsb.

Abstract: This invention aims to provide a white light emission diode arranged so that t rays emitted from an exciting element comprising a n-type semiconductor layer and a p-type semiconductor layer are converted by a wavelength converting element to white light which is then irradiated through molded resin. The white light emission diode offers a high color rendering effect desired for liquid crystal back light and minimizes deterioration of the molded resin to improve its light emission life characteristic. The wavelength converting element is provided on one surface of the exciting element and an insulating film is deposited on the other surface with interposition of a p-type ohmic electrode exhibiting a high reflectivity in UV wavelength band. The exciting element has its side surface covered with a n-type ohmic electrode exhibiting a high reflectivity in UV wavelength band.

Abstract: An optoelectronic semiconductor chip has an active layer containing a photon-emitting zone. The active layer is attached to a carrier member at a bonding side of the active layer. The active layer has at least one recess therein with a cross-sectional area that decreases with increasing depth into said active layer proceeding from said bonding side.

Abstract: A blue light emitting diode with sapphire substrate and method for making the same is disclosed. The blue light emitting diode comprises a sapphire substrate having a at least one channel penetrating the sapphire substrate, two GaN thin film with similar thickness on top and bottom surface of the sapphire substrate and in contact with in the channel, an anode and a cathode on the bottom surface of the lower GaN thin film and the upper surface of the epitaxy layer. The arrangement of the channel provides a conductive passage between the anode and the cathode and realizes a vertical type LED with reduced operation area. Moreover, the polishing process is simplified and the yield is enhanced.

Abstract: A semiconductor device for lowering a triggering voltage includes a semiconductor substrate with a first conductivity; a semiconductor region formed in the substrate having a second conductivity; a first region formed in the substrate, having the first conductivity and being apart from the semiconductor region; a second region formed in the substrate having the second conductivity and being spaced apart from the semiconductor region and first region; a third region formed in the substrate, having the second conductivity and being spaced apart from the semiconductor region, the first and second regions; a fourth region formed in the semiconductor region, having the second conductivity and being connected to the third region through a conductive material; a fifth region formed in the semiconductor region, having the first conductivity and being spaced apart from the fourth region; and a sixth region formed in the semiconductor region, having the second conductivity and being spaced apart from the fourth and fif

Abstract: A semiconductor device having a photo diode which has substantially the same sensitivity to a plurality of light having different wavelengths, comprising a first conductivity type semiconductor layer and a second conductivity type semiconductor layer formed at a surface layer portion of said first conductivity type semiconductor layer, wherein the sensitivity to light of a first wavelength and the sensitivity to light of a second wavelength which is different from said first wavelength are made substantially the same by designing a region in which a depletion layer spreads from a junction of said first conductivity type semiconductor layer and said second conductivity type semiconductor layer when an inverse bias is applied to said first conductivity type semiconductor layer and said second conductivity type semiconductor layer, for example, by designing it to spread in a region of 3 to 6 &mgr;m or a region of 2 to 7 &mgr;m from the surface of the second conductivity type semiconductor layer in the depth dire

Abstract: A solid state p-n heterojunction comprising an electron conductor and a hole conductor; it further comprises a sensitising semiconductor, said sensitizing semiconductor being located at an interface between said electron conductor and said hole conductor. In particular, the sensitizing semiconductor is in form of quantum-dots. A solid state sensitized photovoltaic cell comprises such a layered heterojunction between two electrodes.

Abstract: A process for forming a thin layer of Silicon nanocrystals in an oxide layer is disclosed. The process includes, on a semiconductive substrate, thermally oxidizing a first portion of the substrate into an oxide layer, forming Silicon ions within the layer of oxide, and thermally treating the Silicon ions to become the thin layer of Silicon nanocrystals. In the inventive process the formation of the Silicon ions is by ionic implantation of the Silicon ions into the oxide at an ionization energy of between 0.1 keV and 7 keV, and preferably between 1 and 5 keV. This allows the Silicon atoms to coalesce in a lower temperature than would otherwise be possible. Additionally, more than one layer of nanocrystals can be formed by performing more than one implantation at more than one energy level. Embodiments of the invention can be used to form non-volatile memory devices with a very high quality having a very small size.

Abstract: A semiconductor device comprising a substrate, a conductor and an insulating film provided on the surface of the substrate, part of the surface of the substrate being electrically connected with the conductor through a contact hole made in the insulating film, wherein a barrier layer present between part of the surface of the substrate and the conductor is provided only on the bottom of the contact hole, and the barrier layer provided on the bottom comprises amorphous titanium silicon nitride.

Abstract: A semiconductor memory has a buried bit line structure. One end of the bit line and one end of the diffused impurity layer are connected by being overlapped with each other, and the surface of the source/drain of the selection transistor and the surface of the diffused impurity layer including the connecting portion are silicidized by using metals having high melting points, Ti and Si in this case, thereby forming the titanium silicide layer thereon. This invention not only solves the various problems arising from the buried bit line structure but also realizes sure formation of the silicide, low resistance, greater fineness and high speed operation.

Abstract: The microreactor is completely integrated and is formed by a semiconductor body having a surface and housing at least one buried channel accessible from the surface of the semiconductor body through two trenches. A heating element extends above the surface over the channel and a resist region extends above the heating element and defines an inlet reservoir and an outlet reservoir. The reservoirs are connected to the trenches and have, in cross-section, a larger area than the trenches. The outlet reservoir has a larger area than the inlet reservoir. A sensing electrode extends above the surface and inside the outlet reservoir.

Abstract: To transfer signal charges at high speed with small noise, there is provided a charge transfer apparatus including a semiconductor substrate of one conductivity type, a charge transfer region of a conductivity type opposite to that of the semiconductor substrate that is formed in the semiconductor substrate and joined to the semiconductor substrate to form a diode, a signal charge input portion which inputs a signal charge to the charge transfer region, a signal charge output portion which accumulates the signal charge transferred from the charge transfer region, and a plurality of independent potential supply terminals which supply a potential gradient to the semiconductor substrate, wherein the signal charge in the charge transfer region is transferred by the potential gradient formed by the plurality of potential supply terminals.

Abstract: A defect removable semiconductor element and the manufacturing method thereof are provided with a protective layer covering fuses exposed at a part of the redundancy memory cell region, the layer being thinner than the one covering the main memory cell region, so that a predetermined fuse is cut off for removing a defect without damaging adjacent fuses even if the amount of energy of laser beam to be applied is greater and the size of the spot to be focused is bigger, thereby improving operational conditions in the energy of the laser beam to be applied and the size of a spot to be focused and the operational reliability in removing a defect.

Abstract: A millimeter wave module includes a silicon substrate with first and second cavityes formed by anisotropic etching on the silicon substrate, and a glass substrate having a microstrip filter pattern and microbumps for connecting the glass substrate to the silicon substrate. A filter is provided using an air layer as a dielectric disposed in the first cavity. An MMIC is mounted by the flip chip method over the second air layer. A coplanar waveguide is on the silicon substrate for connecting the filter and MMIC. The filter having low loss is achieved because it has the microstrip structure using air as an insulating layer. Also change in characteristics of the MMIC during mounting is eliminated because the MMIC is protected by contacting air. Accordingly, the millimeter wave module has excellent characteristics and is made using a simple method.

Abstract: The present invention concerns a structure (21) formed on a substrate (23) formed of a substrate material intended to be etched by a reactive agent, this structure including at least one first outer layer (29), or passivating layer, which has a first elastic property. This structure further includes at least one second outer layer (33) formed above the first layer, so that the second layer has a second elastic property which is different to the first elastic property. In the event that the second elastic property provides the second layer with greater elasticity in compression than the first layer, said structure has advantageously a yield higher than 99.8%.

Abstract: A thin film transistor is disclosed, including an insulating substrate, a semiconductor layer formed on the insulating substrate, the semiconductor layer having an active region and an impurity region, a gate insulating layer formed on the active region of the semiconductor layer, a first gate metal layer formed on a predetermined portion of the active region of the semiconductor layer to define a channel region, and a second gate metal layer formed on the first gate metal layer. The first and second gate metal layers have different compositions, such that the second gate metal layer etches faster than the first gate metal layer, thereby preventing formation of a hillock. A first protective layer is formed over the structure, then a light shielding layer, and then a second protective layer is formed over the light shielding layer.

Abstract: By forming a redundant circuit of an extra wiring accompanied with no decrease in an aperture ratio for a photoelectric conversion element, the yield is prevented from being reduced due to wire breaking during a panel manufacturing process.

Abstract: A ferroelectric memory according to the present invention includes a passive matrix array in which memory cells formed of ferroelectric capacitors are arranged, and a peripheral circuit for the passive matrix array. The passive matrix array is formed of a passive matrix array microchip, and the peripheral circuit such as a word line driver circuit or a bit line driver circuit is formed on a peripheral circuit substrate, thereby integrating the passive matrix array microchip on the peripheral circuit substrate. Since this allows the passive matrix array and the peripheral circuit therefor to be separately fabricated, the peripheral circuit is not adversely affected when fabricating the passive matrix array, thereby decreasing the degree of limitation in the fabrication process.

Abstract: DRAM memory cell for a DRAM memory having:

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s

Abstract: The present invention provides a method of forming a metal oxide metal (MOM) capacitor on a substrate, such as a silicon substrate, of a semiconductor wafer in a rapid thermal process (RTP) machine. The MOM capacitor is fabricated by forming a metal layer on the semiconductor substrate. The metal layer is then subjected to a first rapid thermal process in a substantially inert but nitrogen-free atmosphere that consumes a portion of the metal layer to form a first metal electrode layer and a silicide layer between the first metal electrode and the semiconductor substrate. The semiconductor wafer is then subjected to a second rapid thermal process. During this process, the remaining portion of the metal layer is oxidized to form a metal oxide on the first metal electrode, which serves as the dielectric layer of the MOM capacitor. Following the formation of the dielectric layer, a second metal electrode layer is then conventionally formed on the metal oxide, which completes the formation of the MOM capacitor.

Abstract: Memory cells each include one transistor and one capacitor. A memory node of the capacitor is disposed in a first indentation, while a gate electrode of the transistor is disposed in a second indentation. An upper source/drain region, a channel region, and a lower source/drain region of the transistor are disposed above one another and each adjoin both a first flank of the first indentation and the second indentation. At least a portion of the first flank is provided with a capacitor dielectric, which in the region of the lower source/drain region has a recess, in which the memory node adjoins the lower source/drain region. The second indentation of a first one of the memory cells can adjoin the memory node that is disposed in the first indentation of a second one of the memory cells. The second indentations can be parts of word line trenches, which extend transversely to insulation trenches.

Abstract: A low-capacitance bonding pad for a semiconductor device. A diffusion region is formed in a substrate, and a bonding pad is formed on the substrate and aligned with the diffusion region. The bonding pad is made from a stacked metal layer and a metal layer. The stacked metal layer is made from a plurality of metal layers and a plurality of dielectric layers, and the metal layers and the dielectric layers are stacked alternately. The metal layers stacked in the stacked metal layer are formed with small areas. Each of the metal layers stacked in the stacked metal layer is coupled with the adjacent metal layer by via plugs.

Abstract: A semiconductor device and a method of manufacturing thereof can be gained wherein the occurrence of defects can be prevented and it is possible to reduce the manufacturing cost. The semiconductor device includes a capacitor electrode, an insulating layer and a wiring layer. The capacitor electrode is formed on the semiconductor substrate. The insulating film which is formed on the capacitor electrode has a trench which exposes part of the capacitor electrode and has an upper surface. The wiring layer fills in the inside of the trench, has an upper surface and is connected with the capacitor electrode. The upper surface of the wiring layer is located on approximately the same plane as the upper surface of the insulating film.

Abstract: Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a substrate node location and has an opening defining a first interior area. A second container is joined with the node location and has an opening defining a second interior area. The areas are spaced apart from one another in a non-overlapping relationship. A dielectric layer and a conductive capacitor electrode layer are disposed operably proximate the first and second containers. In another embodiment, the first and second containers are generally elongate and extend away from the node location along respective first and second central axes. The axes are different and spaced apart from one another. In yet another embodiment, a conductive layer of material is disposed over and in electrical communication with a substrate node location. The layer of material has an outer surface with a first region and a second region spaced apart from the first region.

Abstract: In order to provide a nonvolatile semiconductor storage device designed to take off such existing restraint on the degree of freedom of device design as needed for the purpose of securing design margin, thus realizing a ferroelectric, nonvolatile storage device of high integration density, there is disclosed a capacitor using a ferroelectric thin film is provided, so that the apparent coercive electric field value in the operational guaranteed margin temperature of the nonvolatile semiconductor storage device when regarded as the voltage applied to the capacitor remains within the range of design margin of the nonvolatile semiconductor storage device at the coercive electric field value at the specified temperature, in which a metal oxide of a layer structure having the ferroelectric-to-normal dielectric phase transition point of 800° C. or higher may be used for the ferroelectric thin film.

Abstract: A microelectronic structure is described which contains a first conductive layer for preventing oxygen diffusion at the structure. The first conductive layer contains a base material and at least one oxygen-binding admixture that is provided with at least one element from the fourth subgroup or the lanthane group. In a preferred embodiment, the microelectronic structure is used in semiconductor storage components with a metal oxide dielectric as a condenser dielectric.

Abstract: A method of manufacturing a semiconductor device, comprises the following steps. A silicon film is formed on a semiconductor substrate. A first silicon oxide film is formed on the silicon film by CVD. The silicon film and the first silicon oxide film are heated in an oxidizing atmosphere, thereby increasing the density of the first silicon oxide film and forming a thermal oxide film between the silicon film and the first silicon oxide film.

Abstract: Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a body. A first resistive element is received by the substrate and connected between the transistor's gate and the body. A second resistive element is received by the substrate and connected between the body and a reference voltage node. The first and second resistive elements form a voltage divider which is configured to selectively change threshold voltages of the field effect transistor with state changes in the gate voltage. In a preferred embodiment, first and second diode assemblies are positioned over the substrate and connected between the gate and body, and the body and a reference voltage node to provide the voltage divider.

Abstract: A semiconductor device comprises a memory cell array in which a plurality of nonvolatile semiconductor memory devices are arrayed in a row direction and a column direction. Each of the nonvolatile semiconductor memory devices includes a silicon semiconductor substrate, a floating gate disposed on the silicon semiconductor substrate through a gate insulating layer interposed therebetween, a second insulating layer disposed on the floating gate, and a control gate which is isolated from the floating gate and extends in the row direction. The nonvolatile semiconductor memory devices which are adjacent each other in the row direction are isolated by element isolation regions extending in the column direction. One of angles formed where a major axis direction of the floating gate in a planar configuration of the memory cell array intersects the column direction is an acute angle.

Abstract: A non-volatile memory device includes a floating gate formed over a semiconductor substrate. At one end of the floating gate, there is a tapered protrusion having a horn-like or bird's beak shape. A control gate covers the floating gate except for the tapered protrusion. Sidewall spacers are formed adjacent to the floating gate and the control gate. An erasing gate is formed over the tapered protrusion of the floating gate.

Abstract: A TFT memory 11 is provided with a polysilicon layer 22, wherein each region of the source 22a, the channel 22b and the drain 22c are formed on a substrate 21, and gate oxide films (insulating films) 23 and 25 are formed on the polysilicon layer 22; and a plurality of silicon particles 24 for trapping the charge of injected carriers are placed between the gate oxide films 23 and 25. Specifically, the gate oxide films comprise a first gate oxide film 23 and a second gate oxide film 25 formed on the first gate oxide film 23; the plurality of silicon particles 24 are located between the first gate oxide film 23 and the second gate oxide film 25, and the first gate oxide film 23 is formed in an extremely thin thickness.

Abstract: A VD (vertical diffusion) MOSFET device for use in RF power applications has a split gate structure and an additional, dummy gate is provided between the spaced apart gates and, in operation of the device, is electrically coupled to source electrodes provided outside of the gates. The split gate structure reduces gate overlap capacitance and the dummy gate induces depletion in the semiconductor body of the device and reduces the substrate capacitance. The gate overlap capacitance and the substrate capacitance both contribute to the feedback capacitance of the device which has to be as low as possible for high frequency operation. By reducing both of these components, the invention provides advantageous high frequency operation.

Abstract: A high voltage semiconductor device having a high breakdown voltage isolation region, in which the high breakdown voltage isolation region and a junction termination including a lateral DMOS transistor are formed between a high voltage region and a low voltage region. The lateral DMOS transistor and the high breakdown voltage isolation region are formed on a structure in which a semiconductor substrate of a first conductivity type and an epitaxial layer of a second conductivity type are sequentially formed. The epitaxial layers in the high breakdown voltage isolation region, the lateral DMOS transistor and the high voltage region are isolated from each other by first diffusion regions of a first conductivity type, which are formed between a certain depth of the semiconductor substrate and a certain depth of the epitaxial layer.