Abstract: A bus extender for extending synchronous busses of limited length provides convenient access to bus cards in ATE systems. The bus extender plugs into a synchronous bus, for example, a PCI bus, and a cable carries bus signals to a remote location, where a remote card is engaged. The bus extender supports both initiator (master) and target (slave) modes of the remote card, and communicates with the remote card in the native protocol of the bus. The bus extender operates without requiring separate control from the bus. For example, the bus extender does not require its own device driver. The bus extender includes a bus snooper circuit that monitors bus transactions with the remote card and stores configuration data. The bus snooper circuit responds locally on behalf of the remote card to bus requests that require rapid responses. The bus extender further includes a state machine that copies the stored configuration data to the remote card to reset the remote card without requiring a reset of the bus.

Abstract: A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length. A trace FIFO (800) is provided for tracing a sequence of instruction addresses to assist with software or hardware debugging. In order to conserve space, only the addresses of an instruction just before (M+K, P+Q) and just after (P, R) a discontinuity are stored in the trace FIFO. A sequence of instruction lengths (SEC13LPC) is also stored in the trace FIFO so that the sequence of instruction addresses can be reconstructed by interpolating between two discontinuity points (P to P+Q).

Abstract: The present invention discloses a fault indicator circuit in a system having a plurality of circuit blocks each provided with an individual power source. Each of the circuit blocks needs to indicate a fault when a fault occurs in the individual power source of the circuit block. The fault indicator circuit of the present invention includes a fault indicator which performs fault indication in response to a fault indication control signal from the circuit block having the fault or one of the other circuit blocks. When a fault occurs in the individual power source of a circuit block, the fault indicator performs fault indication by means of power supplied from the individual power source of one of the other circuit blocks. An input determiner which reduces the level of the fault indicator control signal outputted from one of the other circuit blocks is disposed at the input terminal of a gate circuit into which the fault indication control signal is inputted from one of the other circuit blocks.

Abstract: An integrated multi-channel Fiber Channel analyzer provides coordinated and cooperative triggering and capture of data across multiple channels in a Fiber Channel network. The integrated multi-channel analyzer accommodates up to sixteen separate analyzer channels in a single cabinet. Each analyzer channel is comprised of an input port connection to the Fiber Channel network, a trace buffer memory that captures data and logic circuitry that controls the operation of the trace buffer memory in response to a status condition. A high speed status bus is connected to each analyzer channel and propagates the status conditions of each analyzer channel to all other analyzer channels. In this way, the integrated multi-channel analyzer allows for distributive control over triggering decisions across multiple analyzer channels, and also allows for multi-level triggering where different conditions may be detected by different analyzer channels.

Abstract: A write driver circuit includes a drive circuit having a first drive node adapted to receive a first voltage, a second drive node, an input adapted to receive a data signal, and an output. The drive circuit couples the output to the first voltage node when the data signal has a first logic voltage, and couples the output to the second drive node when the data signal has a second logic voltage. A test circuit has an input adapted to receive a test mode signal, and an output coupled to the second drive node. The test circuit develops a first impedance between the second drive node and a second voltage source when the test mode signal is active, and develops a second impedance between the second drive node and the second voltage source when the test mode signal is inactive.

Abstract: A method for analyzing a scan dump assigns a first latch to a first value, compares the first latch output to the first value for spatial alignment. The method then assigns a second latch to either a second or third value. The second value corresponds to before an event. The third value corresponds to after an event and may be incremented with ongoing clock cycles.

Abstract: The present invention provides a method and apparatus for preventing show-thru (and therefore misinsertion of unintended traffic) among uplink beams transmitted to a satellite. The method includes the steps of selecting (402) an uplink A stagger value, selecting an uplink B stagger value, coding (404) uplink A data to generate coded uplink A data, and coding (406) uplink B data to generate coded uplink B data. Subsequently, the method transmits (412) the coded uplink A data, staggered by the uplink A stagger value, in the uplink A and further transmits (414) the coded uplink B data, staggered by the uplink B stagger value, in the uplink B. During coding (404, 406), the method may use a full length error correcting code capable of correcting t errors. In such a case, the method generally selects an uplink B stagger value differing from the uplink A stagger value by more than t codeword symbols.

Abstract: A method is presented for estimating the reliability of a data sequence after Viterbi decoding. Within the Viterbi decoding, corresponding to an initial time instant, the possible initial states for the Viterbi decoding are established (801). After proceeding to a subsequent time instant (804), at each state corresponding to the present time instant, a surviving trellis path is selected among the trellis paths coming into that state (805). The steps of proceeding and selecting are repeated until a final time instant (807), and at said final time instant a final surviving trellis path is selected to represent the decoded data sequence. At the selection step of the Viterbi decoding, a characteristic reliability metric is updated separately in association with each selected surviving trellis path (806).

Abstract: There is disclosed a cache memory for use in a data processor. The cache memory comprises a first static random access memory (SRAM) that receives up to N incoming bytes of data on an input bus and that stores the up to N incoming bytes of data in an N-byte addressable location. M incoming bytes of data may be written in each of the N-byte addressable locations during a write operation (where M may be less than N) and the M written bytes of data and N−M unwritten bytes of data are output from each N-byte addressable location on an output bus of the first SRAM during each write operation. The cache memory also comprises a parity generator coupled to the first SRAM that receives the M written bytes of data and the N−M unwritten bytes of data and generates at least one write parity bit associated with the M written bytes of data and the N−M unwritten bytes of data.

Abstract: A system within a complementary logic circuit having a true tree and a complement tree, for correcting an illegal non-complementary output caused by a defect in either tree. A complementary logic circuit has a true tree for producing a true signal and a complement tree for producing a complement signal. The true signal is utilized to generate a true output signal from the complementary logic circuit and the complement signal is utilized to generate a complement output signal from the complementary logic circuit. Multiplexing means within the true and complement trees are utilized to selectively replace the true (complement) signal with the complement (true) signal within the true (complement) tree, such that the complement (true) tree is utilized to correct the occurrence of a proscribed non-complementary condition at the output of the complementary logic circuit to diagnose a defect during diagnostic testing or to override a defect during normal runtime operation.

Abstract: A method and system are disclosed for improving a yield of circuits produced from a semiconductor wafer. A plurality of design rules are established for designing a layout of the circuit within the wafer. A yield-limiting set of the plurality of design rules are selected. Adherence to each of the set of rules throughout all of the layout reduces the yield. For each one of the set of rules, a recommended value is determined. A percentage of occasions each one of the set should be exceeded within the layout is also determined. The layout is then designed so that each one of the set of the plurality of design rules meets or exceeds the recommended value more often than the percentage.

Abstract: A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.

Abstract: A method of converting or translating a layout or schematic netlist to a simulation netlist, comprising the steps of identifying net-shorting elements in the layout or schematic netlist and automatically replacing at least one such net-shorting element with an RC network to generate the simulation netlist.

Abstract: A method and system for use in wafer fabrication quality control. The method and system make quantitative a qualitative integrated circuit wafer defect signature. In response to the quantitativize wafer fabrication defect signature, the method and system identify at least one cause of the defect signature.

Abstract: An apparatus or method for testing the setup time and hold time specifications of a chip. An apparatus according to the invention would include a first chip, a second chip, and multiple links coupling the first chip to the second chip. One of the links carries a clock signal between the chips. Other links carrying data have propagation delays different from the propagation delay of the link carrying the clock signal. The relation of the delays for the data links to the delay for the clock link determines a particular setup and/or hold time tested.

Abstract: An automated method of analyzing crosstalk in a digital logic integrated circuit on a digital computer is described. The method uses available software to make an extracted, parameterized netlist from a layout of the integrated circuit. The netlist has gate and black box invocations as well as transistor invocations. Library models are used to find driving resistances and capacitances associated with the gate and black-box invocations. For at least one potential victim wire of the plurality of wires, a subset of the wires of the chip are found to be potential aggressor wires to the victim wire. The aggressor wires are combined into a common aggressor. A risetime of the common aggressor is calculated and used to calculate the magnitude of coupled noise on the victim wire induced by the aggressor wires. An alarm threshold for each potential victim wire is determined based upon the type of logic gate that receives the victim wire.

Abstract: In accordance with a timing verifying method of the present invention, the step of calculating a variation delay time composed of a wire delay time and a cell delay time in consideration of a process varying condition is performed independently of the step of performing logic simulation of a semiconductor integrated circuit based on the calculated variation delay time.

Abstract: A method of control cell placement for an integrated circuit design includes the steps of receiving as input a datapath description including an initial set of coordinates for a plurality of control cells; ordering the plurality of control cells in a sequence (1, 2, 3, . . . , n) according to distance between each of the plurality of control cells and at least one fixed control cell in the plurality of control cells wherein n is the number of control cells in the datapath description; iteratively calculating globally optimum coordinates for the each of the plurality of control cells according to the sequence i=1, 2, 3, . . . , n from a global maximum of a control cell placement function; and generating as output the calculated globally optimum coordinates for the each of the plurality of control cells.

Abstract: Methods for improving the performance of VLSI layouts designed by a timing driven physical design tool. According to one embodiment of the present invention cells of a circuit design are placed in a placement of an integrated circuit, and wires are routed between the cells to complete a layout of the integrated circuit having a number of nets. The placement is analyzed for timing performance, and an improved location is identified for each cell in the placement. The improved location is identified based on an estimated savings in delays caused by all of the nets in the layout to a signal propagating through the layout when the cell is placed in the improved location and a net criticality of each net in the layout.

Abstract: The specification discloses a for reduction of net delays and insertion of buffers in a logic tree having a root and a plurality of leaves. The steps of the method include inserting a plurality of auxiliary nodes into the, defining discrete, approximate scales for delay, load, and ramp time, constructing a set of buffers chains for later insertion into the net tree, determining for each node on the tree a tradeoff function relating ramp time, departure time and load at the node, for each node, removing combinations of the tradeoff functions and the buffer chains, which when inserted into the tradeoff function, lead to a ramp time which exceeds a predetermined maximum allowable ramp time, for each node, using the tradeoff function to determine a minimum delay to insert, and inserting the buffer chain corresponding to the minimum delay as determined by the tradeoff function.

Abstract: A method generates information for a window view of an integrated circuit from layout-formatted data such as GDSII formatted data. The method includes generating outer boundary boxes for structures of the integrated circuit from the layout-formatted data, generating a build file by including information of structures having outer boundary boxes completely or partially in a window, and generating information of the window view from the information thus included in the build file. In generating the build file, information of structures having outer boundary boxes completely outside the window are excluded from the build file. Also excluded is information of structures having areas less than a threshold value.

Abstract: Disclosed is a subgrid detailed router that performs searches for wire locations at the grid level. Once a solution is found, the wire is placed in a based upon a finer subgrid. Specifically, the present invention includes subgrids that in a preferred embodiment have a resolution that is 16X greater than the resolution of the conventional grids. This increased resolution is useful for improving routing density with variable width and variable spacing designs. In operation, the subgrid detailed router of the present invention searches at the grid level for potential wire paths using a code associated with each grid. This code contains data corresponding to each of the subgrids, such that upon completion of a routing a net, information exists that allows for the placement of the net at locations corresponding to the subgrid that has finer resolution than the grid which was used to implement the routing search.

Abstract: Described are systems and methods for measuring the size uniformity of circuit features defined by the critical dimension of an integrated-circuit fabrication process. An integrated circuit is configured to include a number of oscillators, each occupying a region of the integrated circuit. Each oscillator oscillates at a frequency that depends on the critical dimension of features in the region in which it is formed. Consequently, the critical dimensions of regions across the surface of the integrated circuit can be mapped and compared by comparing the oscillation frequencies of identical oscillators formed in various regions of the integrated circuit. In programmable logic devices, oscillators can be implemented using programmable logic resources. In other embodiments, small, simple oscillators can be placed at various locations on the integrated circuit.

Abstract: An FPGA includes a configuration control circuit having an internal memory that stores default configuration data which may configure the some or all of FPGA's logic blocks into a default state. A compressed bitstream includes one or more frame control bits indicative of whether corresponding configuration data is included in the bitstream. During configuration of the FPGA, the compressed bitstream is provided to the configuration control circuit from the external memory. As each frame control bit is received, its logic state is determined. If the frame control bit indicates that corresponding configuration data is included in the bitstream, the corresponding configuration data is read from the bitstream into a frame register. If, on the other hand, the frame control bit indicates that corresponding configuration data is not in the bitstream, default configuration data is read from the internal memory into the frame register.

Abstract: A data processing apparatus comprises a grid pattern area calculation section (24) for calculating the minimum grid and the present area of a circuit element for each layer of circuit patterns given by CAD data (1); an overlap area calculation section (25) for calculating an overlap area of present areas; and a composition/division optimization judgment section (26) for judging by a criterion whether the layers including the overlap area should be processed according to a single common grid or different grids. Each layer can be assigned the grid with the minimum accuracy required for the layer. A grid with more minute accuracy than it requires may not be used. Operation load in making reticle mask data and processing load in actually performing exposure or the like are thereby considerably relieved.

Abstract: Methods and apparatus for controlling an automated material handling procedure. The method includes receiving a recipe file comprising component information and mapping information; interacting with a user to create a procedure for executing a set of material handling steps; and causing a automated material-handling apparatus to carry out the set of material-handling steps by executing the procedure. The mapping information relates a source component and a destination component. The mapping information defines one or more transfers of at least one source component material to at least one destination component location. The method includes providing to the user an assortment of pre-programmed code objects and receiving from the user a selection and arrangement of the pre-programmed code objects. The procedure is defined by the user's selection and arrangement.

Abstract: A process and system for optimizing an invocation of a method is provided. A determination is made to compile a calling method, and a call to a callee method is detected within the first method. The callee method may be a non-final, virtual method, and a determination may be made that the callee method has not been previously overridden. The callee method is then inlined within the first method. In addition, no conditional statements are inserted into the calling method along with the inlined method. The determination to compile and optimize these methods may be made by a just-in-time compiler, and if the methods are Java methods, then a Java just-in-time compiler performs the optimization process. If a determination is made to load a class that contains a method that overrides the callee method, then the calling method is recompiled or patched.

Abstract: A programmatic method transforms a nested loop in a high level programming language into a set of parallel processes, each a single time loop, such that the parallel processes satisfy a specified design constraint. Another programmatic method synthesizes a processor array from the set of parallel processes and a specified design constraint.

Abstract: Disclosed is a system, method, and program for creating a file, such as a batch file, that is capable of executing on one of many different operating systems. An object is processed including a plurality of instructions. Each instruction is associated with at least one executable function. A determination is made of an operating system in which the generated file will be executed. For each instruction in the object, a native operating system command is generated that is capable of executing the function associated with the instruction on the determined operating system. Each generated native operating system command is inserted into the file. Execution of the file on the determined operating system will execute the native operating system commands in the file to perform the functions associated with the instructions included in the object.

Abstract: The invention relates to a method and an arrangement of assigning an information-category and a priority of exposure for spots or blocks of information in a digital information system comprising interfaces for data and telecommunication for round-the-clock transmission of information at places accessible to and frequented by the general public including places where television sets are placed, such that a control center has communication interfaces for coordinating and controlling display devices, with the control center being able to create and update an exposure list in real time. The exposure list contains information including how many times an information is to be exposed during a specific time period. Single spots or blocks of information to a specific information-category and a priority for exposure.

Abstract: In a program information broadcasting system, it is aimed to minimize time for retrieval of program by viewers in operating an electronic program guide or time for waiting when applying for subscription. As a program information broadcasting system, program elements constituting a broadcasting program are divided into a plurality of items and are turned to data at a center, and a master data 21 of a program information to recognize the program is prepared. From the data constituting the master data, minimal necessary items for preparation of a program table are extracted, and a program basic information 22 is prepared. Said master data and said program basic information are transmitted simultaneously with the broadcasting, and said program basic information is received, reproduced and displayed before receiving of the master data at a receiving terminal unit 31 is completed.

Abstract: An architecture for convergence systems is disclosed. The architecture includes a hardware component providing a convergence environment. A channel map services component includes a listing of receivers of programming associated with the convergence environment and a listing of channels associated with the receivers. A content services component includes a listing of programming events associated with the channels of the receivers. The content services component also includes a listing of the times of programming events. A TV services component uses the channel map services component, and the content services component to control the hardware component of the convergence environment to manage the hardware component of the convergence environment. The TV services component controls the audio/video multiplexer to reroute programing signals from receivers to outputs of the audio/video multiplexer and various devices attached to the outputs, at various times.

Abstract: An in-flight entertainment system provides live video/audio programming to passengers and operators over an aircraft video/audio distribution system. The programming signals are derived from satellite broadcast signals that may be in either circular polarized form or linear polarized form. The broadcast signals are collected by two probes and extracted as right and left circular polarized signals. The right and left circular polarized signals are converted into either circular or linear polarized IF signals, and the IF signals are processed by a receiver/decoder unit to produce the live video/audio programming signals.

Abstract: A method for scheduling events between first and second video processing devices coupled together wherein each device having at least one event timer for storing a scheduled event. The method involves programming first event information into the first device, comparing the first event information to each event previously scheduled in the first device for determining conflicts therebetween, sending a message representing the first event information to the second device, comparing the first event information to each event previously scheduled in the second device for determining conflicts therebetween. A user may be provided with information regarding conflicts and may be notified that a password is required for the first event and the respective event timer is enabled in response to receiving the password entered into the first device.