Abstract: In the data read operation, a memory cell and a dummy memory cell are respectively coupled to two bit lines of a selected bit line pair, and a data read current is supplied thereto. In the selected memory cell column, a read gate drives the respective voltages on a read data bus pair, according to the respective voltages on the bit lines. A data read circuit amplifies the voltage difference between the read data buses so as to output read data. The use of the read gate enables the read data buses to be disconnected from a data read current path. As a result, respective voltage changes on the bit lines are rapidly produced, whereby the data read speed can be increased.

Abstract: A method for operating a memory cell of a multi-level NROM is described. The memory cell of the multi-level NROM comprises a nitride layer, wherein the nitride layer comprises a plurality of charge-trapping regions to store locally a plurality of charges as the first bit memory and the second bit of memory. The stored charges of the second bit of memory forms an electrical barrier, which in turns affects the size of the threshold electric current of the first bit. The different threshold electrical currents of the first bit, which are affected by the size of the electrical barrier, define the various memory states of the memory cell of the multi-level NROM.

Abstract: A method for erasing a non-volatile memory cell array, the method including applying an erase pulse to at least one bit of at least one memory cell of the array, erase verifying the at least one bit with a first erase verify level, and if the bit has passed the first erase verify level, applying at least one more erase pulse to the at least one bit.

Abstract: A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Abstract: A memory device and process for improving the state of one or more terminations according to process, voltage, and/or temperature variations. The memory device includes a delay locked-loop circuit (DLL). The memory device also has one or more terminations to which one or more variable resistance circuits are connected and through which one or more external signals are passed for operating the memory device, and a control circuit for generating a control signal for controlling one or more resistance values of the variable resistance circuits, in response to a command enable signal that represents the activation of another operation and an external enable signal that activates the DLL in the memory device. After the state of the one or more terminations is improved by the control signal, the DLL is enabled. While the memory device periodically performs the other operation, the state of the one or more terminations is improved by the control signal.

Abstract: A replaceable component of an apparatus includes a storage medium, wherein the storage medium is at least one of readable and writeable.

Abstract: A semiconductor integrated circuit includes a main memory unit, a redundancy memory unit and a redundancy information file unit, wherein at least a part of data that would otherwise be stored in the main memory is stored in the redundancy memory unit according to redundancy information stored in the redundancy information file unit, thereby secrecy of the data stored in this manner is enhanced.

Abstract: A semiconductor device comprising a semiconductor substrate, an insulating layer formed on the semiconductor substrate, input-output terminals, and a fuse block. A plurality of memory macros each having plurality of memory cells is arranged on the semiconductor substrate. The insulating layer, which has a window portion, may be formed on the semiconductor substrate and covering the memory macros, said insulating layer having a window portion. The input-output terminals are arranged inline along an edge portion of the surface of the insulating layer. The input-output terminals transmit and receive signals between the memory macros and a circuit external to the semiconductor device. The fuse block is arranged in a space corresponding to the window portion in the insulating layer. The fuse block may include a plurality of fuse elements used to remedy a defective memory cells in the memory macros.

Abstract: A data memory comprising a main data memory (2) consisting of a plurality of data memory units, a redundancy data memory (3) consisting of several redundancy data memory units which replace defective data memory units of the main data memory (2), and a redundancy control logic (4) which is used to control access to the redundancy data memory (4).

Abstract: The invention achieves a high speed access when shifting to an active mode from a standby mode, in particular immediately after shifting to a read, and reduces the current consumption at the time of standby. A strong charge pump generates 5.0V and a power supply voltage of 8.0V. The power supply voltage is supplied to constant voltage circuits. The constant voltage circuits generate voltages VPBL, VPYS, VPCGL, VPCGL, VPCGH and VPCGH, respectively, according to the respective read, program and erase operation modes. The constant voltage circuit that operates in active modes consumes a large amount of current when it supplies the voltage VPCGH. In contrast, the constant voltage circuit operates with a low current consumption and generates the voltage VPCGH in the standby mode.

Abstract: According to the multilevel programming method, each memory location can be programmed at a non-binary number of levels. The bits to be stored in the two locations are divided into two sets, wherein the first set defines a number of levels higher than the non-binary number of levels. During programming, if the first set of bits to be written corresponds to a number smaller than the non-binary number of levels, the first set of bits is written in the first location and the second set of bits is written in the second location; ifit is greater than the non-binary number of levels, the first set of bits is written in the second location and the second set of bits is written in the first location. The bits of the first set in the second location are stored in different levels with respect to the bits of the second set.

Abstract: A non-volatile memory device according to embodiments of the invention includes a page buffer acting as a sense amplifier during a read operation and as a write driver during a program operation. The page buffer has two sense and latch blocks, which exclusively carry out the same function. While one of the sense and latch blocks carries out a read operation, the other sense and latch block outputs previously sensed data to the exterior. Further, while one of the sense and latch blocks carries out a program operation, the other sense and latch block loads data to be programmed. Due to the page buffer, an operation speed of the non-volatile memory device can be enhanced.

Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.

Abstract: A sensing circuit comprises a sense amplifier adapted to receive an input signal from a memory cell and to provide a first output signal on a first output node. An output amplifier is adapted to receive the first output signal and to provide a second output signal on a second output node. The output amplifier comprises an output amplifier pre-charge transistor coupled between a first power supply node and a second output node. The output amplifier pre-charge transistor is adapted to pre-charge the second output node to approximately the first power supply potential.

Abstract: A VLSI layout editor and method for using same that increases display and re-display speed and accuracy uses properties inherent to VLSI layouts that allows them to be displayed efficiently and accurately independent of the canonical expression of the VLSI design. The VLSI layout editor and methods for using same use precomputed images that each represent a portion of the VLSI layout, a hierarchy cache that includes multiple LOD versions of selected sub-designs in the pre-computed images, and selected direct determination of the viewable representation from the canonical expression for at least one LOD. Apparatus and methods according to the present invention can render a particular type of data whose canonical form is smaller than its corresponding displayed image thereof when the displayed image has geometric properties that allow heuristics and rasterization for dynamic and accurate expansion using selected combined techniques.

Abstract: Methods and systems for automated memory test modeling generation and validation are provided. Information supplied by a graphical user interface is used to generate a customized memory primitive. The memory primitive subsequently undergoes a two phase validation to test for correct functioning.

Abstract: A semiconductor memory device employs a power supply system in which a first power supply voltage supplied to a cell area is separated from a second power supply voltage supplied to a peripheral circuit area. Particularly, during a wafer burn-in test operation mode, the first power supply voltage supplied to the cell area is higher than the second power supply voltage supplied to the peripheral circuit area. If a wafer burn-in test operation is performed under the second power supply system, a DC current path formed by a latch-up phenomenon of a memory cell can be shut off.

Abstract: A delay device is added to the addressing and refreshing circuitry of a DRAM array comprised of DRAM devices less volatile than conventional DRAM devices and, thus, need not be refreshed as often. The delay device is connected to intercept refresh signals generated by a conventional DRAM refresh controller and initiates a refresh cycle after disregarding a predetermined number of refresh signals generated by the refresh controller whose total duration equals the interval by which the less volatile DRAM devices must be refreshed. The delay device also is adapted to power off circuitry needed to address the DRAM devices when the DRAM devices are not being refreshed or otherwise accessed. Additional circuitry is added to selectively power on only specific addressing devices actually needed to address those certain portions of the array being refreshed at that time.

Abstract: A power saving circuit disables input buffers for command and address signals during an auto-refresh of a DRAM. The input buffers are re-enabled at the end of the auto-refresh in a manner that does not cause spurious commands to be generated. The power saving circuit prevents spurious commands by biasing internal command signals to a “no operation” command whenever the input buffers for the command signals are disabled. The DRAM may also be placed in a mode in which it automatically transitions to a low power precharge mode at the end of the auto-refresh to further reduce power consumed by the DRAM.

Abstract: An apparatus for a refresh and a data input device in the SRAM having a storage capacitor cell comprises an internal clock generator for generating and outputting two internal clock signals having a certain time difference of each other, a refresh timer for generating and outputting an output signal to notify a refresh time, a refresh signal generator for generating a refresh signal in response to a faster signal of the two internal signals and the output signal from the refresh timer, a refresh counter for generating refresh addresses during the refresh and a column path controller for controlling the activation of a column path in response to a row active signal and the refresh signal.

Abstract: An internal power supply potential generating circuit of a DRAM sets, at the time of a burn-in test, a first internal power supply potential for a wordline to an external power supply potential, maintains an internal power supply potential for a sense amplifier at an external reference potential, and maintains a second internal power supply potential for a peripheral circuit at a potential higher than the external reference potential only by a predetermined voltage. An early defect in a circuit portion to which the first internal power supply potential is applied and that in a circuit portion to which the second internal power supply potential is applied can be therefore accelerated separately from each other. Thus, a test efficiency is increased.

Abstract: A circuit for reducing power in SRAMS and DRAMS is implemented by dynamically controlling a voltage applied to individual memory sections of a semiconductor memory array. Individual sections of memory are isolated from a fixed power supply by inserting one or more PFETs between a fixed power supply and a positive connection, VDD, of an individual memory section. The voltage applied to each memory section is controlled by applying a separate variable voltage to each gate of all PFETs connected to a particular memory section. If a memory section is not accessed, the voltage to that section can be lowered, saving power. If a memory section is accessed, the voltage to that section may be raised, providing more power and shortening read and write times.

Abstract: A nonvolatile semiconductor memory device includes a plurality of banks including respective memory cell arrays independent of each other, a password storage area that is associated with one of the banks, a bank decoder which generates a bank selection signal by decoding a bank address, a first bank selection circuit which outputs a write instruction or a read instruction to the one of the banks, a plurality of second bank selection circuits which outputs a write instruction or a read instruction to the respective banks except for the one of the banks, and a command-decode-&-bank-control circuit which controls the first and second bank selection circuits such that receipt of a first command causes one of the first and second bank selection circuits selected by the bank selection signal to output a write instruction or a read instruction, and such that receipt of a second command causes the first bank selection circuit to output a write instruction independently of the bank selection signal, and causes one

Abstract: A semiconductor memory having ports, each of which conducts exclusively a writing or reading operation, by which the access operation can be speeded up when cells at the same row address are accessed simultaneously through two ports, is provided. A current-carrying capability of a write access transistor making up a memory cell is lowered relative to a current-carrying capability of a read access transistor within a range capable of finishing the writing operation.

Abstract: An address decoder having pre-decode logic circuitry positioned in between ends of final decode logic circuitry is provided. Such an address decoder yields less wire load, less gate load, less power consumption, and increased speed due to the pre-decode logic circuitry having to be capable of only driving a signal over half the length of a final decoder. Further, a method to select memory elements from a memory array using centrally positioned pre-decode logic circuitry is provided.

Abstract: A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous flash memory device, in one embodiment, has a command interface comprising a write enable connection (WE#) to receive a write enable signal, a column address strobe connection (CAS#) to receive a column address strobe signal, a row address strobe connection (RAS#) to receive a row address strobe signal. A command operation is initiated in response to a sequence of ACTIVE/WRITE and/or ACTIVE/READ commands provided on the WE#, CAS# and RAS# connections.

Abstract: A method and apparatus is provided for selecting a memory device or a group of memory devices in a memory system using dedicated bank select signals in combination with encoded chip selection signals. A memory controller transmits bank select signals over bank select signal lines and encoded chip select signals on the command and address bus which are used to select an individual memory device or group of memory devices in a bank for an operation.

Abstract: Over-the-road concrete mixer motor trucks with rotatable concrete mixer drums have indicia placed on the drums comprising advertisements of a product or service, and which may be readable from opposite sides of the motor truck as it traverses a roadway. In alternate embodiments, indicia on the rotatable mixer drum is placed in a helical or spiral fashion or simulates the appearance of an article other than the drum itself.

Abstract: Systems and methods for weighing and charging components of a product using a radio-frequency order picking and inventory control system (ROPICS) are disclosed. A system according to the invention can include a server computer having a back-end database for storing inventory data, a client computer that is communicatively coupled to the server computer via a communications network, and a scale for providing to the client computer a weight signal that represents an actual weight of a component on the scale. The server computer includes a data queue for receiving and managing database transaction requests in real-time, and a transaction server for receiving the database transaction requests from the data queue and for interfacing with back-end database to process the received database transaction requests in real-time.

Abstract: A portable mixing/delivery apparatus mixes dry pre-blended materials, such as homogeneous cementitious combinations of dry sand, cement, lime, color pigments, etc., packaged in large bulk bags for use at a remote construction site. The bulk bag is lifted by a removable rack having plural lift eyes and the combination is positioned over a height adjustable frame. The granular material is then discharged into a continuous mixer having a dynamic input mixing stage, an output dry-to-wet mixing stage, and a transition stage therebetween. The enter assembly (bulk bag, frame and continuous mixer) is portable and can be lifted such as by a forklift to the height of a masonry scaffold for dispensing the mixed, wet granular material directly to the point of use. The apparatus allows the continuous mixer and its discharge tube to rotate to facilitate dispensing of the material directly to the point of use.

Abstract: An improved paint mixer is disclosed which includes a base and an upper cabinet pivotally connected to the base. The upper cabinet can be pivoted from a first rearward position which provides access to a front section of the base and a second forward position which provides access to a rear section of the base. As a result, both the front and rear section of the base are easily accessible for service, maintenance, and cleaning. A support system that includes three adjustable legs provides improved support and stability. Casters disclosed at the rear end of the bottom of the base along with a recessed wall of the base and a handle disposed at the front of the base make it easier to move and/or relocate the mixer. Non-stick coatings in the form of a paint-resistant coating or an anti-graffiti coating to the inside surfaces of the mixer facilitate the removal of accumulated paint.

Abstract: A household appliance, in particular, a kitchen machine, includes a planetary gear disposed between an electric drive unit and an output shaft or drive shaft of the appliance and the stationary toothed ring of which is supported on the housing of the appliance by support arms (13) projecting radially outwardly on the outer circumference of the toothed ring. Good damping of the noise originating from the planetary gear is achieved by virtue of the fact that an elastic element preventing direct contact between the support arms and the fixing locations is respectively inserted between the support arms and the fixing locations on the housing.

Abstract: A method of seismic imaging a subsurface formation using an array of seismic sources and an array of seismic receivers located subsurface, wherein there is a complex transmission medium between the two sets by creating a virtual source at a selected receiver within the array, time-reversing a portion of the signal related to the selected source and receiver and convolving the time-reversed portion of the signal with the signal at adjoining receivers within the array and repeating the process for signals attributable to various surface sources to create a seismic image of a target formation.

Abstract: A system and method of creating a filter for use with locally dense seismic data is disclosed. The method includes obtaining survey geometry characteristics from a locally dense seismic survey. A filter is designed which uses spatial derivatives of the wavefield of order between (1) and the maximum order of spatial derivatives of the wavefield that can be estimated within a group. The filter can be designed so as to separate up/down going components, p/s components, or both up/down and p/s components. Partial derivatives in space and time of the wavefield can be calculated, using, for example, a taylor series expansion as an approximation. The seismic data is filtered by combining estimated near surface material properties, the seismic data, and the calculated partial derivatives.

Abstract: An improved acoustic Doppler flow measurement system which employs multiple acoustic frequencies to acquire multiple independent backscatter data from the flow channel, combining the data to enable survey measurement of channel flow properties beyond what can be achieved with either a single frequency system or multiple independent single frequency systems. The system is installed on small moving channel survey boats, remotely measuring vertical profiles of river currents, achieving accurate surveys of channel flow velocity structure and bottom topography, enabling accurate (approximately 1% resolution) survey measurement of channel flow discharge. Significant synergistic improvements are realized from both physical and functional integrations of the multi-frequency operational capability into a single integrated flow survey system. Use of phased array transducer techniques further reduces flow disturbance and transducer size, enabling use on even smaller survey boats.

Abstract: Geometry, polarity of the exciting electrodes, and stray capacitance effect the performance of the thickness-shear mode acoustic wave sensor operating in electrolytes and solutions of biomolecules. In contrast to the mass-based response of the device operating in the gas phase, the response in a liquid is governed by factors including acoustoelectric, and fringing field effects, which are known to be active at the edges of the electrodes. The invention relates to an electrode having modified geometry to increase the edge length to raise the sensitivity of the device, and to enhance the sensor response.

Abstract: A monitoring apparatus for use with an electrical appliance to record and display the electrical appliance's actual accumulated operating time and record and display the number of times the electrical appliance has been energized since the time the monitoring apparatus was installed or last reset. The monitoring apparatus may include a current detector, a time recorder, and a counter for detecting and recording operation time and number of start-ups.

Abstract: A combination clock radio, weather station and message organizer includes a base unit having a visual display, a controller located in the base unit including a central processor for controlling operation of the combination, and a temperature sensor for obtaining outdoor temperature readings, the temperature sensor being in communication with the controller. The controller is adapted to present a hue on the visual display that is a function of the outdoor temperature reading. The combination may also include a pressure sensor in communication with the controller for monitoring a rate of change in atmospheric pressure and providing a weather forecast animation that is a function of the changes in the atmospheric pressure.

Abstract: A method for maintaining the accuracy of time while viewing the standard hour, minute and seconds in a direction counter-clockwise to that of all normal clocks and/or watches, comprising the steps of setting the clock time on the normal correct hour and minute initially, with subsequent observation of movement of both the Hour hand, Minute hand and seconds indicator moving from a 12 O'Clock position towards the left positioning of each subsequent chronological time indicating feature, i.e. 1 O'Clock Hour position Mark and back to the 12 O'Clock Hour position mark in a continuous counter-clockwise time-keeping motion. The design of this clock complies with the requirements of a single claim as defined in 37 CFR □ 1.153 and the patent is requested to protect the utility of this article under (35 U.S.C. 101) and its ornamental looks under (35 U.S.C. 171).

Abstract: A time-error-compensating apparatus and method corrects errors in a real-time clock caused by temperature fluctuations or other external influences. The apparatus includes a frequency counting unit which counts a high-frequency clock signal and a low-frequency clock signal, and a time compensating unit which computes a clock count compensation value based on a comparison of the count values of of the low-frequency and high-frequency clock signals. Correcting time using a high-frequency clock is highly desirable because a clock of this type has proven to be accurate in high external stress conditions. Use of this clock also allows the real-time clock to be implemented as a low-frequency, inexpensive low-frequency clock. The method and apparatus are well suited to correcting time information in the terminals of a mobile communications system, or in any other system or device where time tracking is sought.

Abstract: Automatic watches use the movements of the wrist to re-wind the barrel spring and thus supply the necessary energy for the correct functioning of the watch. When the user cannot wear the watch it is proposed to place it on an automatic re-winding device. The device according to the invention is compact and modular. Furthermore, in order to avoid any error of manipulation, the starting and stopping of the re-winding device is done automatically by means of a detection of the presence of the watch (3). The passing of the strap in the detachable base (2) produces the tension of the device.

Abstract: A recording and/or reproducing apparatus includes a base member at least having a rotation driving mechanism for rotationally driving a disc housed in a disc cartridge, a holder into which is inserted the disc cartridge and an ejection lever formed by an elastically flexible lever. The holder is mounted for movement between a first position in which the disc inserted in the disc cartridge is loaded on the rotation driving mechanism and a second position in which the disc housed in the disc cartridge is spaced apart from the rotation driving mechanism. The second position is higher in level than the first position. The ejection lever is elastically flexed by the disc cartridge inserted into the holder from a position protruded into the holder to the position extending along the back side of the holder. When elastically flexed to the position extending along the back surface of the holder, the ejection lever is engaged with the holder moved to the first position.

Abstract: The present invention relates to a head arrangement for reading a magneto-optical recording medium (10) comprising a storage layer and a read-out layer. The head arrangement comprises an improved field generating means for generating a magnetic field used for copying a written mark from said storage layer to said read-out layer upon laser heating, the field generating means being arranged to generate a predetermined field gradient and/or a predetermined local maximum in a field component perpendicular to the surface of the recording medium (10). The width of the spatial overlap can thus be reduced such that an improved resolution and/or power marginis obtained.

Abstract: An information playback apparatus is provided, which can provide a sound which sounds natural by controlling an abrupt change in a tempo in the case of random access playback. When a cue point is registered, audio data which makes seamless playback possible is stored into a cue point memory, and further, the beat density of a playback sound being played when the cue point is registered is measured and stored. When the cue point is specified to start random access playback later, a ratio of the beat density (&agr;×DBPM) of a playback sound being played when the cue point is specified and the beat density (DBPMreg) stored in advance is found. Then, the random access playback is started after the beat density of a playback sound to be played after random access playback is started is corrected to be equal to the beat density when a start of the random access playback is specified.

Abstract: An apparatus for handling, storing and reloading carriers for disk-shaped items, such as semiconductor wafers or CDs, has at least one cleaning unit and at least one storage unit for the carriers containing the disk-shaped items. The apparatus further has at least one sorting unit for the disk-shaped items. The cleaning unit, the storage unit and the sorting apparatus are integral component parts of the apparatus and are operated by a common automatic control.

Abstract: A method of displacing a media holder assembly of a media autochanger between a first rotational registration position and a second rotational registration position.

Abstract: An optical disk device in which the laser beam emitted from a laser light source and deflected by a movable mirror is focused on an optical recording medium by an optical head section. Tracking control is carried out by a drive control section based on the laser beam reflected from the optical recording medium. A micro electrical mechanical system incorporating the movable mirror is housed in a package accommodating the laser light source. The movable mirror is driven by electrostatic force at a frequency of 0.5 KHz or higher.

Abstract: The present invention discloses an apparatus for controlling a layer jump process of an optical drive. The layer jump control apparatus has a pick up head having a lens and a voice coil motor, a preamplifier for producing a focusing error signal, a controller for receiving the focusing error signal and producing a focusing control signal, a low pass filter for receiving the focusing control signal and producing a layer distance balancing signal, and a driving device to send a driving force to the pick up head.

Abstract: An optical system of an optical recording apparatus forms a main spot and sub-spots preceding and succeeding the main spot on a signal recording medium. The optical system is set such that the sub-spot is shifted from the main spot in the direction orthogonal to a signal track by a distance expressed by an expression (2k−1) P/4 (k=natural number), in which P denotes a distance between adjacent signal tracks on the signal recording medium. Thus, the sub-spot succeeding the main spot can be used to effectively read the state of a signal recorded on the signal recording medium by the main spot.

Abstract: In a reproducing apparatus of the present invention, an input audio signal is divided into bands and an envelope value of each band is measured. Based on a change of the envelope value, a predetermined sound source is superimposed. Further, according to the envelope value of a reproduced audio signal, a tempo of reproduced music is detected and animation representation is changed in synchronism with the detected tempo. Further, a rhythm box is reproduced in synchronism with the detected tempo and a sound field is automatically selected corresponding to the detected tempo to perform synthesization.